Bin Meng e61a2687b3 x86: braswell: Add microcode for B0/C0/D0 stepping SoC ... This adds microcode device tree fragment for Braswell B0 (406C2), C0 (406C3) and D0 (406C4) stepping SoC. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>		2017-09-16 14:57:44 +08:00
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cpu	x86: Add Intel Braswell SoC support	2017-09-16 14:57:44 +08:00
dts	x86: braswell: Add microcode for B0/C0/D0 stepping SoC	2017-09-16 14:57:44 +08:00
include/asm	x86: Add Intel Braswell SoC support	2017-09-16 14:57:44 +08:00
lib	x86: fsp: Update fsp command to show spec 1.1 header	2017-09-16 14:57:44 +08:00
config.mk	x86: Enforce toolchain to generate 64-bit codes for 64-bit U-Boot	2017-08-01 20:17:02 +08:00
Kconfig	x86: Add Intel Braswell SoC support	2017-09-16 14:57:44 +08:00
Makefile	x86: Add 64-bit start-up code	2017-02-06 11:38:46 +08:00