c05ed00afb
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
218 lines
6.4 KiB
C
218 lines
6.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2001 Navin Boppuri / Prashant Patel
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* <nboppuri@trinetcommunication.com>,
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* <pmpatel@trinetcommunication.com>
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* Copyright (c) 2001 Gerd Mennchen <Gerd.Mennchen@icn.siemens.de>
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* Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>.
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*/
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/*
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* MPC8xx CPM SPI interface.
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*
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* Parts of this code are probably not portable and/or specific to
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* the board which I used for the tests. Please send fixes/complaints
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* to wd@denx.de
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*
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*/
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#include <common.h>
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#include <dm.h>
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#include <mpc8xx.h>
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#include <spi.h>
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#include <linux/delay.h>
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#include <asm/cpm_8xx.h>
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#include <asm/io.h>
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#define CPM_SPI_BASE_RX CPM_SPI_BASE
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#define CPM_SPI_BASE_TX (CPM_SPI_BASE + sizeof(cbd_t))
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#define MAX_BUFFER 0x104
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static int mpc8xx_spi_probe(struct udevice *dev)
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{
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immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
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cpm8xx_t __iomem *cp = &immr->im_cpm;
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spi_t __iomem *spi = (spi_t __iomem *)&cp->cp_dparam[PROFF_SPI];
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cbd_t __iomem *tbdf, *rbdf;
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/* Disable relocation */
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out_be16(&spi->spi_rpbase, 0);
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/* 1 */
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/* ------------------------------------------------
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* Initialize Port B SPI pins -> page 34-8 MPC860UM
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* (we are only in Master Mode !)
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* ------------------------------------------------ */
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/* --------------------------------------------
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* GPIO or per. Function
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* PBPAR[28] = 1 [0x00000008] -> PERI: (SPIMISO)
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* PBPAR[29] = 1 [0x00000004] -> PERI: (SPIMOSI)
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* PBPAR[30] = 1 [0x00000002] -> PERI: (SPICLK)
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* PBPAR[31] = 0 [0x00000001] -> GPIO: (CS for PCUE/CCM-EEPROM)
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* -------------------------------------------- */
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clrsetbits_be32(&cp->cp_pbpar, 0x00000001, 0x0000000E); /* set bits */
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/* ----------------------------------------------
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* In/Out or per. Function 0/1
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* PBDIR[28] = 1 [0x00000008] -> PERI1: SPIMISO
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* PBDIR[29] = 1 [0x00000004] -> PERI1: SPIMOSI
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* PBDIR[30] = 1 [0x00000002] -> PERI1: SPICLK
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* PBDIR[31] = 1 [0x00000001] -> GPIO OUT: CS for PCUE/CCM-EEPROM
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* ---------------------------------------------- */
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setbits_be32(&cp->cp_pbdir, 0x0000000F);
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/* ----------------------------------------------
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* open drain or active output
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* PBODR[28] = 1 [0x00000008] -> open drain: SPIMISO
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* PBODR[29] = 0 [0x00000004] -> active output SPIMOSI
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* PBODR[30] = 0 [0x00000002] -> active output: SPICLK
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* PBODR[31] = 0 [0x00000001] -> active output GPIO OUT: CS for PCUE/CCM
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* ---------------------------------------------- */
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clrsetbits_be16(&cp->cp_pbodr, 0x00000007, 0x00000008);
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/* Initialize the parameter ram.
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* We need to make sure many things are initialized to zero
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*/
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out_be32(&spi->spi_rstate, 0);
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out_be32(&spi->spi_rdp, 0);
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out_be16(&spi->spi_rbptr, 0);
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out_be16(&spi->spi_rbc, 0);
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out_be32(&spi->spi_rxtmp, 0);
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out_be32(&spi->spi_tstate, 0);
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out_be32(&spi->spi_tdp, 0);
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out_be16(&spi->spi_tbptr, 0);
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out_be16(&spi->spi_tbc, 0);
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out_be32(&spi->spi_txtmp, 0);
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/* 3 */
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/* Set up the SPI parameters in the parameter ram */
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out_be16(&spi->spi_rbase, CPM_SPI_BASE_RX);
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out_be16(&spi->spi_tbase, CPM_SPI_BASE_TX);
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/***********IMPORTANT******************/
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/*
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* Setting transmit and receive buffer descriptor pointers
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* initially to rbase and tbase. Only the microcode patches
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* documentation talks about initializing this pointer. This
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* is missing from the sample I2C driver. If you dont
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* initialize these pointers, the kernel hangs.
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*/
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out_be16(&spi->spi_rbptr, CPM_SPI_BASE_RX);
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out_be16(&spi->spi_tbptr, CPM_SPI_BASE_TX);
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/* 4 */
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/* Init SPI Tx + Rx Parameters */
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while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG)
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;
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out_be16(&cp->cp_cpcr, mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) |
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CPM_CR_FLG);
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while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG)
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;
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/* 5 */
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/* Set SDMA configuration register */
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out_be32(&immr->im_siu_conf.sc_sdcr, 0x0001);
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/* 6 */
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/* Set to big endian. */
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out_8(&spi->spi_tfcr, SMC_EB);
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out_8(&spi->spi_rfcr, SMC_EB);
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/* 7 */
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/* Set maximum receive size. */
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out_be16(&spi->spi_mrblr, MAX_BUFFER);
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/* 8 + 9 */
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/* tx and rx buffer descriptors */
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tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
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rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
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clrbits_be16(&tbdf->cbd_sc, BD_SC_READY);
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clrbits_be16(&rbdf->cbd_sc, BD_SC_EMPTY);
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/* 10 + 11 */
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out_8(&cp->cp_spim, 0); /* Mask all SPI events */
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out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */
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return 0;
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}
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static int mpc8xx_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
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cpm8xx_t __iomem *cp = &immr->im_cpm;
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cbd_t __iomem *tbdf, *rbdf;
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int tm;
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size_t count = (bitlen + 7) / 8;
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if (count > MAX_BUFFER)
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return -EINVAL;
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tbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_TX];
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rbdf = (cbd_t __iomem *)&cp->cp_dpmem[CPM_SPI_BASE_RX];
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/* Set CS for device */
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clrbits_be32(&cp->cp_pbdat, 0x0001);
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/* Setting tx bd status and data length */
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out_be32(&tbdf->cbd_bufaddr, (ulong)dout);
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out_be16(&tbdf->cbd_sc, BD_SC_READY | BD_SC_LAST | BD_SC_WRAP);
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out_be16(&tbdf->cbd_datlen, count);
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/* Setting rx bd status and data length */
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out_be32(&rbdf->cbd_bufaddr, (ulong)din);
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out_be16(&rbdf->cbd_sc, BD_SC_EMPTY | BD_SC_WRAP);
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out_be16(&rbdf->cbd_datlen, 0); /* rx length has no significance */
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clrsetbits_be16(&cp->cp_spmode, ~SPMODE_LOOP, SPMODE_REV | SPMODE_MSTR |
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SPMODE_EN | SPMODE_LEN(8) | SPMODE_PM(0x8));
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out_8(&cp->cp_spim, 0); /* Mask all SPI events */
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out_8(&cp->cp_spie, SPI_EMASK); /* Clear all SPI events */
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/* start spi transfer */
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setbits_8(&cp->cp_spcom, SPI_STR); /* Start transmit */
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/* --------------------------------
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* Wait for SPI transmit to get out
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* or time out (1 second = 1000 ms)
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* -------------------------------- */
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for (tm = 0; tm < 1000; ++tm) {
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if (in_8(&cp->cp_spie) & SPI_TXB) /* Tx Buffer Empty */
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break;
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if ((in_be16(&tbdf->cbd_sc) & BD_SC_READY) == 0)
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break;
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udelay(1000);
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}
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if (tm >= 1000)
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printf("*** spi_xfer: Time out while xferring to/from SPI!\n");
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/* Clear CS for device */
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setbits_be32(&cp->cp_pbdat, 0x0001);
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return count;
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}
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static const struct dm_spi_ops mpc8xx_spi_ops = {
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.xfer = mpc8xx_spi_xfer,
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};
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static const struct udevice_id mpc8xx_spi_ids[] = {
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{ .compatible = "fsl,mpc8xx-spi" },
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{ }
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};
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U_BOOT_DRIVER(mpc8xx_spi) = {
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.name = "mpc8xx_spi",
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.id = UCLASS_SPI,
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.of_match = mpc8xx_spi_ids,
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.ops = &mpc8xx_spi_ops,
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.probe = mpc8xx_spi_probe,
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};
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