maxims@google.com d5ce357461 aspeed: ast2500: Fix H-PLL and M-PLL clock rate calculation ... Fix H-PLL and M-PLL rate calculation in ast2500 clock driver. Without this fix, valid setting can lead to division by zero when requesting the rate of H-PLL or M-PLL clocks. Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>		2017-02-08 15:56:30 -05:00
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aspeed	aspeed: ast2500: Fix H-PLL and M-PLL clock rate calculation	2017-02-08 15:56:30 -05:00
at91	clk: at91: Improve the clock implementation	2016-10-28 18:37:14 +02:00
exynos	clk: convert API to match reset/mailbox style	2016-06-19 17:05:55 -06:00
rockchip	rockchip: clk: Support setting ACLK	2016-11-25 17:59:31 -07:00
tegra	clock: implement a driver for the Tegra CAR	2016-09-27 09:11:02 -07:00
uniphier	clk: uniphier: fix compatible strings for Pro5, PXs2, LD20 SD clock	2017-01-29 20:59:08 +09:00
clk_boston.c	clk: boston: Providea simple driver for Boston board clocks	2016-09-21 15:04:32 +02:00
clk_fixed_rate.c	dm: clk: Add support for of-platdata	2016-07-14 20:40:24 -06:00
clk_pic32.c	clk: convert API to match reset/mailbox style	2016-06-19 17:05:55 -06:00
clk_sandbox_test.c	clk: convert API to match reset/mailbox style	2016-06-19 17:05:55 -06:00
clk_sandbox.c	clk: sandbox: don't check clk ID against 0	2016-06-24 17:24:35 -04:00
clk_zynqmp.c	clk: zynqmp: Add clock driver support for zynqmp	2017-01-10 10:18:12 +01:00
clk-uclass.c	clk: clk-uclass: Assign clk->dev before call .of_xlate	2016-10-28 18:37:14 +02:00
Kconfig	clk: zynqmp: Add clock driver support for zynqmp	2017-01-10 10:18:12 +01:00
Makefile	aspeed: Add basic ast2500-specific drivers and configuration	2017-01-28 14:04:29 -05:00