4eaf7f525a
Workaround makes FS as default mode on all affected socs.
Add support to check erratum-A005275 validity for an soc. This info is
required to determine whether a given soc is affected by this erratum.
Add quirk for this erratum "has_fsl_erratum_a005275" . This quirk is used
to enable workaround for the errata
Force FS mode as default by:
- making EPS as FS
- setting PFSC bit to disable HS chirping
This workaround can be disabled by mentioning "no_erratum_a005275" in
hwconfig string
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
101 lines
2.7 KiB
C
101 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Freescale USB Controller
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*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*/
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#ifndef _ASM_FSL_USB_H_
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#define _ASM_FSL_USB_H_
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#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
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struct ccsr_usb_port_ctrl {
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u32 ctrl;
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u32 drvvbuscfg;
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u32 pwrfltcfg;
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u32 sts;
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u8 res_14[0xc];
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u32 bistcfg;
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u32 biststs;
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u32 abistcfg;
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u32 abiststs;
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u8 res_30[0x10];
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u32 xcvrprg;
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u32 anaprg;
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u32 anadrv;
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u32 anasts;
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};
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struct ccsr_usb_phy {
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u32 id;
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struct ccsr_usb_port_ctrl port1;
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u8 res_50[0xc];
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u32 tvr;
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u32 pllprg[4];
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u8 res_70[0x4];
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u32 anaccfg;
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u32 dbg;
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u8 res_7c[0x4];
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struct ccsr_usb_port_ctrl port2;
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u8 res_dc[0x334];
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};
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#define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0)
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#define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1)
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#define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1)
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#define CONFIG_SYS_FSL_USB_PLLPRG1_PHY_DIV (1 << 0)
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#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0)
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#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1)
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#define CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN (1 << 13)
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#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
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#define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK (5 << 4)
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#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK (6 << 16)
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#define CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN (1 << 20)
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#endif
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#define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 << 4)
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#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
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#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
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#define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0)
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#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN (1 << 7)
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#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK (3 << 4)
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#define INC_DCNT_THRESHOLD_25MV (0 << 4)
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#define INC_DCNT_THRESHOLD_50MV (1 << 4)
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#define DEC_DCNT_THRESHOLD_25MV (2 << 4)
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#define DEC_DCNT_THRESHOLD_50MV (3 << 4)
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#else
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struct ccsr_usb_phy {
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u32 config1;
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u32 config2;
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u32 config3;
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u32 config4;
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u32 config5;
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u32 status1;
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u32 usb_enable_override;
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u8 res[0xe4];
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};
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#define CONFIG_SYS_FSL_USB_HS_DISCNCT_INC (3 << 22)
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#define CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL (1 << 20)
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#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0 13
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#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3 16
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#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0 0
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#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3 3
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#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
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#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK 0x07
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#endif
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/* USB Erratum Checking code */
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#if defined(CONFIG_PPC) || defined(CONFIG_ARM)
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bool has_dual_phy(void);
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bool has_erratum_a005275(void);
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bool has_erratum_a006261(void);
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bool has_erratum_a007075(void);
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bool has_erratum_a007798(void);
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bool has_erratum_a007792(void);
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bool has_erratum_a005697(void);
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bool has_erratum_a004477(void);
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bool has_erratum_a008751(void);
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bool has_erratum_a010151(void);
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#endif
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#endif /*_ASM_FSL_USB_H_ */
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