c2ae7d8220
Move the SPL settings into common/spl where most of the SPL code is kept. Signed-off-by: Simon Glass <sjg@chromium.org>
70 lines
1.5 KiB
Plaintext
70 lines
1.5 KiB
Plaintext
CONFIG_ARM=y
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CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
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CONFIG_ARCH_ZYNQMP=y
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CONFIG_SYS_MALLOC_F_LEN=0x8000
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CONFIG_ZYNQMP_USB=y
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CONFIG_SYS_TEXT_BASE=0x8000000
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CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102"
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_SPL_LOAD_FIT=y
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CONFIG_SPL=y
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CONFIG_SPL_SYS_MALLOC_SIMPLE=y
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CONFIG_HUSH_PARSER=y
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CONFIG_SYS_PROMPT="ZynqMP> "
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# CONFIG_CMD_IMLS is not set
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CONFIG_CMD_MEMTEST=y
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_MMC=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_DFU=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_TFTPPUT=y
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_TIME=y
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CONFIG_CMD_TIMER=y
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_EXT4_WRITE=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_OF_EMBED=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_SPL_DM=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_BLK=y
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CONFIG_DM_GPIO=y
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CONFIG_DM_MMC=y
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CONFIG_DM_MMC_OPS=y
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CONFIG_ZYNQ_SDHCI=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_BAR=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_WINBOND=y
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CONFIG_DM_ETH=y
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CONFIG_ZYNQ_GEM=y
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CONFIG_DEBUG_UART=y
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CONFIG_DEBUG_UART_ZYNQ=y
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CONFIG_DEBUG_UART_BASE=0xff000000
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CONFIG_DEBUG_UART_CLOCK=100000000
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CONFIG_DEBUG_UART_ANNOUNCE=y
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CONFIG_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_XHCI_DWC3=y
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CONFIG_USB_DWC3=y
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CONFIG_USB_DWC3_GADGET=y
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CONFIG_USB_ULPI_VIEWPORT=y
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CONFIG_USB_ULPI=y
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CONFIG_USB_STORAGE=y
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CONFIG_USB_GADGET=y
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CONFIG_USB_GADGET_DOWNLOAD=y
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CONFIG_G_DNL_MANUFACTURER="Xilinx"
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CONFIG_G_DNL_VENDOR_NUM=0x03FD
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CONFIG_G_DNL_PRODUCT_NUM=0x0300
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CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
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