067f54c66a
This patch is in preparation for the upcoming PLU405 board fix. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
61 lines
1.4 KiB
C
61 lines
1.4 KiB
C
/*
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* Copyright 2009, Matthias Fuchs <matthias.fuchs@esd.eu>
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*
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* SJA1000 register layout for basic CAN mode
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _SJA1000_H_
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#define _SJA1000_H_
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/*
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* SJA1000 register layout in basic can mode
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*/
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struct sja1000_basic_s {
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u8 cr;
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u8 cmr;
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u8 sr;
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u8 ir;
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u8 ac;
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u8 am;
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u8 btr0;
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u8 btr1;
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u8 oc;
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u8 txb[10];
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u8 rxb[10];
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u8 unused;
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u8 cdr;
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};
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/* control register */
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#define CR_RR 0x01
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/* output control register */
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#define OC_MODE0 0x01
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#define OC_MODE1 0x02
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#define OC_POL0 0x04
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#define OC_TN0 0x08
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#define OC_TP0 0x10
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#define OC_POL1 0x20
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#define OC_TN1 0x40
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#define OC_TP1 0x80
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#endif
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