acf3f8da98
The P2040/P2040E have no L2 cache. So we utilize the SVR to determine if we are one of these devices and skip the L2 init code in cpu_init.c and release. For the device tree we skip the updating of the L2 cache properties but we still update the chain of caches so the CPC/L3 node can be properly updated. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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arm | ||
avr32 | ||
blackfin | ||
m68k | ||
microblaze | ||
mips | ||
nios2 | ||
powerpc | ||
sh | ||
sparc | ||
x86 | ||
.gitignore |