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u-boot/arch/mips
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Paul Burton c5b8412d60 MIPS: Ensure Config.K0=2 applies before any memory accesses 
During boot we set Config.K0=2 (uncached) such that any accesses to the
kseg0 memory region are performed uncached before the caches are
initialised. This write to the Config register introduces an execution
hazard between it & any following memory accesses (such as the load of
_gp), which we need to clear in order to ensure those memory accesses
are actually performed uncached. Clear this execution hazard with the
insertion of an ehb execution hazard barrier instruction.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
..
cpu MIPS: Ensure Config.K0=2 applies before any memory accesses 2016-09-21 15:04:04 +02:00
dts mips: xilfpga: Add device tree files 2016-09-21 14:55:14 +02:00
include/asm MIPS: Join the coherent domain when a CM is present 2016-09-21 15:04:04 +02:00
lib MIPS: Join the coherent domain when a CM is present 2016-09-21 15:04:04 +02:00
mach-ath79 MIPS: ath79: Use mach_cpu_init instead of arch_cpu_init 2016-09-21 15:04:04 +02:00
mach-au1x00 net: mii: Use spatch to update miiphy_register 2016-08-15 15:26:33 -05:00
mach-pic32 clk: convert API to match reset/mailbox style 2016-06-19 17:05:55 -06:00
config.mk MIPS: provide a default u-boot-spl.lds 2016-05-31 09:38:11 +02:00
Kconfig MIPS: Malta: Enable CM & L2 support 2016-09-21 15:04:04 +02:00
Makefile MIPS: add tune for MIPS 34kc 2016-05-31 09:38:11 +02:00