afc1ce8288
Documents and READMEs for NDS32 architecture. It patch also provides usage of SoC AG101 and board ADP-AG101. Signed-off-by: Macpaul Lin <macpaul@andestech.com>
56 lines
1.4 KiB
Plaintext
56 lines
1.4 KiB
Plaintext
N1213 is a configurable hard/soft core of NDS32's N12 CPU family.
|
|
|
|
Features
|
|
========
|
|
|
|
CPU Core
|
|
- 16-/32-bit mixable instruction format.
|
|
- 32 general-purpose 32-bit registers.
|
|
- 8-stage pipeline.
|
|
- Dynamic branch prediction.
|
|
- 32/64/128/256 BTB.
|
|
- Return address stack (RAS).
|
|
- Vector interrupts for internal/external.
|
|
interrupt controller with 6 hardware interrupt signals.
|
|
- 3 HW-level nested interruptions.
|
|
- User and super-user mode support.
|
|
- Memory-mapped I/O.
|
|
- Address space up to 4GB.
|
|
|
|
Memory Management Unit
|
|
- TLB
|
|
- 4/8-entry fully associative iTLB/dTLB.
|
|
- 32/64/128-entry 4-way set-associati.ve main TLB.
|
|
- TLB locking support
|
|
- Optional hardware page table walker.
|
|
- Two groups of page size support.
|
|
- 4KB & 1MB.
|
|
- 8KB & 1MB.
|
|
|
|
Memory Subsystem
|
|
- I & D cache.
|
|
- Virtually indexed and physically tagged.
|
|
- Cache size: 8KB/16KB/32KB/64KB.
|
|
- Cache line size: 16B/32B.
|
|
- Set associativity: 2-way, 4-way or direct-mapped.
|
|
- Cache locking support.
|
|
- I & D local memory (LM).
|
|
- Size: 4KB to 1MB.
|
|
- Bank numbers: 1 or 2.
|
|
- Optional 1D/2D DMA engine.
|
|
- Internal or external to CPU core.
|
|
|
|
Bus Interface
|
|
- Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports.
|
|
- Synchronous High speed memory port.
|
|
(HSMP): 0, 1 or 2 ports.
|
|
|
|
Debug
|
|
- JTAG debug interface.
|
|
- Embedded debug module (EDM).
|
|
- Optional embedded program tracer interface.
|
|
|
|
Miscellaneous
|
|
- Programmable data endian control.
|
|
- Performance monitoring mechanism.
|