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c40b6df87f
u-boot/drivers/clk
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Anup Patel c40b6df87f clk: Add SiFive FU540 PRCI clock driver 
Add driver code for the SiFive FU540 PRCI IP block.  This IP block
handles reset and clock control for the SiFive FU540 device and
implements SoC-level clock tree controls and dividers.

Based on code written by Wesley Terpstra <wesley@sifive.com>
found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of:
https://github.com/riscv/riscv-linux

Boot and PLL rate change were tested on a SiFive HiFive Unleashed
board.

Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
2019-02-27 09:12:33 +08:00
..
altera clk: Remove DM_FLAG_PRE_RELOC flag in various drivers 2018-11-14 09:16:28 -08:00
aspeed aspeed: ast2500: fix D2-PLL clock setting in RGMII mode 2018-11-05 10:41:58 -06:00
at91 clk: at91: utmi: add timeout for utmi lock 2018-08-13 14:03:57 -04:00
exynos clk: Remove DM_FLAG_PRE_RELOC flag in various drivers 2018-11-14 09:16:28 -08:00
imx clk: imx8: fix build warning 2019-01-09 17:03:29 +01:00
mediatek clk: MediaTek: bind ethsys reset controller 2019-01-14 17:43:18 -05:00
mvebu clk: armada-37xx-periph: Support changing clock parent and rate 2018-09-19 08:59:26 +02:00
owl clk: Remove DM_FLAG_PRE_RELOC flag in various drivers 2018-11-14 09:16:28 -08:00
renesas clk: renesas: Allow reconfiguring SDHI clock on Gen3 2018-12-03 12:51:16 +01:00
rockchip rockchip: clk: Add mention of four new clocks 2019-02-01 16:59:13 +01:00
sifive clk: Add SiFive FU540 PRCI clock driver 2019-02-27 09:12:33 +08:00
sunxi sunxi: clk: enable clk and reset for CCU devices 2019-01-30 18:21:35 +05:30
tegra drivers: cosmetic: Convert SPDX license tags to Linux Kernel style 2018-10-28 09:26:39 -04:00
uniphier clk: uniphier: add NAND 200MHz clock 2018-12-29 11:38:38 +09:00
clk_bcm6345.c clk: bcm6345: convert to use live dt 2018-06-01 15:56:02 +02:00
clk_boston.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
clk_fixed_rate.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
clk_meson_axg.c clk: Add clock driver for AXG 2018-11-26 14:40:52 +01:00
clk_meson.c ARM: meson: Add regmap support for clock driver 2018-12-03 13:34:21 +01:00
clk_meson.h clk: add Amlogic meson clock driver 2018-06-19 07:31:47 -04:00
clk_pic32.c clk: Remove DM_FLAG_PRE_RELOC flag in various drivers 2018-11-14 09:16:28 -08:00
clk_sandbox_test.c clk: add clk_valid() 2018-08-03 19:53:10 -04:00
clk_sandbox.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
clk_stm32f.c clk: clk_stm32f: Use PLLSAIP as USB 48MHz clock 2018-05-08 09:07:34 -04:00
clk_stm32h7.c SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
clk_stm32mp1.c clk: stm32mp1: correctly handle Clock Spreading Generator 2019-02-09 07:50:57 -05:00
clk_vexpress_osc.c misc: Update read() and write() methods to return bytes xfered 2018-11-20 19:14:22 -07:00
clk_zynq.c clk: Remove DM_FLAG_PRE_RELOC flag in various drivers 2018-11-14 09:16:28 -08:00
clk_zynqmp.c clk: zynqmp: Fixed the same if/else part error reported by coverity 2018-07-19 10:49:53 +02:00
clk-hsdk-cgu.c Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR 2018-04-27 14:54:48 -04:00
clk-ti-sci.c clk: Introduce TI System Control Interface (TI SCI) clock driver 2018-09-11 08:32:55 -04:00
clk-uclass.c clk: Improve debug message in clk_set_default_rates() 2019-02-01 16:59:12 +01:00
ics8n3qv01.c clk: Add ICS8N3QV01 driver 2018-05-08 18:50:23 -04:00
Kconfig clk: Add SiFive FU540 PRCI clock driver 2019-02-27 09:12:33 +08:00
Makefile clk: Add SiFive FU540 PRCI clock driver 2019-02-27 09:12:33 +08:00
mpc83xx_clk.c clk: Add MPC83xx clock driver 2018-09-18 00:01:18 -06:00
mpc83xx_clk.h clk: Add MPC83xx clock driver 2018-09-18 00:01:18 -06:00