c2ae7d8220
Move the SPL settings into common/spl where most of the SPL code is kept. Signed-off-by: Simon Glass <sjg@chromium.org>
26 lines
694 B
Plaintext
26 lines
694 B
Plaintext
CONFIG_ARM=y
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CONFIG_ARCH_SUNXI=y
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CONFIG_MACH_SUN8I_A83T=y
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CONFIG_DRAM_TYPE=7
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CONFIG_DRAM_CLK=480
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CONFIG_DRAM_ZQ=15355
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CONFIG_DRAM_ODT_EN=y
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CONFIG_INITIAL_USB_SCAN_DELAY=500
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CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
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CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
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CONFIG_USB0_ID_DET="PH11"
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CONFIG_USB1_VBUS_PIN="PD24"
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CONFIG_AXP_GPIO=y
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CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-sinovoip-bpi-m3"
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# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
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CONFIG_SYS_EXTRA_OPTIONS="SATAPWR=SUNXI_GPD(25)"
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CONFIG_SPL=y
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_FLASH is not set
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# CONFIG_CMD_FPGA is not set
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CONFIG_AXP_DCDC5_VOLT=1200
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CONFIG_AXP_DLDO3_VOLT=2500
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CONFIG_AXP_SW_ON=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_MUSB_HOST=y
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