Shaohui Xie ba50fee6ae powerpc/p2041rdb: update cpld reset command according to CPLD 2.0 ... CPLD 2.0 provides a new register which bit[0] is set to '1' will reset board with initializing the CPLD registers to default values. And add bit[6] of register at offset 0x5 to use to enable flash bank selection. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>		2011-10-03 08:29:54 -05:00
..
cpld.c	powerpc/p2041rdb: update cpld reset command according to CPLD 2.0	2011-10-03 08:29:54 -05:00
cpld.h	powerpc/p2041rdb: update cpld reset command according to CPLD 2.0	2011-10-03 08:29:54 -05:00
ddr.c	MPC8xxx: drop redundant boot messages	2011-07-29 08:53:39 -05:00
eth.c	powerpc/p2041rdb: Add ethernet support on P2041RDB board	2011-09-29 19:01:05 -05:00
Makefile	powerpc/85xx: Refactor P2041RDB to use common p_corenet files	2011-09-29 19:01:06 -05:00
p2041rdb.c	powerpc/p2041rdb: Add ethernet support on P2041RDB board	2011-09-29 19:01:05 -05:00