u-boot/arch/arm/mach-tegra/tegra186
Stephen Warren b9ae6415b6 ARM: tegra: translate __asm_flush_l3_cache to assembly
When performing a cache disable function, code must not access DRAM.
That is because when the cache is disabled, it will be bypassed and all
loads and stores will be serviced by RAM. This prevents accessing any
dirty data in the cache. In turn, this means the stack cannot be
used, since that is in RAM. To guarantee that code doesn't use RAM (and
in particular the stack) __asm_flush_l3_cache() must be manually
implemented in assembly, rather than implemented in C since the compiler
won't know not to touch RAM.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-11-07 14:36:28 -08:00
..
cache.S ARM: tegra: translate __asm_flush_l3_cache to assembly 2016-11-07 14:36:28 -08:00
Kconfig ARM: tegra: add p2771-0000 board support 2016-05-31 11:22:59 -07:00
Makefile ARM: tegra: flush caches via SMC call 2016-09-27 09:11:03 -07:00
nvtboot_ll.S ARM: tegra: ensure nvtboot_boot_x0 alignment 2016-11-07 14:36:28 -08:00
nvtboot_mem.c ARM: tegra: pick up actual memory size 2016-07-21 09:31:30 -07:00