ac727577f0
Upon further review, not all code authors are in favour of this change.
This reverts commit ee3556bcaf.
Signed-off-by: Tom Rini <trini@konsulko.com>
188 lines
6.8 KiB
C
188 lines
6.8 KiB
C
/*
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* Common internal memory map for some Freescale SoCs
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*
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* Copyright 2013-2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __FSL_IMMAP_H
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#define __FSL_IMMAP_H
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/*
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* DDR memory controller registers
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* This structure works for mpc83xx (DDR2 and DDR3), mpc85xx, mpc86xx.
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*/
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struct ccsr_ddr {
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u32 cs0_bnds; /* Chip Select 0 Memory Bounds */
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u8 res_04[4];
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u32 cs1_bnds; /* Chip Select 1 Memory Bounds */
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u8 res_0c[4];
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u32 cs2_bnds; /* Chip Select 2 Memory Bounds */
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u8 res_14[4];
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u32 cs3_bnds; /* Chip Select 3 Memory Bounds */
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u8 res_1c[100];
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u32 cs0_config; /* Chip Select Configuration */
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u32 cs1_config; /* Chip Select Configuration */
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u32 cs2_config; /* Chip Select Configuration */
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u32 cs3_config; /* Chip Select Configuration */
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u8 res_90[48];
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u32 cs0_config_2; /* Chip Select Configuration 2 */
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u32 cs1_config_2; /* Chip Select Configuration 2 */
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u32 cs2_config_2; /* Chip Select Configuration 2 */
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u32 cs3_config_2; /* Chip Select Configuration 2 */
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u8 res_d0[48];
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u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
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u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
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u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
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u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
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u32 sdram_cfg; /* SDRAM Control Configuration */
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u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */
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u32 sdram_mode; /* SDRAM Mode Configuration */
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u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */
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u32 sdram_md_cntl; /* SDRAM Mode Control */
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u32 sdram_interval; /* SDRAM Interval Configuration */
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u32 sdram_data_init; /* SDRAM Data initialization */
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u8 res_12c[4];
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u32 sdram_clk_cntl; /* SDRAM Clock Control */
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u8 res_134[20];
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u32 init_addr; /* training init addr */
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u32 init_ext_addr; /* training init extended addr */
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u8 res_150[16];
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u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */
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u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */
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u32 timing_cfg_6; /* SDRAM Timing Configuration 6 */
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u32 timing_cfg_7; /* SDRAM Timing Configuration 7 */
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u32 ddr_zq_cntl; /* ZQ calibration control*/
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u32 ddr_wrlvl_cntl; /* write leveling control*/
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u8 reg_178[4];
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u32 ddr_sr_cntr; /* self refresh counter */
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u32 ddr_sdram_rcw_1; /* Control Words 1 */
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u32 ddr_sdram_rcw_2; /* Control Words 2 */
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u8 reg_188[8];
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u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */
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u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */
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u8 res_198[0x1a0-0x198];
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u32 ddr_sdram_rcw_3;
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u32 ddr_sdram_rcw_4;
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u32 ddr_sdram_rcw_5;
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u32 ddr_sdram_rcw_6;
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u8 res_1b0[0x200-0x1b0];
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u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */
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u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */
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u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */
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u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */
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u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */
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u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */
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u8 res_218[0x220-0x218];
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u32 sdram_mode_9; /* SDRAM Mode Configuration 9 */
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u32 sdram_mode_10; /* SDRAM Mode Configuration 10 */
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u32 sdram_mode_11; /* SDRAM Mode Configuration 11 */
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u32 sdram_mode_12; /* SDRAM Mode Configuration 12 */
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u32 sdram_mode_13; /* SDRAM Mode Configuration 13 */
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u32 sdram_mode_14; /* SDRAM Mode Configuration 14 */
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u32 sdram_mode_15; /* SDRAM Mode Configuration 15 */
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u32 sdram_mode_16; /* SDRAM Mode Configuration 16 */
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u8 res_240[0x250-0x240];
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u32 timing_cfg_8; /* SDRAM Timing Configuration 8 */
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u32 timing_cfg_9; /* SDRAM Timing Configuration 9 */
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u8 res_258[0x260-0x258];
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u32 sdram_cfg_3;
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u8 res_264[0x400-0x264];
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u32 dq_map_0;
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u32 dq_map_1;
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u32 dq_map_2;
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u32 dq_map_3;
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u8 res_410[0xb20-0x410];
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u32 ddr_dsr1; /* Debug Status 1 */
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u32 ddr_dsr2; /* Debug Status 2 */
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u32 ddr_cdr1; /* Control Driver 1 */
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u32 ddr_cdr2; /* Control Driver 2 */
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u8 res_b30[200];
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u32 ip_rev1; /* IP Block Revision 1 */
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u32 ip_rev2; /* IP Block Revision 2 */
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u32 eor; /* Enhanced Optimization Register */
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u8 res_c04[252];
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u32 mtcr; /* Memory Test Control Register */
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u8 res_d04[28];
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u32 mtp1; /* Memory Test Pattern 1 */
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u32 mtp2; /* Memory Test Pattern 2 */
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u32 mtp3; /* Memory Test Pattern 3 */
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u32 mtp4; /* Memory Test Pattern 4 */
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u32 mtp5; /* Memory Test Pattern 5 */
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u32 mtp6; /* Memory Test Pattern 6 */
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u32 mtp7; /* Memory Test Pattern 7 */
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u32 mtp8; /* Memory Test Pattern 8 */
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u32 mtp9; /* Memory Test Pattern 9 */
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u32 mtp10; /* Memory Test Pattern 10 */
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u8 res_d48[184];
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u32 data_err_inject_hi; /* Data Path Err Injection Mask High */
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u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */
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u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */
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u8 res_e0c[20];
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u32 capture_data_hi; /* Data Path Read Capture High */
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u32 capture_data_lo; /* Data Path Read Capture Low */
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u32 capture_ecc; /* Data Path Read Capture ECC */
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u8 res_e2c[20];
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u32 err_detect; /* Error Detect */
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u32 err_disable; /* Error Disable */
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u32 err_int_en;
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u32 capture_attributes; /* Error Attrs Capture */
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u32 capture_address; /* Error Addr Capture */
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u32 capture_ext_address; /* Error Extended Addr Capture */
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u32 err_sbe; /* Single-Bit ECC Error Management */
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u8 res_e5c[164];
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u32 debug[64]; /* debug_1 to debug_64 */
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};
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#ifdef CONFIG_SYS_FSL_HAS_CCI400
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#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
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#define CCI400_CTRLORD_EN_BARRIER 0
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#define CCI400_SHAORD_NON_SHAREABLE 0x00000002
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#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
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#define CCI400_SNOOP_REQ_EN 0x00000001
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/* CCI-400 registers */
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struct ccsr_cci400 {
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u32 ctrl_ord; /* Control Override */
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u32 spec_ctrl; /* Speculation Control */
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u32 secure_access; /* Secure Access */
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u32 status; /* Status */
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u32 impr_err; /* Imprecise Error */
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u8 res_14[0x100 - 0x14];
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u32 pmcr; /* Performance Monitor Control */
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u8 res_104[0xfd0 - 0x104];
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u32 pid[8]; /* Peripheral ID */
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u32 cid[4]; /* Component ID */
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struct {
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u32 snoop_ctrl; /* Snoop Control */
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u32 sha_ord; /* Shareable Override */
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u8 res_1008[0x1100 - 0x1008];
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u32 rc_qos_ord; /* read channel QoS Value Override */
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u32 wc_qos_ord; /* read channel QoS Value Override */
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u8 res_1108[0x110c - 0x1108];
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u32 qos_ctrl; /* QoS Control */
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u32 max_ot; /* Max OT */
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u8 res_1114[0x1130 - 0x1114];
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u32 target_lat; /* Target Latency */
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u32 latency_regu; /* Latency Regulation */
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u32 qos_range; /* QoS Range */
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u8 res_113c[0x2000 - 0x113c];
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} slave[5]; /* Slave Interface */
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u8 res_6000[0x9004 - 0x6000];
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u32 cycle_counter; /* Cycle counter */
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u32 count_ctrl; /* Count Control */
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u32 overflow_status; /* Overflow Flag Status */
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u8 res_9010[0xa000 - 0x9010];
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struct {
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u32 event_select; /* Event Select */
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u32 event_count; /* Event Count */
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u32 counter_ctrl; /* Counter Control */
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u32 overflow_status; /* Overflow Flag Status */
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u8 res_a010[0xb000 - 0xa010];
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} pcounter[4]; /* Performance Counter */
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u8 res_e004[0x10000 - 0xe004];
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};
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#endif
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#endif /* __FSL_IMMAP_H */
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