b31bf37a38
Clean config headers by moving CONFIG_SYS_DA850_DDR_INIT away to a Kconfig file. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
312 lines
9.7 KiB
C
312 lines
9.7 KiB
C
/*
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* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
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* Based on:
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* U-Boot:include/configs/da850evm.h
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*
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Based on davinci_dvevm.h. Original Copyrights follow:
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*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* Board
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*/
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#define CONFIG_DRIVER_TI_EMAC
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#define CONFIG_BARIX_IPAM390
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/*
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* SoC Configuration
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*/
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#define CONFIG_MACH_DAVINCI_DA850_EVM
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#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
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#define CONFIG_SOC_DA850 /* TI DA850 SoC */
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#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
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#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
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#define CONFIG_SYS_OSCIN_FREQ 24000000
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#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
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#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
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#define CONFIG_SYS_TEXT_BASE 0xc1080000
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/*
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* Memory Info
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*/
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#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
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#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
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#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
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#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
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/* memtest start addr */
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#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
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/* memtest will be run on 16MB */
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 16 * 1024 * 1024)
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
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DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
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DAVINCI_SYSCFG_SUSPSRC_UART2 | \
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DAVINCI_SYSCFG_SUSPSRC_UART0 | \
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DAVINCI_SYSCFG_SUSPSRC_EMAC)
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/*
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* PLL configuration
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*/
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#define CONFIG_SYS_DV_CLKMODE 0
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#define CONFIG_SYS_DA850_PLL0_POSTDIV 1
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#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
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#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
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#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
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#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
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#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
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#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
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#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
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#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
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#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
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#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
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#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
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#define CONFIG_SYS_DA850_PLL0_PLLM 24
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#define CONFIG_SYS_DA850_PLL1_PLLM 24
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/*
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* DDR2 memory configuration
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*/
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#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
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DV_DDR_PHY_EXT_STRBEN | \
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(0x2 << DV_DDR_PHY_RD_LATENCY_SHIFT))
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#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000498
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#define CONFIG_SYS_DA850_DDR2_SDBCR2 0x00000004
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#define CONFIG_SYS_DA850_DDR2_PBBPR 0x00000020
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#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
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(13 << DV_DDR_SDTMR1_RFC_SHIFT) | \
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(2 << DV_DDR_SDTMR1_RP_SHIFT) | \
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(2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
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(2 << DV_DDR_SDTMR1_WR_SHIFT) | \
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(5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
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(8 << DV_DDR_SDTMR1_RC_SHIFT) | \
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(1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
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(1 << DV_DDR_SDTMR1_WTR_SHIFT))
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#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
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(8 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
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(2 << DV_DDR_SDTMR2_XP_SHIFT) | \
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(0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
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(14 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
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(0xc7 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
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(1 << DV_DDR_SDTMR2_RTP_SHIFT) | \
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(2 << DV_DDR_SDTMR2_CKE_SHIFT))
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#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
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(1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
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(1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \
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(1 << DV_DDR_SDCR_DDREN_SHIFT) | \
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(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
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(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
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(2 << DV_DDR_SDCR_CL_SHIFT) | \
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(3 << DV_DDR_SDCR_IBANK_SHIFT) | \
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(2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
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#define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(1) | \
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DAVINCI_ABCR_WSTROBE(2) | \
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DAVINCI_ABCR_WHOLD(0) | \
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DAVINCI_ABCR_RSETUP(1) | \
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DAVINCI_ABCR_RSTROBE(2) | \
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DAVINCI_ABCR_RHOLD(1) | \
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DAVINCI_ABCR_TA(0) | \
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DAVINCI_ABCR_ASIZE_8BIT)
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/*
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* Serial Driver info
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*/
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
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#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART0_BASE /* Base address of UART0 */
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#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
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#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
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#define CONFIG_BAUDRATE 115200 /* Default baud rate */
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/*
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* Flash & Environment
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*/
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#define CONFIG_NAND_DAVINCI
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
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#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
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#define CONFIG_ENV_SIZE (128 << 10)
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#define CONFIG_SYS_NAND_USE_FLASH_BBT
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#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
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#define CONFIG_SYS_NAND_PAGE_2K
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#define CONFIG_SYS_NAND_CS 3
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#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
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#define CONFIG_SYS_NAND_MASK_CLE 0x10
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#define CONFIG_SYS_NAND_MASK_ALE 0x8
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#undef CONFIG_SYS_NAND_HW_ECC
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
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#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x120000
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#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
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#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
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CONFIG_SYS_NAND_U_BOOT_SIZE - \
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CONFIG_SYS_MALLOC_LEN - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_NAND_ECCPOS { \
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6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
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22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
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38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
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54, 55, 56, 57, 58, 59, 60, 61, 62, 63}
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 10
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SPL_NAND_BASE
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#define CONFIG_SPL_NAND_DRIVERS
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#define CONFIG_SPL_NAND_ECC
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#define CONFIG_SPL_NAND_SIMPLE
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#define CONFIG_SPL_NAND_LOAD
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/*
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* Network & Ethernet Configuration
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*/
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#ifdef CONFIG_DRIVER_TI_EMAC
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#define CONFIG_DRIVER_TI_EMAC_USE_RMII
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#define CONFIG_BOOTP_DEFAULT
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#define CONFIG_BOOTP_DNS
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#define CONFIG_BOOTP_DNS2
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#define CONFIG_BOOTP_SEND_HOSTNAME
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#define CONFIG_NET_RETRY_COUNT 10
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#endif
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/*
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* U-Boot general configuration
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*/
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#define CONFIG_MISC_INIT_R
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_BOOTFILE "uImage" /* Boot file name */
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
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#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_CRC32_VERIFY
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#define CONFIG_MX_CYCLIC
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/*
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* Linux Information
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*/
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#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
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#define CONFIG_HWCONFIG /* enable hwconfig */
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_REVISION_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"defbootargs=setenv bootargs mem=128M console=ttyS0,115200n8 " \
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"root=/dev/mtdblock5 rw noinitrd " \
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"rootfstype=jffs2 noinitrd\0" \
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"hwconfig=dsp:wake=yes\0" \
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"bootcmd=nboot kernel;run defbootargs addmtd;bootm 0xc0700000\0" \
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"bootfile=uImage\0" \
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"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
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"mtddevname=uboot-env\0" \
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"mtddevnum=0\0" \
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"mtdids=" MTDIDS_DEFAULT "\0" \
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"mtdparts=" MTDPARTS_DEFAULT "\0" \
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"u-boot=/tftpboot/ipam390/u-boot.ais\0" \
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"upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;" \
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"nand write c0000000 20000 ${filesize}\0" \
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"setbootparms=nand read c0100000 200000 400000;" \
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"run defbootargs addmtd;" \
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"spl export atags c0100000;" \
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"nand erase.part bootparms;" \
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"nand write c0000100 180000 20000\0" \
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"\0"
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/*
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* U-Boot commands
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*/
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#define CONFIG_CMD_ENV
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#define CONFIG_CMD_DIAG
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#define CONFIG_CMD_SAVES
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#ifdef CONFIG_CMD_BDI
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#define CONFIG_CLOCKS
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#endif
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#ifndef CONFIG_DRIVER_TI_EMAC
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#endif
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_NAND_TRIMFFS
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#define CONFIG_CMD_MTDPARTS
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#define CONFIG_MTD_DEVICE
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#define CONFIG_MTD_PARTITIONS
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#define CONFIG_LZO
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#define CONFIG_RBTREE
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#define CONFIG_CMD_UBIFS
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#define MTDIDS_NAME_STR "davinci_nand.0"
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#define MTDIDS_DEFAULT "nand0=" MTDIDS_NAME_STR
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#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
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"128k(u-boot-env)," \
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"1408k(u-boot)," \
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"128k(bootparms)," \
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"384k(factory-info)," \
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"4M(kernel)," \
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"-(rootfs)"
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/* defines for SPL */
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_BOARD_INIT
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#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
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CONFIG_SYS_MALLOC_LEN)
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#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
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#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-ipam390.lds"
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#define CONFIG_SPL_STACK 0x8001ff00
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#define CONFIG_SPL_TEXT_BASE 0x80000000
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#define CONFIG_SPL_MAX_SIZE 0x20000
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#define CONFIG_SPL_MAX_FOOTPRINT 32768
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/* additions for new relocation code, must added to all boards */
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#define CONFIG_SYS_SDRAM_BASE 0xc0000000
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
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GENERATED_GBL_DATA_SIZE)
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/* add FALCON boot mode */
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#define CONFIG_CMD_SPL
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#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000
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#define CONFIG_SYS_SPL_ARGS_ADDR LINUX_BOOT_PARAM_ADDR
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#define CONFIG_CMD_SPL_NAND_OFS 0x00180000
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#define CONFIG_CMD_SPL_WRITE_SIZE 0x400
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/* GPIO support */
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#define CONFIG_DA8XX_GPIO
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#define CONFIG_IPAM390_GPIO_BOOTMODE ((16 * 7) + 14)
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#define CONFIG_SHOW_BOOT_PROGRESS
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#define CONFIG_IPAM390_GPIO_LED_RED ((16 * 7) + 11)
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#define CONFIG_IPAM390_GPIO_LED_GREEN ((16 * 7) + 12)
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#endif /* __CONFIG_H */
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