9e75875849
Add support for Freescale T4240 SoC. Feature of T4240 are
(incomplete list):
12 dual-threaded e6500 cores built on Power Architecture® technology
Arranged as clusters of four cores sharing a 2 MB L2 cache.
Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture
v2.06-compliant)
Three levels of instruction: user, supervisor, and hypervisor
1.5 MB CoreNet Platform Cache (CPC)
Hierarchical interconnect fabric
CoreNet fabric supporting coherent and non-coherent transactions with
prioritization and bandwidth allocation amongst CoreNet end-points
1.6 Tbps coherent read bandwidth
Queue Manager (QMan) fabric supporting packet-level queue management and
quality of service scheduling
Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support
Memory prefetch engine (PMan)
Data Path Acceleration Architecture (DPAA) incorporating acceleration for
the following functions:
Packet parsing, classification, and distribution (Frame Manager 1.1)
Queue management for scheduling, packet sequencing, and congestion
management (Queue Manager 1.1)
Hardware buffer management for buffer allocation and de-allocation
(BMan 1.1)
Cryptography acceleration (SEC 5.0) at up to 40 Gbps
RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps
Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps
DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0)
32 SerDes lanes at up to 10.3125 GHz
Ethernet interfaces
Up to four 10 Gbps Ethernet MACs
Up to sixteen 1 Gbps Ethernet MACs
Maximum configuration of 4 x 10 GE + 8 x 1 GE
High-speed peripheral interfaces
Four PCI Express 2.0/3.0 controllers
Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with
Type 11 messaging and Type 9 data streaming support
Interlaken look-aside interface for serial TCAM connection
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Four I2C controllers
Four 2-pin or two 4-pin UARTs
Integrated Flash controller supporting NAND and NOR flash
Two eight-channel DMA engines
Support for hardware virtualization and partitioning enforcement
QorIQ Platform's Trust Architecture 1.1
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
126 lines
3.2 KiB
C
126 lines
3.2 KiB
C
/*
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __FM_ETH_H__
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#define __FM_ETH_H__
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#include <common.h>
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#include <asm/types.h>
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#include <asm/fsl_enet.h>
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enum fm_port {
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FM1_DTSEC1,
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FM1_DTSEC2,
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FM1_DTSEC3,
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FM1_DTSEC4,
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FM1_DTSEC5,
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FM1_DTSEC6,
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FM1_DTSEC9,
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FM1_DTSEC10,
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FM1_10GEC1,
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FM1_10GEC2,
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FM2_DTSEC1,
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FM2_DTSEC2,
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FM2_DTSEC3,
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FM2_DTSEC4,
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FM2_DTSEC5,
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FM2_DTSEC6,
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FM2_DTSEC9,
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FM2_DTSEC10,
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FM2_10GEC1,
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FM2_10GEC2,
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NUM_FM_PORTS,
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};
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enum fm_eth_type {
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FM_ETH_1G_E,
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FM_ETH_10G_E,
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};
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#define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xe1120)
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#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xf1000)
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#define DEFAULT_FM_MDIO_NAME "FSL_MDIO0"
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#define DEFAULT_FM_TGEC_MDIO_NAME "FM_TGEC_MDIO"
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/* Fman ethernet info struct */
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#define FM_ETH_INFO_INITIALIZER(idx, pregs) \
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.fm = idx, \
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.phy_regs = (void *)pregs, \
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.enet_if = PHY_INTERFACE_MODE_NONE, \
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#define FM_DTSEC_INFO_INITIALIZER(idx, n) \
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{ \
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FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR) \
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.index = idx, \
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.num = n - 1, \
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.type = FM_ETH_1G_E, \
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.port = FM##idx##_DTSEC##n, \
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.rx_port_id = RX_PORT_1G_BASE + n - 1, \
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.tx_port_id = TX_PORT_1G_BASE + n - 1, \
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.compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
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offsetof(struct ccsr_fman, mac_1g[n-1]),\
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}
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#define FM_TGEC_INFO_INITIALIZER(idx, n) \
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{ \
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FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
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.index = idx, \
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.num = n - 1, \
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.type = FM_ETH_10G_E, \
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.port = FM##idx##_10GEC##n, \
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.rx_port_id = RX_PORT_10G_BASE + n - 1, \
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.tx_port_id = TX_PORT_10G_BASE + n - 1, \
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.compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
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offsetof(struct ccsr_fman, mac_10g[n-1]),\
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}
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struct fm_eth_info {
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u8 enabled;
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u8 fm;
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u8 num;
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u8 phy_addr;
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int index;
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u16 rx_port_id;
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u16 tx_port_id;
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enum fm_port port;
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enum fm_eth_type type;
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void *phy_regs;
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phy_interface_t enet_if;
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u32 compat_offset;
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struct mii_dev *bus;
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};
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struct tgec_mdio_info {
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struct tgec_mdio_controller *regs;
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char *name;
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};
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int fm_tgec_mdio_init(bd_t *bis, struct tgec_mdio_info *info);
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int fm_standard_init(bd_t *bis);
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void fman_enet_init(void);
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void fdt_fixup_fman_ethernet(void *fdt);
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phy_interface_t fm_info_get_enet_if(enum fm_port port);
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void fm_info_set_phy_address(enum fm_port port, int address);
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int fm_info_get_phy_address(enum fm_port port);
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void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus);
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void fm_disable_port(enum fm_port port);
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#endif
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