48b42616e9
- rewrite of the S3C24X0 register definitions stuff
- "driver" for the built-in S3C24X0 RTC
* Patches by Yuli Barcohen, 12 Jun 2003:
- Add MII support and Ethernet PHY initialization for MPC8260ADS board
- Fix incorrect SIUMCR initialisation caused by wrong Hard Reset
configuration word supplied by FPGA on some MPC8260ADS boards
* Patch by Pantelis Antoniou, 10 Jun 2003:
Unify status LED interface
228 lines
7.6 KiB
C
228 lines
7.6 KiB
C
/*
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* (C) Copyright 2003
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* David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/************************************************
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* NAME : s3c2410.h
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* Version : 31.3.2003
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*
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* Based on S3C2410X User's manual Rev 1.1
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************************************************/
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#ifndef __S3C2410_H__
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#define __S3C2410_H__
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#define S3C24X0_UART_CHANNELS 3
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#define S3C24X0_SPI_CHANNELS 2
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/* S3C2410 only supports 512 Byte HW ECC */
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#define S3C2410_ECCSIZE 512
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#define S3C2410_ECCBYTES 3
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typedef enum {
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S3C24X0_UART0,
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S3C24X0_UART1,
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S3C24X0_UART2
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} S3C24X0_UARTS_NR;
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/* S3C2410 device base addresses */
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#define S3C24X0_MEMCTL_BASE 0x48000000
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#define S3C24X0_USB_HOST_BASE 0x49000000
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#define S3C24X0_INTERRUPT_BASE 0x4A000000
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#define S3C24X0_DMA_BASE 0x4B000000
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#define S3C24X0_CLOCK_POWER_BASE 0x4C000000
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#define S3C24X0_LCD_BASE 0x4D000000
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#define S3C2410_NAND_BASE 0x4E000000
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#define S3C24X0_UART_BASE 0x50000000
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#define S3C24X0_TIMER_BASE 0x51000000
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#define S3C24X0_USB_DEVICE_BASE 0x52000140
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#define S3C24X0_WATCHDOG_BASE 0x53000000
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#define S3C24X0_I2C_BASE 0x54000000
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#define S3C24X0_I2S_BASE 0x55000000
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#define S3C24X0_GPIO_BASE 0x56000000
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#define S3C24X0_RTC_BASE 0x57000000
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#define S3C2410_ADC_BASE 0x58000000
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#define S3C24X0_SPI_BASE 0x59000000
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#define S3C2410_SDI_BASE 0x5A000000
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/* include common stuff */
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#include <s3c24x0.h>
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static inline S3C24X0_MEMCTL * const S3C24X0_GetBase_MEMCTL(void)
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{
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return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE;
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}
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static inline S3C24X0_USB_HOST * const S3C24X0_GetBase_USB_HOST(void)
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{
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return (S3C24X0_USB_HOST * const)S3C24X0_USB_HOST_BASE;
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}
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static inline S3C24X0_INTERRUPT * const S3C24X0_GetBase_INTERRUPT(void)
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{
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return (S3C24X0_INTERRUPT * const)S3C24X0_INTERRUPT_BASE;
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}
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static inline S3C24X0_DMAS * const S3C24X0_GetBase_DMAS(void)
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{
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return (S3C24X0_DMAS * const)S3C24X0_DMA_BASE;
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}
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static inline S3C24X0_CLOCK_POWER * const S3C24X0_GetBase_CLOCK_POWER(void)
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{
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return (S3C24X0_CLOCK_POWER * const)S3C24X0_CLOCK_POWER_BASE;
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}
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static inline S3C24X0_LCD * const S3C24X0_GetBase_LCD(void)
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{
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return (S3C24X0_LCD * const)S3C24X0_LCD_BASE;
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}
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static inline S3C2410_NAND * const S3C2410_GetBase_NAND(void)
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{
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return (S3C2410_NAND * const)S3C2410_NAND_BASE;
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}
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static inline S3C24X0_UART * const S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr)
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{
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return (S3C24X0_UART * const)(S3C24X0_UART_BASE + (nr * 0x4000));
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}
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static inline S3C24X0_TIMERS * const S3C24X0_GetBase_TIMERS(void)
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{
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return (S3C24X0_TIMERS * const)S3C24X0_TIMER_BASE;
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}
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static inline S3C24X0_USB_DEVICE * const S3C24X0_GetBase_USB_DEVICE(void)
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{
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return (S3C24X0_USB_DEVICE * const)S3C24X0_USB_DEVICE_BASE;
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}
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static inline S3C24X0_WATCHDOG * const S3C24X0_GetBase_WATCHDOG(void)
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{
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return (S3C24X0_WATCHDOG * const)S3C24X0_WATCHDOG_BASE;
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}
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static inline S3C24X0_I2C * const S3C24X0_GetBase_I2C(void)
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{
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return (S3C24X0_I2C * const)S3C24X0_I2C_BASE;
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}
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static inline S3C24X0_I2S * const S3C24X0_GetBase_I2S(void)
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{
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return (S3C24X0_I2S * const)S3C24X0_I2S_BASE;
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}
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static inline S3C24X0_GPIO * const S3C24X0_GetBase_GPIO(void)
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{
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return (S3C24X0_GPIO * const)S3C24X0_GPIO_BASE;
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}
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static inline S3C24X0_RTC * const S3C24X0_GetBase_RTC(void)
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{
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return (S3C24X0_RTC * const)S3C24X0_RTC_BASE;
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}
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static inline S3C2410_ADC * const S3C2410_GetBase_ADC(void)
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{
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return (S3C2410_ADC * const)S3C2410_ADC_BASE;
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}
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static inline S3C24X0_SPI * const S3C24X0_GetBase_SPI(void)
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{
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return (S3C24X0_SPI * const)S3C24X0_SPI_BASE;
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}
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static inline S3C2410_SDI * const S3C2410_GetBase_SDI(void)
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{
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return (S3C2410_SDI * const)S3C2410_SDI_BASE;
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}
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/* ISR */
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#define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0))
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#define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4))
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#define pISR_SWI (*(unsigned *)(_ISR_STARTADDRESS+0x8))
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#define pISR_PABORT (*(unsigned *)(_ISR_STARTADDRESS+0xC))
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#define pISR_DABORT (*(unsigned *)(_ISR_STARTADDRESS+0x10))
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#define pISR_RESERVED (*(unsigned *)(_ISR_STARTADDRESS+0x14))
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#define pISR_IRQ (*(unsigned *)(_ISR_STARTADDRESS+0x18))
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#define pISR_FIQ (*(unsigned *)(_ISR_STARTADDRESS+0x1C))
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#define pISR_EINT0 (*(unsigned *)(_ISR_STARTADDRESS+0x20))
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#define pISR_EINT1 (*(unsigned *)(_ISR_STARTADDRESS+0x24))
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#define pISR_EINT2 (*(unsigned *)(_ISR_STARTADDRESS+0x28))
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#define pISR_EINT3 (*(unsigned *)(_ISR_STARTADDRESS+0x2C))
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#define pISR_EINT4_7 (*(unsigned *)(_ISR_STARTADDRESS+0x30))
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#define pISR_EINT8_23 (*(unsigned *)(_ISR_STARTADDRESS+0x34))
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#define pISR_BAT_FLT (*(unsigned *)(_ISR_STARTADDRESS+0x3C))
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#define pISR_TICK (*(unsigned *)(_ISR_STARTADDRESS+0x40))
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#define pISR_WDT (*(unsigned *)(_ISR_STARTADDRESS+0x44))
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#define pISR_TIMER0 (*(unsigned *)(_ISR_STARTADDRESS+0x48))
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#define pISR_TIMER1 (*(unsigned *)(_ISR_STARTADDRESS+0x4C))
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#define pISR_TIMER2 (*(unsigned *)(_ISR_STARTADDRESS+0x50))
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#define pISR_TIMER3 (*(unsigned *)(_ISR_STARTADDRESS+0x54))
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#define pISR_TIMER4 (*(unsigned *)(_ISR_STARTADDRESS+0x58))
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#define pISR_UART2 (*(unsigned *)(_ISR_STARTADDRESS+0x5C))
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#define pISR_NOTUSED (*(unsigned *)(_ISR_STARTADDRESS+0x60))
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#define pISR_DMA0 (*(unsigned *)(_ISR_STARTADDRESS+0x64))
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#define pISR_DMA1 (*(unsigned *)(_ISR_STARTADDRESS+0x68))
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#define pISR_DMA2 (*(unsigned *)(_ISR_STARTADDRESS+0x6C))
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#define pISR_DMA3 (*(unsigned *)(_ISR_STARTADDRESS+0x70))
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#define pISR_SDI (*(unsigned *)(_ISR_STARTADDRESS+0x74))
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#define pISR_SPI0 (*(unsigned *)(_ISR_STARTADDRESS+0x78))
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#define pISR_UART1 (*(unsigned *)(_ISR_STARTADDRESS+0x7C))
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#define pISR_USBD (*(unsigned *)(_ISR_STARTADDRESS+0x84))
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#define pISR_USBH (*(unsigned *)(_ISR_STARTADDRESS+0x88))
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#define pISR_IIC (*(unsigned *)(_ISR_STARTADDRESS+0x8C))
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#define pISR_UART0 (*(unsigned *)(_ISR_STARTADDRESS+0x90))
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#define pISR_SPI1 (*(unsigned *)(_ISR_STARTADDRESS+0x94))
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#define pISR_RTC (*(unsigned *)(_ISR_STARTADDRESS+0x98))
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#define pISR_ADC (*(unsigned *)(_ISR_STARTADDRESS+0xA0))
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/* PENDING BIT */
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#define BIT_EINT0 (0x1)
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#define BIT_EINT1 (0x1<<1)
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#define BIT_EINT2 (0x1<<2)
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#define BIT_EINT3 (0x1<<3)
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#define BIT_EINT4_7 (0x1<<4)
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#define BIT_EINT8_23 (0x1<<5)
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#define BIT_BAT_FLT (0x1<<7)
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#define BIT_TICK (0x1<<8)
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#define BIT_WDT (0x1<<9)
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#define BIT_TIMER0 (0x1<<10)
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#define BIT_TIMER1 (0x1<<11)
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#define BIT_TIMER2 (0x1<<12)
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#define BIT_TIMER3 (0x1<<13)
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#define BIT_TIMER4 (0x1<<14)
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#define BIT_UART2 (0x1<<15)
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#define BIT_LCD (0x1<<16)
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#define BIT_DMA0 (0x1<<17)
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#define BIT_DMA1 (0x1<<18)
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#define BIT_DMA2 (0x1<<19)
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#define BIT_DMA3 (0x1<<20)
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#define BIT_SDI (0x1<<21)
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#define BIT_SPI0 (0x1<<22)
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#define BIT_UART1 (0x1<<23)
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#define BIT_USBD (0x1<<25)
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#define BIT_USBH (0x1<<26)
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#define BIT_IIC (0x1<<27)
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#define BIT_UART0 (0x1<<28)
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#define BIT_SPI1 (0x1<<29)
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#define BIT_RTC (0x1<<30)
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#define BIT_ADC (0x1<<31)
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#define BIT_ALLMSK (0xFFFFFFFF)
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#define ClearPending(bit) {\
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rSRCPND = bit;\
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rINTPND = bit;\
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rINTPND;\
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}
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/* Wait until rINTPND is changed for the case that the ISR is very short. */
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#endif /*__S3C2410_H__*/
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