9aea95307f
- support larger DDR memories up to 2G on the PC8540/8560ADS and STXGP3 boards - Made MPC8540/8560ADS be 33Mhz PCI by default. - Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16 and CONFIG_L2_INIT_RAM options. - Refactor Local Bus initialization out of SDRAM setup. - Re-implement new version of LBC11/DDR11 errata workarounds. - Moved board specific PCI init parts out of CPU directory. - Added TLB entry for PCI-1 IO Memory - Updated README.mpc85xxads
116 lines
3.5 KiB
C
116 lines
3.5 KiB
C
/*
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* Copyright 2003 Motorola,Inc.
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* Xianghua Xiao(x.xiao@motorola.com)
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*/
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#ifndef __E500_H__
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#define __E500_H__
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#ifndef __ASSEMBLY__
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typedef struct
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{
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unsigned long freqProcessor;
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unsigned long freqSystemBus;
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} MPC85xx_SYS_INFO;
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#endif /* _ASMLANGUAGE */
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/* Motorola E500 core provides 16 TLB1 entries; they can be used for
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* initial memory mapping like legacy BAT registers do. Usually we
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* use four MAS registers(MAS0-3) to operate on TLB1 entries.
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*
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* While there are 16 Entries with variable Page Sizes in TLB1,
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* there are also 256 Entries with fixed 4K pages in TLB0.
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*
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* We also need LAWs(Local Access Window) to associate a range of
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* the local 32-bit address space with a particular target interface
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* such as PCI/PCI-X, RapidIO, Local Bus and DDR SDRAM.
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*
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* We put TLB1/LAW code here because memory mapping is board-specific
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* instead of cpu-specific.
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*
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* While these macros are all nominally for TLB1 by name, they can
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* also be used for TLB0 as well.
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*/
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/*
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* Convert addresses to Effective and Real Page Numbers.
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* Grab the high 20-bits and shift 'em down, dropping the "byte offset".
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*/
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#define E500_TLB_EPN(addr) (((addr) >> 12) & 0xfffff)
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#define E500_TLB_RPN(addr) (((addr) >> 12) & 0xfffff)
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/* MAS0
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* tlbsel(TLB Select):0,1
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* esel(Entry Select): 0,1,2,...,15 for TLB1
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* nv(Next victim):0,1
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*/
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#define TLB1_MAS0(tlbsel,esel,nv) \
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((((tlbsel) << 28) & MAS0_TLBSEL) |\
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(((esel) << 16) & MAS0_ESEL ) |\
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(nv) )
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/* MAS1
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* v(TLB valid bit):0,1
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* iprot(invalidate protect):0,1
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* tid(translation identity):8bit to match process IDs
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* ts(translation space,comparing with MSR[IS,DS]): 0,1
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* tsize(translation size):1,2,...,9(4K,16K,64K,256K,1M,4M,16M,64M,256M)
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*/
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#define TLB1_MAS1(v,iprot,tid,ts,tsize) \
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((((v) << 31) & MAS1_VALID) |\
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(((iprot) << 30) & MAS1_IPROT) |\
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(((tid) << 16) & MAS1_TID) |\
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(((ts) << 12) & MAS1_TS) |\
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(((tsize) << 8) & MAS1_TSIZE) )
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/* MAS2
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* epn(effective page number):20bits
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* sharen(Shared cache state):0,1
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* x0,x1(implementation specific page attribute):0,1
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* w,i,m,g,e(write-through,cache-inhibited,memory coherency,guarded,
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* endianness):0,1
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*/
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#define TLB1_MAS2(epn,sharen,x0,x1,w,i,m,g,e) \
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((((epn) << 12) & MAS2_EPN) |\
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(((sharen) << 9) & MAS2_SHAREN) |\
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(((x0) << 6) & MAS2_X0) |\
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(((x1) << 5) & MAS2_X1) |\
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(((w) << 4) & MAS2_W) |\
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(((i) << 3) & MAS2_I) |\
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(((m) << 2) & MAS2_M) |\
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(((g) << 1) & MAS2_G) |\
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(e) )
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/* MAS3
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* rpn(real page number):20bits
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* u0-u3(user bits, useful for page table management in OS):0,1
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* ux,sx,uw,sw,ur,sr(permission bits, user and supervisor read,
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* write,execute permission).
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*/
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#define TLB1_MAS3(rpn,u0,u1,u2,u3,ux,sx,uw,sw,ur,sr) \
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((((rpn) << 12) & MAS3_RPN) |\
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(((u0) << 9) & MAS3_U0) |\
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(((u1) << 8) & MAS3_U1) |\
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(((u2) << 7) & MAS3_U2) |\
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(((u3) << 6) & MAS3_U3) |\
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(((ux) << 5) & MAS3_UX) |\
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(((sx) << 4) & MAS3_SX) |\
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(((uw) << 3) & MAS3_UW) |\
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(((sw) << 2) & MAS3_SW) |\
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(((ur) << 1) & MAS3_UR) |\
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(sr) )
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#define RESET_VECTOR 0xfffffffc
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#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache
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line aligned data. */
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#endif /* __E500_H__ */
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