8fa6979beb
This change adds support for configuring the module clocks for SPI1 and SPI5 from the 594MHz GPLL. Note that the driver (rk_spi.c) always sets this to 99MHz, but the implemented functionality is more general and will also support different clock configurations. X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com> Acked-by: Simon Glass <sjg@chromium.org> |
||
---|---|---|
.. | ||
aspeed | ||
at91 | ||
exynos | ||
rockchip | ||
tegra | ||
uniphier | ||
clk_boston.c | ||
clk_fixed_rate.c | ||
clk_pic32.c | ||
clk_sandbox_test.c | ||
clk_sandbox.c | ||
clk_stm32f7.c | ||
clk_zynq.c | ||
clk_zynqmp.c | ||
clk-uclass.c | ||
Kconfig | ||
Makefile |