4135e10732
This adds a transport driver that implements UCLASS_VIRTIO for virtio over pci, which is commonly used on x86. It only supports the legacy interface of the pci transport, which is the default device that QEMU emulates. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
174 lines
5.1 KiB
C
174 lines
5.1 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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*
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* From Linux kernel include/uapi/linux/virtio_pci.h
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*/
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#ifndef _LINUX_VIRTIO_PCI_H
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#define _LINUX_VIRTIO_PCI_H
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#ifndef VIRTIO_PCI_NO_LEGACY
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/* A 32-bit r/o bitmask of the features supported by the host */
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#define VIRTIO_PCI_HOST_FEATURES 0
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/* A 32-bit r/w bitmask of features activated by the guest */
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#define VIRTIO_PCI_GUEST_FEATURES 4
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/* A 32-bit r/w PFN for the currently selected queue */
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#define VIRTIO_PCI_QUEUE_PFN 8
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/* A 16-bit r/o queue size for the currently selected queue */
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#define VIRTIO_PCI_QUEUE_NUM 12
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/* A 16-bit r/w queue selector */
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#define VIRTIO_PCI_QUEUE_SEL 14
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/* A 16-bit r/w queue notifier */
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#define VIRTIO_PCI_QUEUE_NOTIFY 16
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/* An 8-bit device status register */
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#define VIRTIO_PCI_STATUS 18
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/*
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* An 8-bit r/o interrupt status register. Reading the value will return the
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* current contents of the ISR and will also clear it. This is effectively
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* a read-and-acknowledge.
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*/
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#define VIRTIO_PCI_ISR 19
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/* MSI-X registers: only enabled if MSI-X is enabled */
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/* A 16-bit vector for configuration changes */
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#define VIRTIO_MSI_CONFIG_VECTOR 20
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/* A 16-bit vector for selected queue notifications */
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#define VIRTIO_MSI_QUEUE_VECTOR 22
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/*
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* The remaining space is defined by each driver as the per-driver
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* configuration space
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*/
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#define VIRTIO_PCI_CONFIG_OFF(msix) ((msix) ? 24 : 20)
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/* Virtio ABI version, this must match exactly */
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#define VIRTIO_PCI_ABI_VERSION 0
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/*
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* How many bits to shift physical queue address written to QUEUE_PFN.
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* 12 is historical, and due to x86 page size.
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*/
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#define VIRTIO_PCI_QUEUE_ADDR_SHIFT 12
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/*
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* The alignment to use between consumer and producer parts of vring.
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* x86 pagesize again.
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*/
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#define VIRTIO_PCI_VRING_ALIGN 4096
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#endif /* VIRTIO_PCI_NO_LEGACY */
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/* The bit of the ISR which indicates a device configuration change */
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#define VIRTIO_PCI_ISR_CONFIG 0x2
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/* Vector value used to disable MSI for queue */
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#define VIRTIO_MSI_NO_VECTOR 0xffff
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#ifndef VIRTIO_PCI_NO_MODERN
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/* IDs for different capabilities. Must all exist. */
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/* Common configuration */
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#define VIRTIO_PCI_CAP_COMMON_CFG 1
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/* Notifications */
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#define VIRTIO_PCI_CAP_NOTIFY_CFG 2
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/* ISR access */
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#define VIRTIO_PCI_CAP_ISR_CFG 3
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/* Device specific configuration */
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#define VIRTIO_PCI_CAP_DEVICE_CFG 4
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/* PCI configuration access */
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#define VIRTIO_PCI_CAP_PCI_CFG 5
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/* This is the PCI capability header: */
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struct virtio_pci_cap {
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__u8 cap_vndr; /* Generic PCI field: PCI_CAP_ID_VNDR */
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__u8 cap_next; /* Generic PCI field: next ptr */
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__u8 cap_len; /* Generic PCI field: capability length */
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__u8 cfg_type; /* Identifies the structure */
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__u8 bar; /* Where to find it */
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__u8 padding[3]; /* Pad to full dword */
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__le32 offset; /* Offset within bar */
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__le32 length; /* Length of the structure, in bytes */
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};
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struct virtio_pci_notify_cap {
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struct virtio_pci_cap cap;
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__le32 notify_off_multiplier; /* Multiplier for queue_notify_off */
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};
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/* Fields in VIRTIO_PCI_CAP_COMMON_CFG: */
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struct virtio_pci_common_cfg {
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/* About the whole device */
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__le32 device_feature_select; /* read-write */
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__le32 device_feature; /* read-only */
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__le32 guest_feature_select; /* read-write */
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__le32 guest_feature; /* read-write */
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__le16 msix_config; /* read-write */
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__le16 num_queues; /* read-only */
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__u8 device_status; /* read-write */
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__u8 config_generation; /* read-only */
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/* About a specific virtqueue */
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__le16 queue_select; /* read-write */
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__le16 queue_size; /* read-write, power of 2 */
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__le16 queue_msix_vector; /* read-write */
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__le16 queue_enable; /* read-write */
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__le16 queue_notify_off; /* read-only */
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__le32 queue_desc_lo; /* read-write */
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__le32 queue_desc_hi; /* read-write */
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__le32 queue_avail_lo; /* read-write */
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__le32 queue_avail_hi; /* read-write */
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__le32 queue_used_lo; /* read-write */
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__le32 queue_used_hi; /* read-write */
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};
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/* Fields in VIRTIO_PCI_CAP_PCI_CFG: */
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struct virtio_pci_cfg_cap {
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struct virtio_pci_cap cap;
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__u8 pci_cfg_data[4]; /* Data for BAR access */
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};
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/* Macro versions of offsets for the Old Timers! */
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#define VIRTIO_PCI_CAP_VNDR 0
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#define VIRTIO_PCI_CAP_NEXT 1
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#define VIRTIO_PCI_CAP_LEN 2
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#define VIRTIO_PCI_CAP_CFG_TYPE 3
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#define VIRTIO_PCI_CAP_BAR 4
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#define VIRTIO_PCI_CAP_OFFSET 8
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#define VIRTIO_PCI_CAP_LENGTH 12
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#define VIRTIO_PCI_NOTIFY_CAP_MULT 16
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#define VIRTIO_PCI_COMMON_DFSELECT 0
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#define VIRTIO_PCI_COMMON_DF 4
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#define VIRTIO_PCI_COMMON_GFSELECT 8
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#define VIRTIO_PCI_COMMON_GF 12
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#define VIRTIO_PCI_COMMON_MSIX 16
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#define VIRTIO_PCI_COMMON_NUMQ 18
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#define VIRTIO_PCI_COMMON_STATUS 20
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#define VIRTIO_PCI_COMMON_CFGGENERATION 21
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#define VIRTIO_PCI_COMMON_Q_SELECT 22
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#define VIRTIO_PCI_COMMON_Q_SIZE 24
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#define VIRTIO_PCI_COMMON_Q_MSIX 26
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#define VIRTIO_PCI_COMMON_Q_ENABLE 28
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#define VIRTIO_PCI_COMMON_Q_NOFF 30
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#define VIRTIO_PCI_COMMON_Q_DESCLO 32
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#define VIRTIO_PCI_COMMON_Q_DESCHI 36
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#define VIRTIO_PCI_COMMON_Q_AVAILLO 40
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#define VIRTIO_PCI_COMMON_Q_AVAILHI 44
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#define VIRTIO_PCI_COMMON_Q_USEDLO 48
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#define VIRTIO_PCI_COMMON_Q_USEDHI 52
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#endif /* VIRTIO_PCI_NO_MODERN */
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#endif /* _LINUX_VIRTIO_PCI_H */
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