5d3bcdb12f
Add generic support for backplane kr modes currently available: 10gbase-kr, 40gbase-kr4. Remove platform generic fixups (armv8/layerscape and powerpc) for ethernet interfaces specified in device tree as supported backplane modes. Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
103 lines
2.8 KiB
C
103 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2020 NXP
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* Andy Fleming <afleming@gmail.com>
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*
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* This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
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*/
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#ifndef _PHY_INTERFACE_H
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#define _PHY_INTERFACE_H
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typedef enum {
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PHY_INTERFACE_MODE_MII,
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PHY_INTERFACE_MODE_GMII,
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PHY_INTERFACE_MODE_SGMII,
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PHY_INTERFACE_MODE_SGMII_2500,
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PHY_INTERFACE_MODE_QSGMII,
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PHY_INTERFACE_MODE_TBI,
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PHY_INTERFACE_MODE_RMII,
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PHY_INTERFACE_MODE_RGMII,
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PHY_INTERFACE_MODE_RGMII_ID,
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PHY_INTERFACE_MODE_RGMII_RXID,
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PHY_INTERFACE_MODE_RGMII_TXID,
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PHY_INTERFACE_MODE_RTBI,
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PHY_INTERFACE_MODE_XGMII,
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PHY_INTERFACE_MODE_XAUI,
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PHY_INTERFACE_MODE_RXAUI,
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PHY_INTERFACE_MODE_SFI,
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PHY_INTERFACE_MODE_INTERNAL,
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PHY_INTERFACE_MODE_25G_AUI,
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PHY_INTERFACE_MODE_XLAUI,
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PHY_INTERFACE_MODE_CAUI2,
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PHY_INTERFACE_MODE_CAUI4,
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PHY_INTERFACE_MODE_NCSI,
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PHY_INTERFACE_MODE_XFI,
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PHY_INTERFACE_MODE_USXGMII,
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PHY_INTERFACE_MODE_NONE, /* Must be last */
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PHY_INTERFACE_MODE_COUNT,
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} phy_interface_t;
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static const char * const phy_interface_strings[] = {
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[PHY_INTERFACE_MODE_MII] = "mii",
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[PHY_INTERFACE_MODE_GMII] = "gmii",
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[PHY_INTERFACE_MODE_SGMII] = "sgmii",
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[PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500",
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[PHY_INTERFACE_MODE_QSGMII] = "qsgmii",
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[PHY_INTERFACE_MODE_TBI] = "tbi",
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[PHY_INTERFACE_MODE_RMII] = "rmii",
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[PHY_INTERFACE_MODE_RGMII] = "rgmii",
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[PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id",
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[PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid",
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[PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid",
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[PHY_INTERFACE_MODE_RTBI] = "rtbi",
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[PHY_INTERFACE_MODE_XGMII] = "xgmii",
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[PHY_INTERFACE_MODE_XAUI] = "xaui",
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[PHY_INTERFACE_MODE_RXAUI] = "rxaui",
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[PHY_INTERFACE_MODE_SFI] = "sfi",
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[PHY_INTERFACE_MODE_INTERNAL] = "internal",
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[PHY_INTERFACE_MODE_25G_AUI] = "25g-aui",
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[PHY_INTERFACE_MODE_XLAUI] = "xlaui4",
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[PHY_INTERFACE_MODE_CAUI2] = "caui2",
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[PHY_INTERFACE_MODE_CAUI4] = "caui4",
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[PHY_INTERFACE_MODE_NCSI] = "NC-SI",
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[PHY_INTERFACE_MODE_XFI] = "xfi",
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[PHY_INTERFACE_MODE_USXGMII] = "usxgmii",
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[PHY_INTERFACE_MODE_NONE] = "",
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};
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/* Backplane modes:
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* are considered a sub-type of phy_interface_t: XGMII
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* and are specified in "phy-connection-type" with one of the following strings
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*/
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static const char * const backplane_mode_strings[] = {
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"10gbase-kr",
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"40gbase-kr4",
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};
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static inline const char *phy_string_for_interface(phy_interface_t i)
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{
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/* Default to unknown */
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if (i > PHY_INTERFACE_MODE_NONE)
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i = PHY_INTERFACE_MODE_NONE;
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return phy_interface_strings[i];
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}
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static inline bool is_backplane_mode(const char *phyconn)
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{
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int i;
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if (!phyconn)
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return false;
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for (i = 0; i < ARRAY_SIZE(backplane_mode_strings); i++) {
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if (!strcmp(phyconn, backplane_mode_strings[i]))
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return true;
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}
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return false;
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}
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#endif /* _PHY_INTERFACE_H */
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