83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
85 lines
2.9 KiB
C
85 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* DP83848 ethernet Physical layer
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*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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*/
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/* National Semiconductor PHYSICAL LAYER TRANSCEIVER DP83848 */
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#define DP83848_CTL_REG 0x0 /* Basic Mode Control Reg */
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#define DP83848_STAT_REG 0x1 /* Basic Mode Status Reg */
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#define DP83848_PHYID1_REG 0x2 /* PHY Idendifier Reg 1 */
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#define DP83848_PHYID2_REG 0x3 /* PHY Idendifier Reg 2 */
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#define DP83848_ANA_REG 0x4 /* Auto_Neg Advt Reg */
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#define DP83848_ANLPA_REG 0x5 /* Auto_neg Link Partner Ability Reg */
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#define DP83848_ANE_REG 0x6 /* Auto-neg Expansion Reg */
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#define DP83848_PHY_STAT_REG 0x10 /* PHY Status Register */
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#define DP83848_PHY_INTR_CTRL_REG 0x11 /* PHY Interrupt Control Register */
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#define DP83848_PHY_CTRL_REG 0x19 /* PHY Status Register */
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/*--Bit definitions: DP83848_CTL_REG */
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#define DP83848_RESET (1 << 15) /* 1= S/W Reset */
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#define DP83848_LOOPBACK (1 << 14) /* 1=loopback Enabled */
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#define DP83848_SPEED_SELECT (1 << 13)
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#define DP83848_AUTONEG (1 << 12)
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#define DP83848_POWER_DOWN (1 << 11)
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#define DP83848_ISOLATE (1 << 10)
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#define DP83848_RESTART_AUTONEG (1 << 9)
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#define DP83848_DUPLEX_MODE (1 << 8)
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#define DP83848_COLLISION_TEST (1 << 7)
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/*--Bit definitions: DP83848_STAT_REG */
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#define DP83848_100BASE_T4 (1 << 15)
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#define DP83848_100BASE_TX_FD (1 << 14)
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#define DP83848_100BASE_TX_HD (1 << 13)
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#define DP83848_10BASE_T_FD (1 << 12)
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#define DP83848_10BASE_T_HD (1 << 11)
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#define DP83848_MF_PREAMB_SUPPR (1 << 6)
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#define DP83848_AUTONEG_COMP (1 << 5)
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#define DP83848_RMT_FAULT (1 << 4)
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#define DP83848_AUTONEG_ABILITY (1 << 3)
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#define DP83848_LINK_STATUS (1 << 2)
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#define DP83848_JABBER_DETECT (1 << 1)
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#define DP83848_EXTEND_CAPAB (1 << 0)
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/*--definitions: DP83848_PHYID1 */
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#define DP83848_PHYID1_OUI 0x2000
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#define DP83848_PHYID2_OUI 0x5c90
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/*--Bit definitions: DP83848_ANAR, DP83848_ANLPAR */
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#define DP83848_NP (1 << 15)
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#define DP83848_ACK (1 << 14)
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#define DP83848_RF (1 << 13)
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#define DP83848_PAUSE (1 << 10)
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#define DP83848_T4 (1 << 9)
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#define DP83848_TX_FDX (1 << 8)
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#define DP83848_TX_HDX (1 << 7)
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#define DP83848_10_FDX (1 << 6)
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#define DP83848_10_HDX (1 << 5)
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#define DP83848_AN_IEEE_802_3 0x0001
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/*--Bit definitions: DP83848_ANER */
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#define DP83848_PDF (1 << 4)
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#define DP83848_LP_NP_ABLE (1 << 3)
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#define DP83848_NP_ABLE (1 << 2)
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#define DP83848_PAGE_RX (1 << 1)
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#define DP83848_LP_AN_ABLE (1 << 0)
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/*--Bit definitions: DP83848_PHY_STAT */
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#define DP83848_RX_ERR_LATCH (1 << 13)
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#define DP83848_POLARITY_STAT (1 << 12)
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#define DP83848_FALSE_CAR_SENSE (1 << 11)
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#define DP83848_SIG_DETECT (1 << 10)
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#define DP83848_DESCRAM_LOCK (1 << 9)
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#define DP83848_PAGE_RCV (1 << 8)
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#define DP83848_PHY_RMT_FAULT (1 << 6)
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#define DP83848_JABBER (1 << 5)
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#define DP83848_AUTONEG_COMPLETE (1 << 4)
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#define DP83848_LOOPBACK_STAT (1 << 3)
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#define DP83848_DUPLEX (1 << 2)
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#define DP83848_SPEED (1 << 1)
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#define DP83848_LINK (1 << 0)
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