u-boot

History

Wolfgang Denk 64134f0112 Fix linker scripts: add NOLOAD atribute to .bss/.sbss sections With recent toolchain versions, some boards would not build because or errors like this one (here for ocotea board when building with ELDK 4.2 beta): ppc_4xx-ld: section .bootpg [fffff000 -> fffff23b] overlaps section .bss [fffee900 -> fffff8ab] For many boards, the .bss section is big enough that it wraps around at the end of the address space (0xFFFFFFFF), so the problem will not be visible unless you use a 64 bit tool chain for development. On some boards however, changes to the code size (due to different optimizations) we bail out with section overlaps like above. The fix is to add the NOLOAD attribute to the .bss and .sbss sections, telling the linker that .bss does not consume any space in the image. Signed-off-by: Wolfgang Denk <wd@denx.de>		2008-01-12 20:31:39 +01:00
..
config.mk	* Patch by Stephen Williams, 01 Apr 2004:	2004-04-15 23:14:49 +00:00
flash.c	Patch by Stephen Williams, 11 May 2004:	2004-06-09 00:15:33 +00:00
host_bridge.c	* Code cleanup, mostly for GCC-3.3.x	2004-12-31 09:32:47 +00:00
init.S	* Patch by Stephen Williams, 01 Apr 2004:	2004-04-15 23:14:49 +00:00
jse_priv.h	* Patch by Stephen Williams, 01 Apr 2004:	2004-04-15 23:14:49 +00:00
jse.c	* Patch by Stephen Williams, 01 Apr 2004:	2004-04-15 23:14:49 +00:00
Makefile	Move "ar" flags to config.mk to allow for silent "make -s"	2006-10-09 01:02:05 +02:00
README.txt	* Patch by Stephen Williams, 01 Apr 2004:	2004-04-15 23:14:49 +00:00
sdram.c	* Patch by Stephen Williams, 01 Apr 2004:	2004-04-15 23:14:49 +00:00
u-boot.lds	Fix linker scripts: add NOLOAD atribute to .bss/.sbss sections	2008-01-12 20:31:39 +01:00

README.txt

JSE Configuration Details

Memory Bank 0 -- Flash chip
---------------------------

0xfff00000 - 0xffffffff

The flash chip is really only 512Kbytes, but the high address bit of
the 1Meg region is ignored, so the flash is replicated through the
region. Thus, this is consistent with a flash base address 0xfff80000.

The placement at the end is to be consistent with reset behavior,
where the processor itself initially uses this bus to load the branch
vector and start running.

On-Chip Memory
--------------

0xf4000000 - 0xf4000fff

The 405GPr includes a 4K on-chip memory that can be placed however
software chooses. I choose to place the memory at this address, to
keep it out of the cachable areas.


Memory Bank 1 -- SystemACE Controller
-------------------------------------

0xf0000000 - 0xf00fffff

The SystemACE chip is along on peripheral bank CS#1. We don't need
much space, but 1Meg is the smallest we can configure the chip to
allocate. We need it far away from the flash region, because this
region is set to be non-cached.


Internal Peripherals
--------------------

0xef600300 - 0xef6008ff

These are scattered various peripherals internal to the PPC405GPr
chip.

SDRAM
-----

0x00000000 - 0x07ffffff  (128 MBytes)