22fe68fbdc
This patch introduces proper ARM vector handling for i.MX28 CPU. This issue wasn't addressed because the interrupts weren't enabled on any ARMv5 core, therefore the issue wasn't noticed earlier. In previous implementation, the vectoring code used by i.MX28 CPU when an exception happened was that of the SPL. With this change, the branch target when an exception happens can be reconfigured by U-Boot. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
235 lines
5.4 KiB
ArmAsm
235 lines
5.4 KiB
ArmAsm
/*
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* armboot - Startup Code for ARM926EJS CPU-core
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*
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* Copyright (c) 2003 Texas Instruments
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*
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* ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
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*
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* Copyright (c) 2001 Marius Groger <mag@sysgo.de>
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* Copyright (c) 2002 Alex Zupke <azu@sysgo.de>
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* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
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* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
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* Copyright (c) 2003 Kshitij <kshitij@ti.com>
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* Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
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*
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* Change to support call back into iMX28 bootrom
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* Copyright (c) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <common.h>
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#include <version.h>
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#if defined(CONFIG_OMAP1610)
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#include <./configs/omap1510.h>
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#elif defined(CONFIG_OMAP730)
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#include <./configs/omap730.h>
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#endif
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/*
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*************************************************************************
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*
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* Jump vector table as in table 3.1 in [1]
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*
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*************************************************************************
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*/
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.globl _start
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_start:
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b reset
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b undefined_instruction
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b software_interrupt
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b prefetch_abort
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b data_abort
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b not_used
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b irq
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b fiq
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/*
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* Vector table, located at address 0x20.
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* This table allows the code running AFTER SPL, the U-Boot, to install it's
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* interrupt handlers here. The problem is that the U-Boot is loaded into RAM,
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* including it's interrupt vectoring table and the table at 0x0 is still the
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* SPLs. So if interrupt happens in U-Boot, the SPLs interrupt vectoring table
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* is still used.
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*/
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_vt_reset:
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.word _reset
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_vt_undefined_instruction:
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.word _hang
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_vt_software_interrupt:
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.word _hang
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_vt_prefetch_abort:
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.word _hang
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_vt_data_abort:
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.word _hang
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_vt_not_used:
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.word _reset
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_vt_irq:
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.word _hang
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_vt_fiq:
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.word _hang
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reset:
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ldr pc, _vt_reset
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undefined_instruction:
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ldr pc, _vt_undefined_instruction
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software_interrupt:
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ldr pc, _vt_software_interrupt
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prefetch_abort:
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ldr pc, _vt_prefetch_abort
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data_abort:
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ldr pc, _vt_data_abort
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not_used:
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ldr pc, _vt_not_used
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irq:
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ldr pc, _vt_irq
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fiq:
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ldr pc, _vt_fiq
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.balignl 16,0xdeadbeef
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/*
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*************************************************************************
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*
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* Startup Code (reset vector)
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*
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* do important init only if we don't start from memory!
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* setup Memory and board specific bits prior to relocation.
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* relocate armboot to ram
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* setup stack
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*
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*************************************************************************
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*/
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.globl _TEXT_BASE
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_TEXT_BASE:
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.word CONFIG_SYS_TEXT_BASE
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/*
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* These are defined in the board-specific linker script.
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* Subtracting _start from them lets the linker put their
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* relative position in the executable instead of leaving
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* them null.
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*/
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.globl _bss_start_ofs
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_bss_start_ofs:
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.word __bss_start - _start
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.globl _bss_end_ofs
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_bss_end_ofs:
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.word __bss_end__ - _start
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.globl _end_ofs
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_end_ofs:
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.word _end - _start
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#ifdef CONFIG_USE_IRQ
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/* IRQ stack memory (calculated at run-time) */
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.globl IRQ_STACK_START
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IRQ_STACK_START:
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.word 0x0badc0de
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/* IRQ stack memory (calculated at run-time) */
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.globl FIQ_STACK_START
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FIQ_STACK_START:
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.word 0x0badc0de
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#endif
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/* IRQ stack memory (calculated at run-time) + 8 bytes */
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.globl IRQ_STACK_START_IN
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IRQ_STACK_START_IN:
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.word 0x0badc0de
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/*
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* the actual reset code
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*/
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_reset:
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/*
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* Store all registers on old stack pointer, this will allow us later to
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* return to the BootROM and let the BootROM load U-Boot into RAM.
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*/
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push {r0-r12,r14}
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/*
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* set the cpu to SVC32 mode
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*/
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mrs r0,cpsr
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bic r0,r0,#0x1f
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orr r0,r0,#0xd3
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msr cpsr,r0
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/*
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* we do sys-critical inits only at reboot,
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* not when booting from ram!
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*/
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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bl cpu_init_crit
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#endif
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bl board_init_ll
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pop {r0-r12,r14}
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bx lr
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/*
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*************************************************************************
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*
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* CPU_init_critical registers
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*
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* setup important registers
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* setup memory timing
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*
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*************************************************************************
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*/
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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cpu_init_crit:
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/*
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* flush v4 I/D caches
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*/
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
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mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
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/*
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* disable MMU stuff and caches
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*/
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
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bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
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orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
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orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
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mcr p15, 0, r0, c1, c0, 0
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mov pc, lr /* back to my caller */
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.align 5
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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_hang:
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ldr sp, _TEXT_BASE /* switch to abort stack */
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1:
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bl 1b /* hang and never return */
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