52923c6db7
AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
65 lines
1.1 KiB
Plaintext
65 lines
1.1 KiB
Plaintext
menu "RISC-V architecture"
|
|
depends on RISCV
|
|
|
|
config SYS_ARCH
|
|
default "riscv"
|
|
|
|
choice
|
|
prompt "Target select"
|
|
optional
|
|
|
|
config TARGET_AX25_AE350
|
|
bool "Support ax25-ae350"
|
|
|
|
config TARGET_QEMU_VIRT
|
|
bool "Support QEMU Virt Board"
|
|
|
|
endchoice
|
|
|
|
# board-specific options below
|
|
source "board/AndesTech/ax25-ae350/Kconfig"
|
|
source "board/emulation/qemu-riscv/Kconfig"
|
|
|
|
# platform-specific options below
|
|
source "arch/riscv/cpu/ax25/Kconfig"
|
|
|
|
# architecture-specific options below
|
|
|
|
choice
|
|
prompt "Base ISA"
|
|
default ARCH_RV32I
|
|
|
|
config ARCH_RV32I
|
|
bool "RV32I"
|
|
select 32BIT
|
|
help
|
|
Choose this option to target the RV32I base integer instruction set.
|
|
|
|
config ARCH_RV64I
|
|
bool "RV64I"
|
|
select 64BIT
|
|
select PHYS_64BIT
|
|
help
|
|
Choose this option to target the RV64I base integer instruction set.
|
|
|
|
endchoice
|
|
|
|
config RISCV_ISA_C
|
|
bool "Emit compressed instructions"
|
|
default y
|
|
help
|
|
Adds "C" to the ISA subsets that the toolchain is allowed to emit
|
|
when building U-Boot, which results in compressed instructions in the
|
|
U-Boot binary.
|
|
|
|
config RISCV_ISA_A
|
|
def_bool y
|
|
|
|
config 32BIT
|
|
bool
|
|
|
|
config 64BIT
|
|
bool
|
|
|
|
endmenu
|