83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
172 lines
4.3 KiB
C
172 lines
4.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016-2017 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#include <linux/errno.h>
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#include <asm/global_data.h>
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#include <asm/gpio.h>
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#include <dt-bindings/gpio/uniphier-gpio.h>
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#define UNIPHIER_GPIO_PORT_DATA 0x0 /* data */
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#define UNIPHIER_GPIO_PORT_DIR 0x4 /* direction (1:in, 0:out) */
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#define UNIPHIER_GPIO_IRQ_EN 0x90 /* irq enable */
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struct uniphier_gpio_priv {
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void __iomem *regs;
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};
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static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank)
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{
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unsigned int reg;
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reg = (bank + 1) * 8;
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/*
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* Unfortunately, the GPIO port registers are not contiguous because
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* offset 0x90-0x9f is used for IRQ. Add 0x10 when crossing the region.
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*/
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if (reg >= UNIPHIER_GPIO_IRQ_EN)
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reg += 0x10;
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return reg;
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}
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static void uniphier_gpio_get_bank_and_mask(unsigned int offset,
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unsigned int *bank, u32 *mask)
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{
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*bank = offset / UNIPHIER_GPIO_LINES_PER_BANK;
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*mask = BIT(offset % UNIPHIER_GPIO_LINES_PER_BANK);
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}
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static void uniphier_gpio_reg_update(struct uniphier_gpio_priv *priv,
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unsigned int reg, u32 mask, u32 val)
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{
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u32 tmp;
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tmp = readl(priv->regs + reg);
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tmp &= ~mask;
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tmp |= mask & val;
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writel(tmp, priv->regs + reg);
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}
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static void uniphier_gpio_bank_write(struct udevice *dev, unsigned int bank,
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unsigned int reg, u32 mask, u32 val)
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{
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struct uniphier_gpio_priv *priv = dev_get_priv(dev);
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if (!mask)
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return;
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uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg,
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mask, val);
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}
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static void uniphier_gpio_offset_write(struct udevice *dev, unsigned int offset,
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unsigned int reg, int val)
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{
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unsigned int bank;
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u32 mask;
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uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
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uniphier_gpio_bank_write(dev, bank, reg, mask, val ? mask : 0);
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}
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static int uniphier_gpio_offset_read(struct udevice *dev,
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unsigned int offset, unsigned int reg)
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{
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struct uniphier_gpio_priv *priv = dev_get_priv(dev);
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unsigned int bank, reg_offset;
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u32 mask;
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uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
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reg_offset = uniphier_gpio_bank_to_reg(bank) + reg;
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return !!(readl(priv->regs + reg_offset) & mask);
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}
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static int uniphier_gpio_get_function(struct udevice *dev, unsigned int offset)
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{
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return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_PORT_DIR) ?
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GPIOF_INPUT : GPIOF_OUTPUT;
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}
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static int uniphier_gpio_direction_input(struct udevice *dev,
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unsigned int offset)
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{
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uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DIR, 1);
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return 0;
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}
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static int uniphier_gpio_direction_output(struct udevice *dev,
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unsigned int offset, int value)
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{
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uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DATA, value);
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uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DIR, 0);
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return 0;
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}
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static int uniphier_gpio_get_value(struct udevice *dev, unsigned int offset)
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{
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return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_PORT_DATA);
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}
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static int uniphier_gpio_set_value(struct udevice *dev,
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unsigned int offset, int value)
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{
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uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DATA, value);
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return 0;
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}
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static const struct dm_gpio_ops uniphier_gpio_ops = {
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.direction_input = uniphier_gpio_direction_input,
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.direction_output = uniphier_gpio_direction_output,
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.get_value = uniphier_gpio_get_value,
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.set_value = uniphier_gpio_set_value,
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.get_function = uniphier_gpio_get_function,
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};
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static int uniphier_gpio_probe(struct udevice *dev)
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{
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struct uniphier_gpio_priv *priv = dev_get_priv(dev);
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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fdt_addr_t addr;
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addr = devfdt_get_addr(dev);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->regs = devm_ioremap(dev, addr, SZ_512);
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if (!priv->regs)
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return -ENOMEM;
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uc_priv->gpio_count = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
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"ngpios", 0);
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return 0;
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}
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static const struct udevice_id uniphier_gpio_match[] = {
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{ .compatible = "socionext,uniphier-gpio" },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(uniphier_gpio) = {
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.name = "uniphier-gpio",
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.id = UCLASS_GPIO,
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.of_match = uniphier_gpio_match,
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.probe = uniphier_gpio_probe,
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.priv_auto_alloc_size = sizeof(struct uniphier_gpio_priv),
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.ops = &uniphier_gpio_ops,
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};
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