e1fd16b6f5
Added fsl_ddr_get_version() function to for DDR3 to poll DDRC IP version (major, minor, errata) to determine if unique mode registers are available. If true, always use unique mode registers. Dynamic ODT is enabled if needed. The table is documented in doc/README.fsl-ddr. This function may also need to be extend for future other platforms if such a feature exists. Enable address parity and RCW by default for RDIMMs. Change default output driver impedance from 34 ohm to 40ohm. Make it 34ohm for quad-rank RDIMMs. Use a formula to calculate rodt_on for timing_cfg_5. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
173 lines
10 KiB
Plaintext
173 lines
10 KiB
Plaintext
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Table of interleaving modes supported in cpu/8xxx/ddr/
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======================================================
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+-------------+---------------------------------------------------------+
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| | Rank Interleaving |
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| +--------+-----------+-----------+------------+-----------+
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|Memory | | | | 2x2 | 4x1 |
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|Controller | None | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ |
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|Interleaving | | {CS0+CS1} | {CS2+CS3} | {CS2+CS3} | CS2+CS3} |
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+-------------+--------+-----------+-----------+------------+-----------+
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|None | Yes | Yes | Yes | Yes | Yes |
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+-------------+--------+-----------+-----------+------------+-----------+
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|Cacheline | Yes | Yes | No | No, Only(*)| Yes |
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| |CS0 Only| | | {CS0+CS1} | |
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+-------------+--------+-----------+-----------+------------+-----------+
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|Page | Yes | Yes | No | No, Only(*)| Yes |
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| |CS0 Only| | | {CS0+CS1} | |
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+-------------+--------+-----------+-----------+------------+-----------+
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|Bank | Yes | Yes | No | No, Only(*)| Yes |
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| |CS0 Only| | | {CS0+CS1} | |
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+-------------+--------+-----------+-----------+------------+-----------+
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|Superbank | No | Yes | No | No, Only(*)| Yes |
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| | | | | {CS0+CS1} | |
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+-------------+--------+-----------+-----------+------------+-----------+
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(*) Although the hardware can be configured with memory controller
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interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1}
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from each controller. {CS2+CS3} on each controller are only rank
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interleaved on that controller.
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For memory controller interleaving, identical DIMMs are suggested. Software
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doesn't check the size or organization of interleaved DIMMs.
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The ways to configure the ddr interleaving mode
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==============================================
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1. In board header file(e.g.MPC8572DS.h), add default interleaving setting
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under "CONFIG_EXTRA_ENV_SETTINGS", like:
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"hwconfig=fsl_ddr:ctlr_intlv=bank" \
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......
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2. Run u-boot "setenv" command to configure the memory interleaving mode.
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Either numerical or string value is accepted.
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# disable memory controller interleaving
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setenv hwconfig "fsl_ddr:ctlr_intlv=null"
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# cacheline interleaving
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setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline"
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# page interleaving
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setenv hwconfig "fsl_ddr:ctlr_intlv=page"
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# bank interleaving
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setenv hwconfig "fsl_ddr:ctlr_intlv=bank"
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# superbank
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setenv hwconfig "fsl_ddr:ctlr_intlv=superbank"
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# disable bank (chip-select) interleaving
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setenv hwconfig "fsl_ddr:bank_intlv=null"
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# bank(chip-select) interleaving cs0+cs1
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setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1"
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# bank(chip-select) interleaving cs2+cs3
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setenv hwconfig "fsl_ddr:bank_intlv=cs2_cs3"
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# bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3) (2x2)
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setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_and_cs2_cs3"
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# bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
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setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"
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Memory controller address hashing
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==================================
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If the DDR controller supports address hashing, it can be enabled by hwconfig.
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Syntax is:
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hwconfig=fsl_ddr:addr_hash=true
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Memory controller ECC on/off
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============================
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If ECC is enabled in board configuratoin file, i.e. #define CONFIG_DDR_ECC,
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ECC can be turned on/off by hwconfig.
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Syntax is
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hwconfig=fsl_ddr:ecc=off
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Memory testing options for mpc85xx
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==================================
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1. Memory test can be done once U-boot prompt comes up using mtest, or
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2. Memory test can be done with Power-On-Self-Test function, activated at
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compile time.
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In order to enable the POST memory test, CONFIG_POST needs to be
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defined in board configuraiton header file. By default, POST memory test
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performs a fast test. A slow test can be enabled by changing the flag at
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compiling time. To test memory bigger than 2GB, 36BIT support is needed.
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Memory is tested within a 2GB window. TLBs are used to map the virtual 2GB
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window to physical address so that all physical memory can be tested.
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Combination of hwconfig
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=======================
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Hwconfig can be combined with multiple parameters, for example, on a supported
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platform
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hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,ecc=on
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Table for dynamic ODT for DDR3
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==============================
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For single-slot system with quad-rank DIMM and dual-slot system, dynamic ODT may
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be needed, depending on the configuration. The numbers in the following tables are
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in Ohms.
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* denotes dynamic ODT
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Two slots system
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+-----------------------+----------+---------------+-----------------------------+-----------------------------+
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| Configuration | |DRAM controller| Slot 1 | Slot 2 |
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+-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+
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| | | | | | Rank 1 | Rank 2 | Rank 1 | Rank 2 |
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+ Slot 1 | Slot 2 |Write/Read| Write | Read |-------+------+-------+------+-------+------+-------+------+
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| | | | | | Write | Read | Write | Read | Write | Read | Write | Read |
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+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | | Slot 1 | off | 75 | 120 | off | off | off | off | off | 30 | 30 |
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| Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | | Slot 2 | off | 75 | off | off | 30 | 30 | 120 | off | off | off |
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+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | | Slot 1 | off | 75 | 120 | off | off | off | 20 | 20 | | |
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| Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | | Slot 2 | off | 75 | off | off | 20 | 20 | 120 *| off | | |
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+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | | Slot 1 | off | 75 | 120 *| off | | | off | off | 20 | 20 |
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|Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | | Slot 2 | off | 75 | 20 | 20 | | | 120 | off | off | off |
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+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | | Slot 1 | off | 75 | 120 *| off | | | 30 | 30 | | |
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|Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | | Slot 2 | off | 75 | 30 | 30 | | | 120 *| off | | |
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+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| Dual Rank | Empty | Slot 1 | off | 75 | 40 | off | off | off | | | | |
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+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| Empty | Dual Rank | Slot 2 | off | 75 | | | | | 40 | off | off | off |
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+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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|Single Rank| Empty | Slot 1 | off | 75 | 40 | off | | | | | | |
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+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| Empty |Single Rank| Slot 2 | off | 75 | | | | | 40 | off | | |
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+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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Single slot system
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+-------------+------------+---------------+-----------------------------+-----------------------------+
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| | |DRAM controller| Rank 1 | Rank 2 | Rank 3 | Rank 4 |
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|Configuration| Write/Read |-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | | Write | Read | Write | Read | Write | Read | Write | Read | Write | Read |
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+-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | R1 | off | 75 | 120 *| off | off | off | 20 | 20 | off | off |
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| |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | R2 | off | 75 | off | 20 | 120 | off | 20 | 20 | off | off |
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| Quad Rank |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | R3 | off | 75 | 20 | 20 | off | off | 120 *| off | off | off |
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| |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | R4 | off | 75 | 20 | 20 | off | off | off | 20 | 120 | off |
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+-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
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| | R1 | off | 75 | 40 | off | off | off |
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| Dual Rank |------------+-------+-------+-------+------+-------+------+
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| | R2 | off | 75 | 40 | off | off | off |
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+-------------+------------+-------+-------+-------+------+-------+------+
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| Single Rank | R1 | off | 75 | 40 | off |
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+-------------+------------+-------+-------+-------+------+
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Reference http://www.xrosstalkmag.com/mag_issues/xrosstalk_oct08_final.pdf
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http://download.micron.com/pdf/technotes/ddr3/tn4108_ddr3_design_guide.pdf
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