3bb3f266ee
The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper logic to integrate these blocks in the device. The DDR subsystem is used to provide an interface to external SDRAM devices which can be utilized for storing program or data. Introduce support for the DDR controller and DDR phy within the DDR subsystem. Signed-off-by: Kevin Scholz <k-scholz@ti.com Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> |
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| .. | ||
| cps_drv_lpddr4.h | ||
| k3-j721e-ddrss.c | ||
| lpddr4_address_slice_0_macros.h | ||
| lpddr4_ctl_regs.h | ||
| lpddr4_data_slice_0_macros.h | ||
| lpddr4_data_slice_1_macros.h | ||
| lpddr4_data_slice_2_macros.h | ||
| lpddr4_data_slice_3_macros.h | ||
| lpddr4_ddr_controller_macros.h | ||
| lpddr4_if.h | ||
| lpddr4_obj_if.c | ||
| lpddr4_obj_if.h | ||
| lpddr4_phy_core_macros.h | ||
| lpddr4_pi_macros.h | ||
| lpddr4_private.h | ||
| lpddr4_sanity.h | ||
| lpddr4_structs_if.h | ||
| lpddr4.c | ||
| Makefile | ||