u-boot/board/freescale/ls1028a
Yuantian Tang 353f36d96e armv8: ls1028ardb: Add support for LS1028ARDB
LS1028A is an ARMv8 implementation. LS1028ARDB is an evaluation
platform that supports the LS1028A family SoCs. This patch add basic
support of the platform.

Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22 12:24:24 +05:30
..
ddr.c armv8: ls1028ardb: Add support for LS1028ARDB 2019-05-22 12:24:24 +05:30
Kconfig armv8: ls1028ardb: Add support for LS1028ARDB 2019-05-22 12:24:24 +05:30
ls1028a.c armv8: ls1028ardb: Add support for LS1028ARDB 2019-05-22 12:24:24 +05:30
MAINTAINERS armv8: ls1028ardb: Add support for LS1028ARDB 2019-05-22 12:24:24 +05:30
Makefile armv8: ls1028ardb: Add support for LS1028ARDB 2019-05-22 12:24:24 +05:30
README armv8: ls1028ardb: Add support for LS1028ARDB 2019-05-22 12:24:24 +05:30

Overview
--------
The LS1028A Reference Design (RDB) is a high-performance computing,
evaluation, and development platform that supports ARM SoC LS1028A and its
derivatives.

LS1028A SoC Overview
--------------------------------------
Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc

RDB Default Switch Settings (1: ON; 0: OFF)
-------------------------------------------
For XSPI NOR boot (default)
SW2: 1111_1000
SW3: 1111_0000
SW5: 0011_1001

For SD Boot
SW2: 1000_1000
SW3: 1111_0000
SW5: 0011_1001

For eMMC Boot
SW2: 1001_1000
SW3: 1111_0000
SW5: 0011_1001

LS1028ARDB board Overview
-------------------------
Processor
 Two Arm Cortex- A72 processor cores:
  - Based on 64-bit ARMv8 architecture
  - Up to 1.3 GHz operation
  - Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1
    data cache
  - Arranged as a single cluster of two cores sharing a single 1 MB L2
    cache
DDR memory
  - Five onboard 1G x8 discrete memory modules (Four data byte lanes
    ECC)
  - 32-bit data and 4-bit ECC
  - One chip select
  - Data transfer rates of up to 1.6 GT/s
  - Single-bit error correction and double-bit error detection ECC (4-bit
    check word across 32-bit data)
High-speed serial ports(SerDes)
 - Lane 0: Supports one 1 GbE RJ45 SGMII, connected through the
   Qualcomm AR8033 PHY
 - Lane 1: Supports four 1.25 GbE RJ45 QSGMII, each connected
   through the NXP F104S8A PHY
 - Lane 2: Connects to one PCIe M.2 Key-E slot to support PCIe Gen3
   (8 Gbit/s) cards
 - Lane 3: Connects to one PCIe M.2 Key-E slot or one SATA M.2 Key-B
   slot through a register mux to support either PCIe Gen 3 (8 Gbit/s) or
   SATA Gen 3 cards (6 Gbit/s) at a time
eSDHC
 - eSDHC1, eSDHC2
SPI
 - Connects to two mikroBUS sockets to support mikro-click modules,
   such as Bluetooth 4.0, 2.4 GHz IEEE 802.15.4 radio transceiver, near
   field communications (NFC) controller
Octal SPI (XSPI)
 - One 256 MB onboard XSPI serial NOR flash memory
 - One 512 MB onboard XSPI serial NAND flash memory
 - Supports a QSPI emulator for offboard QSPI emulation
I2C
 - All system devices are accessed via I2C1, which is multiplexed on
   I2C multiplexer PCA9848 to isolate address conflicts and reduce
   capacitive load
 - I2C1 is used for EEPROMs, RTC, INA220 current-power sensor,
   thermal monitor, PCIe/SATA M.2 connectors and mikro-click modules
   1 and 2
CAN
 - The two CAN DB9 ports can support CAN FD fast phase at data rates of
   up to 5 Mbit/s
Serial audio interface(SAI)
 - Audio codec SGTL5000 provides headphone and audio LINEOUT for
   stereo speakers
 - IEEE1588 interface to support audio on SAI4