* Boot failures have been discovered due to a combination of routing issues and non optimal ddr3 timings in the EMIF * Since ddr3 timings are different after significant board layout changes different timings are required for alpha, beta and production boards. Signed-off-by: Franklin S. Cooper Jr <fcooper@ti.com> |
||
---|---|---|
.. | ||
board.c | ||
board.h | ||
Makefile | ||
mux.c |