u-boot/arch/riscv
Bin Meng 215c3a7701 riscv: Mark existing SBI as v0.1 SBI
As per the new SBI specification, current SBI implementation version
is defined as 0.1 and will be removed/replaced in future. Each of the
function call in 0.1 is defined as a separate extension which makes
easier to replace them one at a time.

Rename existing implementation to reflect that. This patch is just
a preparatory patch for SBI v0.2 and doesn't introduce any functional
changes.

This commit is inspired from Linux kernel patch:
https://patchwork.kernel.org/patch/11407355/

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-03-17 11:29:54 +08:00
..
cpu riscv: Remove unnecessary instruction 2020-02-10 14:51:52 +08:00
dts riscv: dts: Add #address-cells and #size-cells in nor node 2019-12-10 08:23:10 +08:00
include/asm riscv: Mark existing SBI as v0.1 SBI 2020-03-17 11:29:54 +08:00
lib riscv: Avoid calling sbi_clear_ipi() 2020-03-17 11:29:40 +08:00
config.mk riscv: qemu: define standalone load address 2019-01-15 09:36:31 +08:00
Kconfig riscv: Add option to print registers on exception 2020-02-10 14:51:08 +08:00
Makefile riscv: add Kconfig entries for the code model 2018-12-18 09:56:26 +08:00