Simon Glass 191c008a21 x86: Implement a cache for Memory Reference Code parameters ... The memory reference code takes a very long time to 'train' its SDRAM interface, around half a second. To avoid this delay on every boot we can store the parameters from the last training sessions to speed up the next. Add an implementation of this, storing the training data in CMOS RAM and SPI flash. Signed-off-by: Simon Glass <sjg@chromium.org>		2015-01-24 06:13:45 -07:00
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cpu	x86: Implement a cache for Memory Reference Code parameters	2015-01-24 06:13:45 -07:00
dts	x86: dts: Add SPI flash MRC details for chromebook_link	2015-01-24 06:13:45 -07:00
include/asm	x86: Implement a cache for Memory Reference Code parameters	2015-01-24 06:13:45 -07:00
lib	x86: Test mtrr support flag before accessing mtrr msr	2015-01-23 17:24:55 -07:00
config.mk	x86: Remove REALMODE_BASE which is no longer used	2014-11-21 07:24:08 +01:00
Kconfig	x86: coreboot: Move coreboot-specific defines from coreboot.h to Kconfig	2015-01-13 07:25:03 -08:00
Makefile	Kbuild: introduce Makefile in arch/$ARCH/	2014-12-08 09:35:45 -05:00