150c24936b
The move is pretty straight-forward. ap20.h and tegra20.h were renamed to ap.h and tegra.h. Some files remain in arch-tegra20 but 'include' a file in 'arch-tegra' with #defines & structs that will be common between T20 and T30 HW. HW-specific #defines, etc. stay in the 'arch-tegra20' 'root' file. All boards build OK w/MAKEALL -s tegra20. Checkpatch.pl runs clean. Seaboard works OK. Signed-off-by: Tom Warren <twarren@nvidia.com>
82 lines
2.1 KiB
C
82 lines
2.1 KiB
C
/*
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* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch-tegra/mmc.h>
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#include <asm/gpio.h>
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#ifdef CONFIG_TEGRA_MMC
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#include <mmc.h>
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#endif
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/*
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* Routine: gpio_config_uart
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* Description: Does nothing on Paz00 - no conflict w/SPI.
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*/
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void gpio_config_uart(void)
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{
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}
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#ifdef CONFIG_TEGRA_MMC
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/*
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* Routine: pin_mux_mmc
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* Description: setup the pin muxes/tristate values for the SDMMC(s)
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*/
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static void pin_mux_mmc(void)
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{
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/* SDMMC4: config 3, x8 on 2nd set of pins */
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pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4);
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pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4);
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pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4);
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pinmux_tristate_disable(PINGRP_ATB);
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pinmux_tristate_disable(PINGRP_GMA);
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pinmux_tristate_disable(PINGRP_GME);
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/* SDIO1: SDIO1_CLK, SDIO1_CMD, SDIO1_DAT[3:0] */
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pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_SDIO1);
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pinmux_tristate_disable(PINGRP_SDIO1);
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/* For power GPIO PV1 */
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pinmux_tristate_disable(PINGRP_UAC);
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/* For CD GPIO PV5 */
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pinmux_tristate_disable(PINGRP_GPV);
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}
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/* this is a weak define that we are overriding */
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int board_mmc_init(bd_t *bd)
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{
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debug("board_mmc_init called\n");
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/* Enable muxes, etc. for SDMMC controllers */
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pin_mux_mmc();
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debug("board_mmc_init: init eMMC\n");
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/* init dev 0, eMMC chip, with 4-bit bus */
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/* The board has an 8-bit bus, but 8-bit doesn't work yet */
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tegra_mmc_init(0, 4, -1, -1);
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debug("board_mmc_init: init SD slot\n");
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/* init dev 3, SD slot, with 4-bit bus */
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tegra_mmc_init(3, 4, GPIO_PV1, GPIO_PV5);
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return 0;
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}
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#endif
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