Allow VDD voltage overriding with a command. This is an add-on feasture of VID. To override VDD, use command vdd_override with the value of voltage in mV, for example vdd_override <voltage in mV, eg. 1050> The above example will set the VDD to 1.050 volt. Any wrong value out of range of 0.8188 to 1.2125 volt or invalid string is ignored. In addition to the command, if overriding VDD is needed earlier in booting process, save an variable and reboot: setenv t4240qds_vdd_mv <voltage in mV> saveenv Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
123 lines
4.9 KiB
Plaintext
123 lines
4.9 KiB
Plaintext
Overview
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--------
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The T4240QDS is a high-performance computing evaluation, development and test
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platform supporting the T4240 QorIQ™ Power Architecture™ processor. T4240QDS is
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optimized to support the high-bandwidth DDR3 memory ports, as well as the
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highly-configurable SerDes ports. The system is lead-free and RoHS-compliant.
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Board Features
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SERDES Connections
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32 lanes grouped into four 8-lane banks
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Two “front side” banks dedicated to Ethernet
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- High-speed crosspoint switch fabric on selected lanes
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- Two PCI Express slots with side-band connector supporting
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- SGMII
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- XAUI
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- HiGig
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- I-pass connectors allow board-to-board and loopback support
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Two “back side” banks dedicated to other protocols
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- High-speed crosspoint switch fabric on all lanes
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- Four PCI Express slots with side-band connector supporting
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- PCI Express 3.0
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- SATA 2.0
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- SRIO 2.0
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- Supports 4X Aurora debug with two connectors
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DDR Controllers
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Three independant 64-bit DDR3 controllers
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Supports rates of 1866 up to 2133 MHz data-rate
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Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller
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DDR power supplies 1.5V to all devices with automatic tracking of VTT.
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Power software-switchable to 1.35V if software detects all DDR3LP devices.
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MT9JSF25672AZ-2G1KZESZF has been tested at 1333, 1600, 1867, 2000 and
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2133MT/s speeds. For 1867MT/s and above, read-to-write turnaround time
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increases by 1 clock.
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IFC/Local Bus
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NAND flash: 8-bit, async or sync, up to 2GB.
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NOR: 16-bit, Address/Data Multiplexed (ADM), up to 128 MB
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NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
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- NOR devices support 16 virtual banks
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GASIC: Minimal target within Qixis FPGA
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PromJET rapid memory download support
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Address demultiplexing handled within FPGA.
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- Flexible demux allows 8 or 16 bit evaluation.
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IFC Debug/Development card
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- Support for 32-bit devices
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Ethernet
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Support two on-board RGMII 10/100/1G ethernet ports.
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SGMII and XAUI support via SERDES block (see above).
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1588 support via Symmetricom board.
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QIXIS System Logic FPGA
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Manages system power and reset sequencing
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Manages DUT, board, clock, etc. configuration for dynamic shmoo
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Collects V-I-T data in background for code/power profiling.
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Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion)
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General fault monitoring and logging
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Runs from ATX “hot” power rails allowing operation while system is off.
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Clocks
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System and DDR clock (SYSCLK, “DDRCLK”)
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- Switch selectable to one of 16 common settings in the interval 33MHz-166MHz.
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- Software selectable in 1MHz increments from 1-200MHz.
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SERDES clocks
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- Provides clocks to all SerDes blocks and slots
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- 100, 125 and 156.25 MHz
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Power Supplies
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Dedicated regulators for VDD
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- Adjustable from (0.7V to 1.3V at 80A
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- Regulators can be controlled by VID and/or software
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Dedicated regulator for GVDD_PL: 1.35/1.5V at 22A
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- VTT/MVREF automatically track operating voltage
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Dedicated regulators/filters for AVDD supplies
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Dedicated regulators for other supplies: OVDD, BVDD, DVDD, LVDD, POVDD, etc.
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USB
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Supports two USB 2.0 ports with integrated PHYs
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- One type A, one type micro-AB with 1.0A power per port.
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Other IO
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eSDHC/MMC
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- SDHC card slot
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eSPI port
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- High-speed serial flash
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Two Serial port
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Four I2C ports
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Memory map
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----------
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The addresses in brackets are physical addresses.
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0x0_0000_0000 (0x0_0000_0000) - 0x0_7fff_ffff 2GB DDR (more than 2GB is initialized but not mapped under with TLB)
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0x0_8000_0000 (0xc_0000_0000) - 0x0_dfff_ffff 1.5GB PCIE memory
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0x0_f000_0000 (0xf_0000_0000) - 0x0_f03f_ffff 4MB DCSR
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0x0_f400_0000 (0xf_f400_0000) - 0x0_f5ff_ffff 32MB BMan
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0x0_f600_0000 (0xf_f600_0000) - 0x0_f7ff_ffff 32MB QMan
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0x0_f800_0000 (0xf_f800_0000) - 0x0_f803_ffff 256KB PCIE IO
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0x0_e000_0000 (0xf_e000_0000) - 0x0_efff_ffff 256MB NOR flash
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0x0_fe00_0000 (0xf_fe00_0000) - 0x0_feff_ffff 16MB CCSR
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0x0_ffdf_0000 (0xf_ffdf_0000) - 0x0_ffdf_03ff 4KB QIXIS
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0x0_ffff_f000 (0x0_7fff_fff0) - 0x0_ffff_ffff 4KB Boot page translation for secondary cores
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The physical address of the last (boot page translation) varies with the actual DDR size.
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Voltage ID and VDD override
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--------------------
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T4240 has a VID feature. U-boot reads the VID efuses and adjust the voltage
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accordingly. The voltage can also be override by command vdd_override. The
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syntax is
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vdd_override <voltage in mV>, eg. 1050 is for 1.050v.
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Upon success, the actual voltage will be read back. The value is checked
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for safety and any invalid value will not adjust the voltage.
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Another way to override VDD is to use environmental variable, in case of using
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command is too late for some debugging. The syntax is
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setenv t4240qds_vdd_mv <voltage in mV>
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saveenv
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reset
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The override voltage takes effect when booting.
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Note: voltage adjustment needs to be done step by step. Changing voltage too
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rapidly may cause current surge. The voltage stepping is done by software.
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Users can set the final voltage directly.
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