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0812a1d3e5
u-boot/arch/arm/cpu/armv7/socfpga
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Dinh Nguyen 0812a1d3e5 arm: socfpga: spl: enable sdram, timer and uart 
Add the calls in the spl_board_init to enable SDRAM, timer, and UART.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Marek Vasut <marex@denx.de>
2015-04-21 12:23:16 +02:00
..
clock_manager.c arm: socfpga: Add DW master SPI clock to clock_manager.c 2014-11-07 16:09:10 +01:00
config.mk socfpga: Fix SOCFPGA build error for Altera dev kit 2014-08-29 15:50:54 -04:00
fpga_manager.c arm: socfpga: fpga: Add SoCFPGA FPGA programming interface 2014-10-06 17:46:50 +02:00
freeze_controller.c socfpga: correctly increment freeze_controller_base address 2014-12-06 13:53:57 +01:00
lowlevel_init.S remove unnecessary version.h includes 2015-03-24 10:50:50 -04:00
Makefile arm: socfpga: fpga: Add SoCFPGA FPGA programming interface 2014-10-06 17:46:50 +02:00
misc.c Kconfig: Move CONFIG_DESIGNWARE_ETH to Kconfig 2015-04-18 11:11:36 -06:00
reset_manager.c arm: socfpga: add functions to bring sdram, timer, and uart out of reset 2015-04-21 12:23:16 +02:00
scan_manager.c socfpga: Adding Scan Manager driver 2014-07-05 00:27:27 +02:00
spl.c arm: socfpga: spl: enable sdram, timer and uart 2015-04-21 12:23:16 +02:00
system_manager.c arm: socfpga: sysmgr: Add FPGA bits into system manager 2014-10-06 17:46:50 +02:00
timer.c arm: socfpga: timer: Pull the timer reload value from config file 2014-10-06 17:46:49 +02:00
u-boot-spl.lds arm: socfpga: Zap spl.h and ad-hoc related syms 2014-10-27 02:26:24 +01:00