c5bf161fac
MIPS is no longer a part of Imagination Technologies, and as such my @imgtec.com email address will soon cease to function. This patch updates occurrances of it with my new @mips.com email address, and adds an entry in .mailmap such that git (& tools such as get_maintainer.pl when examining history) will use the new address. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: u-boot@lists.denx.de
136 lines
4.5 KiB
C
136 lines
4.5 KiB
C
/*
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* Copyright (C) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@mips.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __MSC01_H__
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#define __MSC01_H__
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/*
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* Bus Interface Unit
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*/
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#define MSC01_BIU_IP1BAS1L_OFS 0x0208
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#define MSC01_BIU_IP1MSK1L_OFS 0x0218
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#define MSC01_BIU_IP1BAS2L_OFS 0x0248
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#define MSC01_BIU_IP1MSK2L_OFS 0x0258
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#define MSC01_BIU_IP2BAS1L_OFS 0x0288
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#define MSC01_BIU_IP2MSK1L_OFS 0x0298
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#define MSC01_BIU_IP2BAS2L_OFS 0x02c8
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#define MSC01_BIU_IP2MSK2L_OFS 0x02d8
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#define MSC01_BIU_IP3BAS1L_OFS 0x0308
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#define MSC01_BIU_IP3MSK1L_OFS 0x0318
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#define MSC01_BIU_IP3BAS2L_OFS 0x0348
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#define MSC01_BIU_IP3MSK2L_OFS 0x0358
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#define MSC01_BIU_MCBAS1L_OFS 0x0388
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#define MSC01_BIU_MCMSK1L_OFS 0x0398
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#define MSC01_BIU_MCBAS2L_OFS 0x03c8
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#define MSC01_BIU_MCMSK2L_OFS 0x03d8
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/*
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* PCI Bridge
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*/
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#define MSC01_PCI_SC2PMBASL_OFS 0x0208
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#define MSC01_PCI_SC2PMMSKL_OFS 0x0218
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#define MSC01_PCI_SC2PMMAPL_OFS 0x0228
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#define MSC01_PCI_SC2PIOBASL_OFS 0x0248
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#define MSC01_PCI_SC2PIOMSKL_OFS 0x0258
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#define MSC01_PCI_SC2PIOMAPL_OFS 0x0268
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#define MSC01_PCI_P2SCMSKL_OFS 0x0308
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#define MSC01_PCI_P2SCMAPL_OFS 0x0318
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#define MSC01_PCI_INTSTAT_OFS 0x0608
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#define MSC01_PCI_CFGADDR_OFS 0x0610
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#define MSC01_PCI_CFGDATA_OFS 0x0618
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#define MSC01_PCI_HEAD0_OFS 0x2000
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#define MSC01_PCI_HEAD1_OFS 0x2008
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#define MSC01_PCI_HEAD2_OFS 0x2010
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#define MSC01_PCI_HEAD3_OFS 0x2018
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#define MSC01_PCI_HEAD4_OFS 0x2020
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#define MSC01_PCI_HEAD5_OFS 0x2028
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#define MSC01_PCI_HEAD6_OFS 0x2030
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#define MSC01_PCI_HEAD7_OFS 0x2038
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#define MSC01_PCI_HEAD8_OFS 0x2040
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#define MSC01_PCI_HEAD9_OFS 0x2048
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#define MSC01_PCI_HEAD10_OFS 0x2050
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#define MSC01_PCI_HEAD11_OFS 0x2058
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#define MSC01_PCI_HEAD12_OFS 0x2060
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#define MSC01_PCI_HEAD13_OFS 0x2068
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#define MSC01_PCI_HEAD14_OFS 0x2070
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#define MSC01_PCI_HEAD15_OFS 0x2078
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#define MSC01_PCI_BAR0_OFS 0x2220
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#define MSC01_PCI_CFG_OFS 0x2380
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#define MSC01_PCI_SWAP_OFS 0x2388
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#define MSC01_PCI_SC2PMMSKL_MSK_MSK 0xff000000
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#define MSC01_PCI_SC2PIOMSKL_MSK_MSK 0xff000000
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#define MSC01_PCI_INTSTAT_TA_SHF 6
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#define MSC01_PCI_INTSTAT_TA_MSK (0x1 << MSC01_PCI_INTSTAT_TA_SHF)
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#define MSC01_PCI_INTSTAT_MA_SHF 7
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#define MSC01_PCI_INTSTAT_MA_MSK (0x1 << MSC01_PCI_INTSTAT_MA_SHF)
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#define MSC01_PCI_CFGADDR_BNUM_SHF 16
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#define MSC01_PCI_CFGADDR_BNUM_MSK (0xff << MSC01_PCI_CFGADDR_BNUM_SHF)
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#define MSC01_PCI_CFGADDR_DNUM_SHF 11
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#define MSC01_PCI_CFGADDR_DNUM_MSK (0x1f << MSC01_PCI_CFGADDR_DNUM_SHF)
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#define MSC01_PCI_CFGADDR_FNUM_SHF 8
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#define MSC01_PCI_CFGADDR_FNUM_MSK (0x3 << MSC01_PCI_CFGADDR_FNUM_SHF)
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#define MSC01_PCI_CFGADDR_RNUM_SHF 2
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#define MSC01_PCI_CFGADDR_RNUM_MSK (0x3f << MSC01_PCI_CFGADDR_RNUM_SHF)
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#define MSC01_PCI_HEAD0_VENDORID_SHF 0
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#define MSC01_PCI_HEAD0_DEVICEID_SHF 16
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#define MSC01_PCI_HEAD2_REV_SHF 0
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#define MSC01_PCI_HEAD2_CLASS_SHF 16
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#define MSC01_PCI_CFG_EN_SHF 15
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#define MSC01_PCI_CFG_EN_MSK (0x1 << MSC01_PCI_CFG_EN_SHF)
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#define MSC01_PCI_CFG_G_SHF 16
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#define MSC01_PCI_CFG_G_MSK (0x1 << MSC01_PCI_CFG_G_SHF)
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#define MSC01_PCI_CFG_RA_SHF 17
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#define MSC01_PCI_CFG_RA_MSK (0x1 << MSC01_PCI_CFG_RA_SHF)
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#define MSC01_PCI_SWAP_BAR0_BSWAP_SHF 0
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#define MSC01_PCI_SWAP_IO_BSWAP_SHF 18
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/*
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* Peripheral Bus Controller
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*/
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#define MSC01_PBC_CLKCFG_OFS 0x0100
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#define MSC01_PBC_CS0CFG_OFS 0x0400
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#define MSC01_PBC_CS0TIM_OFS 0x0500
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#define MSC01_PBC_CS0RW_OFS 0x0600
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#define MSC01_PBC_CLKCFG_SHF 0
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#define MSC01_PBC_CLKCFG_MSK (0x1f << MSC01_PBC_CLKCFG_SHF)
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#define MSC01_PBC_CS0CFG_WS_SHF 0
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#define MSC01_PBC_CS0CFG_WS_MSK (0x1f << MSC01_PBC_CS0CFG_WS_SHF)
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#define MSC01_PBC_CS0CFG_WSIDLE_SHF 8
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#define MSC01_PBC_CS0CFG_WSIDLE_MSK (0x1f << MSC01_PBC_CS0CFG_WSIDLE_SHF)
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#define MSC01_PBC_CS0CFG_DTYP_SHF 16
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#define MSC01_PBC_CS0CFG_DTYP_MSK (0x3 << MSC01_PBC_CS0CFG_DTYP_SHF)
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#define MSC01_PBC_CS0CFG_ADM_SHF 20
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#define MSC01_PBC_CS0CFG_ADM_MSK (0x1 << MSC01_PBC_CS0CFG_ADM_SHF)
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#define MSC01_PBC_CS0TIM_CAT_SHF 0
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#define MSC01_PBC_CS0TIM_CAT_MSK (0x1f << MSC01_PBC_CS0TIM_CAT_SHF)
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#define MSC01_PBC_CS0TIM_CDT_SHF 8
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#define MSC01_PBC_CS0TIM_CDT_MSK (0x1f << MSC01_PBC_CS0TIM_CDT_SHF)
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#define MSC01_PBC_CS0RW_WAT_SHF 0
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#define MSC01_PBC_CS0RW_WAT_MSK (0x1f << MSC01_PBC_CS0RW_WAT_SHF)
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#define MSC01_PBC_CS0RW_WDT_SHF 8
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#define MSC01_PBC_CS0RW_WDT_MSK (0x1f << MSC01_PBC_CS0RW_WDT_SHF)
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#define MSC01_PBC_CS0RW_RAT_SHF 16
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#define MSC01_PBC_CS0RW_RAT_MSK (0x1f << MSC01_PBC_CS0RW_RAT_SHF)
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#define MSC01_PBC_CS0RW_RDT_SHF 24
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#define MSC01_PBC_CS0RW_RDT_MSK (0x1f << MSC01_PBC_CS0RW_RDT_SHF)
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#endif /* __MSC01_H__ */
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