9a84116b31
This patch adds definition of the number of bytes sent at once by the MC34708 PMIC. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
161 lines
3.4 KiB
C
161 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2010
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
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*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*/
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#ifndef __FSL_PMIC_H__
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#define __FSL_PMIC_H__
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/*
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* The registers of different PMIC has the same meaning
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* but the bit positions of the fields can differ or
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* some fields has a meaning only on some devices.
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* You have to check with the internal SPI bitmap
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* (see Freescale Documentation) to set the registers
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* for the device you are using
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*/
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enum {
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REG_INT_STATUS0 = 0,
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REG_INT_MASK0,
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REG_INT_SENSE0,
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REG_INT_STATUS1,
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REG_INT_MASK1,
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REG_INT_SENSE1,
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REG_PU_MODE_S,
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REG_IDENTIFICATION,
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REG_UNUSED0,
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REG_ACC0,
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REG_ACC1, /*10 */
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REG_UNUSED1,
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REG_UNUSED2,
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REG_POWER_CTL0,
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REG_POWER_CTL1,
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REG_POWER_CTL2,
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REG_REGEN_ASSIGN,
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REG_UNUSED3,
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REG_MEM_A,
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REG_MEM_B,
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REG_RTC_TIME, /*20 */
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REG_RTC_ALARM,
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REG_RTC_DAY,
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REG_RTC_DAY_ALARM,
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REG_SW_0,
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REG_SW_1,
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REG_SW_2,
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REG_SW_3,
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REG_SW_4,
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REG_SW_5,
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REG_SETTING_0, /*30 */
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REG_SETTING_1,
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REG_MODE_0,
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REG_MODE_1,
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REG_POWER_MISC,
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REG_UNUSED4,
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REG_UNUSED5,
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REG_UNUSED6,
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REG_UNUSED7,
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REG_UNUSED8,
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REG_UNUSED9, /*40 */
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REG_UNUSED10,
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REG_UNUSED11,
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REG_ADC0,
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REG_ADC1,
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REG_ADC2,
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REG_ADC3,
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REG_ADC4,
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REG_CHARGE,
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REG_USB0,
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REG_USB1, /*50 */
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REG_LED_CTL0,
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REG_LED_CTL1,
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REG_LED_CTL2,
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REG_LED_CTL3,
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REG_UNUSED12,
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REG_UNUSED13,
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REG_TRIM0,
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REG_TRIM1,
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REG_TEST0,
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REG_TEST1, /*60 */
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REG_TEST2,
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REG_TEST3,
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REG_TEST4,
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PMIC_NUM_OF_REGS,
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};
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/* REG_POWER_MISC */
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#define GPO1EN (1 << 6)
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#define GPO1STBY (1 << 7)
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#define GPO2EN (1 << 8)
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#define GPO2STBY (1 << 9)
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#define GPO3EN (1 << 10)
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#define GPO3STBY (1 << 11)
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#define GPO4EN (1 << 12)
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#define GPO4STBY (1 << 13)
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#define PWGT1SPIEN (1 << 15)
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#define PWGT2SPIEN (1 << 16)
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#define PWUP (1 << 21)
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/* Power Control 0 */
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#define COINCHEN (1 << 23)
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#define BATTDETEN (1 << 19)
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/* Interrupt status 1 */
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#define RTCRSTI (1 << 7)
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/* MC34708 Definitions */
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#define SWx_VOLT_MASK_MC34708 0x3F
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#define SWx_1_110V_MC34708 0x24
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#define SWx_1_250V_MC34708 0x30
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#define SWx_1_300V_MC34708 0x34
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#define TIMER_MASK_MC34708 0x300
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#define TIMER_4S_MC34708 0x100
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#define VUSBSEL_MC34708 (1 << 2)
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#define VUSBEN_MC34708 (1 << 3)
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#define SWBST_CTRL 31
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#define SWBST_AUTO 0x8
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#define MC34708_REG_SW12_OPMODE 28
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#define MC34708_SW1AMODE_MASK 0x00000f
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#define MC34708_SW1AMHMODE 0x000010
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#define MC34708_SW1AUOMODE 0x000020
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#define MC34708_SW1DVSSPEED 0x0000c0
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#define MC34708_SW2MODE_MASK 0x03c000
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#define MC34708_SW2MHMODE 0x040000
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#define MC34708_SW2UOMODE 0x080000
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#define MC34708_SW2DVSSPEED 0x300000
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#define MC34708_PLLEN 0x400000
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#define MC34708_PLLX 0x800000
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#define MC34708_REG_SW345_OPMODE 29
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#define MC34708_SW3MODE_MASK 0x00000f
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#define MC34708_SW3MHMODE 0x000010
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#define MC34708_SW3UOMODE 0x000020
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#define MC34708_SW4AMODE_MASK 0x0003c0
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#define MC34708_SW4AMHMODE 0x000400
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#define MC34708_SW4AUOMODE 0x000800
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#define MC34708_SW4BMODE_MASK 0x00f000
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#define MC34708_SW4BMHMODE 0x010000
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#define MC34708_SW4BUOMODE 0x020000
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#define MC34708_SW5MODE_MASK 0x3c0000
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#define MC34708_SW5MHMODE 0x400000
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#define MC34708_SW5UOMODE 0x800000
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#define SW_MODE_OFFOFF 0x00
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#define SW_MODE_PWMOFF 0x01
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#define SW_MODE_PFMOFF 0x03
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#define SW_MODE_APSOFF 0x04
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#define SW_MODE_PWMPWM 0x05
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#define SW_MODE_PWMAPS 0x06
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#define SW_MODE_APSAPS 0x08
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#define SW_MODE_APSPFM 0x0c
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#define SW_MODE_PWMPFM 0x0d
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#define SW_MODE_PFMPFM 0x0f
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#define MC34708_TRANSFER_SIZE 3
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#endif
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