7d4ce3ac58
The crystal, CPU and master clock were not displayed correctly on SAM9X60
after adding CCF clock support. Add compatible for ARM926EJ-S to fix
this.
Reported-by: Eugen Hristev <eugen.hristev@microchip.com>
Fixes: a64862284f ("clk: at91: sam9x60: add support compatible with CCF")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
125 lines
2.5 KiB
C
125 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Claudiu Beznea <claudiu.beznea@microchip.com>
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*/
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#include <common.h>
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#include <cpu.h>
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#include <dm.h>
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#include <div64.h>
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#include <linux/clk-provider.h>
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struct at91_cpu_plat {
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const char *name;
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ulong cpufreq_mhz;
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ulong mckfreq_mhz;
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ulong xtalfreq_mhz;
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};
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extern char *get_cpu_name(void);
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const char *at91_cpu_get_name(void)
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{
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return get_cpu_name();
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}
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int at91_cpu_get_desc(const struct udevice *dev, char *buf, int size)
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{
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struct at91_cpu_plat *plat = dev_get_plat(dev);
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snprintf(buf, size, "%s\n"
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"Crystal frequency: %8lu MHz\n"
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"CPU clock : %8lu MHz\n"
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"Master clock : %8lu MHz\n",
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plat->name, plat->xtalfreq_mhz, plat->cpufreq_mhz,
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plat->mckfreq_mhz);
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return 0;
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}
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static int at91_cpu_get_info(const struct udevice *dev, struct cpu_info *info)
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{
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struct at91_cpu_plat *plat = dev_get_plat(dev);
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info->cpu_freq = plat->cpufreq_mhz * 1000000;
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info->features = BIT(CPU_FEAT_L1_CACHE);
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return 0;
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}
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static int at91_cpu_get_count(const struct udevice *dev)
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{
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return 1;
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}
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static int at91_cpu_get_vendor(const struct udevice *dev, char *buf, int size)
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{
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snprintf(buf, size, "Microchip Technology Inc.");
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return 0;
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}
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static const struct cpu_ops at91_cpu_ops = {
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.get_desc = at91_cpu_get_desc,
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.get_info = at91_cpu_get_info,
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.get_count = at91_cpu_get_count,
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.get_vendor = at91_cpu_get_vendor,
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};
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static const struct udevice_id at91_cpu_ids[] = {
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{ .compatible = "arm,cortex-a7" },
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{ .compatible = "arm,arm926ej-s" },
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{ /* Sentinel. */ }
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};
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static int at91_cpu_probe(struct udevice *dev)
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{
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struct at91_cpu_plat *plat = dev_get_plat(dev);
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struct clk clk;
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ulong rate;
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int ret;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret)
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return ret;
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rate = clk_get_rate(&clk);
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if (!rate)
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return -ENOTSUPP;
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plat->cpufreq_mhz = DIV_ROUND_CLOSEST_ULL(rate, 1000000);
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ret = clk_get_by_index(dev, 1, &clk);
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if (ret)
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return ret;
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rate = clk_get_rate(&clk);
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if (!rate)
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return -ENOTSUPP;
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plat->mckfreq_mhz = DIV_ROUND_CLOSEST_ULL(rate, 1000000);
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ret = clk_get_by_index(dev, 2, &clk);
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if (ret)
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return ret;
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rate = clk_get_rate(&clk);
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if (!rate)
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return -ENOTSUPP;
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plat->xtalfreq_mhz = DIV_ROUND_CLOSEST_ULL(rate, 1000000);
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plat->name = get_cpu_name();
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return 0;
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}
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U_BOOT_DRIVER(cpu_at91_drv) = {
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.name = "at91-cpu",
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.id = UCLASS_CPU,
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.of_match = at91_cpu_ids,
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.ops = &at91_cpu_ops,
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.probe = at91_cpu_probe,
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.plat_auto = sizeof(struct at91_cpu_plat),
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.flags = DM_FLAG_PRE_RELOC,
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};
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