* Patch by Stefan Roese, 5 Jul 2005:

Update uc100 board PHY setup

CHANGELOG

@@ -1,3 +1,482 @@
+======================================================================
+Changes for U-Boot 1.1.3:
+======================================================================
+
+* Patch by Stefan Roese, 5 Jul 2005:
+  Update uc100 board PHY setup
+
+* Patch by Stefan Roese, 1 Jul 2005:
+  Fix PHY address for CATcenter board (now correct!)
+
+* Patch by Stefan Roese, 30 Jun 2005:
+  Fix PHY addresses for PPChameleon and CATcenter boards
+  Change MAINTAINER for most esd boards
+
+* Patch by Detlev Zundel, 30 Jun 2005:
+  Fix LCD logo for lwmon board which got lost in the merge of 8xx and PXA LCD code
+
+* Fix baudrate calculation problem on MPC5200 systems
+
+* Add EEPROM and RTC support for HMI1001 board
+
+* Patch by Detlev Zundel, 20 Jun 2005:
+  Fix initialization of low active GPIO pins on inka4x0 board
+
+* Enable redundant environment, disable HW flash protection of
+  HMI1001 board
+
+* Patch by Travis Sawyer, 10 Jun 2005:
+  Initialize allocated dev and private hw structures
+  after their respective allocation in 440gx_enet.c
+
+* Patch by Steven Scholz, 10 Jun 2005:
+  Fix byteorder problems with second argument of "bootm" with
+  standalone images;
+
+* Add support for HMI1001 board
+
+* Disable "date" and "sntp" commands on TQM866M
+
+* Fix watchdog reset problems on LWMON board
+
+* Patch by Juergen Selent, 17 May 2005:
+  Add support for Funkwerk VoVPN gateway module.
+
+* Cleanup debug code for MPC8220 FEC driver
+
+* Extend burst mode RAM test program to take a loop count
+  (0 = infinite)
+
+* Use CONFIG_DRIVER_KS8695ETH to enable KS8695 ethernet driver on
+  those boards that use it.
+
+* Patches by Greg Ungerer, 19 May 2005:
+  - add support for the KS8695P (ARM 922 based) CPU
+  - add support for the OpenGear CM4008, CM4116 and CM4148 boards
+
+* Patch by Steven Scholz, 19 May 2005:
+  Add support for CONFIG_SERIAL_TAG on ARM boards
+
+* Add PCI support for Sorcery board.
+  Code cleanup (especially Sorcery / Alaska / Yukon serial driver).
+
+* Fix compile problems caused by new burst mode SDRAM test;
+  make port pins to trigger logic analyzer configurable
+
+* Fix timer handling on MPC85xx systems
+
+* Fix debug code in omap5912osk flash driver
+
+* Add support for MPC8247 based "IDS8247" board.
+
+* Add support for 2 x TSEC interfaces on the TQM8540 board.
+
+* On LWMON we must use the watchdog to reset the board as the CPU
+  genereated HRESET pulse is too short to reset the external
+  circuitry.
+
+* Add test tool to exercise SDRAM accesses in burst mode
+  (as standalone program, MPC8xx/PowerPC only)
+
+* Increase CFG_MONITOR_LEN for Rattler board to match actual code
+  size.
+
+* Major upate of JFFS2 code; now in sync with snapshot of MTD CVS of
+  March 13, 2005); new configuration option CONFIG_JFFS2_LZO_LZARI
+  added to support LZO and LZARI compression modes (undefined by
+  default).
+
+* Fix problem with symbolic links in JFFS2 code.
+
+* Use linker ASSERT statement to prevent undetected overlapping of
+  sections on PPChameleon board; other boards might use this, too.
+
+* Patch by Stefan Roese, 03 May 2005:
+  Update for P3G4
+  Fix problems in cmd_universe.c
+
+* Patch by Matthias Fuchs, 03 May 2005:
+  Added missing variable declaration in cmd_nand.c
+  Modified CFG_PCI_PTM1MS in configs/PLU405.h to map 128MB ram
+
+* Fix INKA4x0: use CS1 as gpio_wkup_6 output
+
+* Fix bug in the SDRAM initialization code for canmb, IceCube and
+  PM520 boards.
+  Fix PHY address for canmb board.
+
+* Cleanup serial console baudrate calculation on AT91RM9200;
+  get rid of obsolete CFG_AT91C_BRGR_DIVISOR definition
+
+* Patch by Matthias Fuchs, 18 Apr 2005:
+  Make PCI target address spaces on PMC405 and CPCI405 boards
+  configurable via environment variables
+
+* Auto-size RAM on canmb board.
+
+* Add support for canmb board
+
+* Patch by Stefan Roese, 13 Apr 2005:
+  Update for esd apc405
+
+* Fixes for TQM8560 board:
+  - fix clock rates
+  - remove debug messages
+  - fix flash sector protection
+
+* Patch by Steven Scholz, 07 Apr 2005:
+  Add i2c_reg_write() and i2c_reg_write() for at91rm9200 I2C
+
+* Patches by Steven Scholz, 07 Apr 2005:
+  Fix compiler warning in altera.c
+  Fix warning in cpu/arm920t/at91rm9200/i2c.c
+
+* Patch by Ladislav Michl, 06 Apr 2005:
+  Fix voiceblue configuration.
+
+* Patch by Stefan Roese, 06 Apr 2005:
+  Updates for OCOTEA board:
+  - Changed U-Boot size from 512kByte to 256kByte
+  - Fixed flash driver to support boot from soldered user flash
+  - Added README for switch from PIBS firmware to U-Boot
+
+* Patch by Travis Sawyer, 05 Apr 2005:
+  - Change timer frequency for ppc 440 from 10 ms to 1 ms.
+    Problem found by Andrew Wozniak.
+
+* Patch by Steven Scholz, 06 Apr 2005:
+  - creating SoC subdir for Atmel AT91RM9200 cpu/arm920t/at91rm9200
+  - moving code out of cpu/at91rm9200 into cpu/arm920t/at91rm9200
+
+* Patches by Robert Whaley, 29 Nov 2004:
+  - update the pxa-regs.h file for PXA27x chips
+  - add PXA27x based ADSVIX board
+  - add support for MMC on PXA27x processors
+
+* Patch by Andrew E. Mileski, 28 Nov 2004:
+  Fix PPC4xx SPD SDRAM detection bug
+
+* Patch by Hiroshi Ito, 26 Nov 2004:
+  Fix logic of "test -z" and "test -n" commands
+
+* Patch by Ladislav Michl, 05 Apr 2005:
+  Add support for VoiceBlue board.
+
+* Patch by Ladislav Michl, 05 Apr 2005:
+  Fix netboot_common() prototypes.
+
+* Patch by Steven Scholz, 05 Apr 2005:
+  Use i.MX watchdog timer for reset_cpu()
+
+* Patch by Steven Scholz, 05 Apr 2005:
+  Move reset_cpu() out of cpu/arm920t/start.S into the SoC specific
+  subdirectories cpu/arm920t/imx/ and cpu/arm920t/s3c24x0/
+  (now in interupts.c)
+
+* Add support for MPC8220 based "sorcery" board.
+
+* Add support for TQM8560 board.
+
+* Add FEC support for TQM8540 board.
+  Interfaces are named as follows: "ENET1" - TSEC2, "ENET2" - FEC
+
+* Patch by Martin Krause, 04 Apr 2005:
+  Update default configuration for CMC_PU2 board.
+
+* Patch by Steven Scholz, 04 Apr 2005:
+  - remove all references to CONFIG_INIT_CRITICAL for ARM based boards
+  - introduce two new configuration options instead:
+    CONFIG_SKIP_LOWLEVEL_INIT and CONFIG_SKIP_RELOCATE_UBOOT
+
+* Patch by Steven Scholz, 04 Apr 2005:
+  Make sure that MDIO clock does not exceed 2.5 MHz on AT91
+
+* Fix timer code for ARM systems: make sure that udelay() does not
+  reset timers so it's save to use udelay() in timeout code.
+
+* Patch by Mathias K<>ster, 23 Nov 2004:
+  add udelay support for the mcf5282 cpu
+
+* Patch by Tolunay Orkun, 16 November 2004:
+  fix incorrect onboard Xilinx CPLD base address
+
+* Patch by Jerry Van Baren, 08 Nov 2004:
+  - Add low-boot option for MPC8260ADS board (if lowboot is selected,
+    the jumper for the HRCW source should select flash. If lowboot is
+    not selected, the jumper for the HRCW source should select the
+    BCSR.
+  - change default load base address to 0x00400000
+
+* Patch by Yuli Barcohen, 08 Nov 2004:
+  Add support for Analogue & Micro Rattler boards.
+  Tested on Rattler8248.
+
+* Patch by Andre Renaud, 08 Nov 2004:
+  Fix watchdog support in common/lcd.c
+
+* Patch by Marc Leeman, 05 Nov 2003:
+  Enable all 4 PCMBRW buffers for the MPC8245 processor since the CPU
+  bug only affects the XPC8245 processors
+
+* Patches by Josef Wagner, 29 Oct 2004:
+  - Add support for MicroSys CPU87 board
+  - Add support for MicroSys PM854 board
+
+* Patch by Jian Zhang, 02 Nov 2004:
+  Add 16-bit NAND support
+
+* Patch by Scott McNutt, 01 Nov 2004:
+  Add missing NIOS/NIOS2 support for "iminfo" command
+
+* Patch by Detlev Zundel, 29 Oct 2004:
+  Add missing NIOS/NIOS2 support for "mkimage" tool.
+
+* Patch by David Adair, 27 Oct 2004:
+  Add missing 440GX SDRAM Controller reset
+
+* Patch by Steven Scholz, 25 Oct 2004:
+  Declare reset_cpu() in include/common.h instead locally
+
+* Patch by Yusdi Santoso, 22 Oct 2004:
+  - Add support for HIDDEN_DRAGON board
+  - fix endianess problem in driver/rtl1839.c
+
+* Patch by Allen Curtis, 21 Oct 2004:
+  support multiple serial ports
+
+* Patch by Richard Klingler, 03 Apr 2005:
+  Add call to eth_halt() in net/net.c when called functions fail
+  after eth_init() has been called.
+
+* Patch by Sam Song, 3 April 2005:
+  - Update README.Netconsole
+  - Update README
+
+* Prepare for SoC rework of ARM code:
+  - rename CONFIG_BOOTBINFUNC into  CONFIG_INIT_CRITICAL
+  - rename memsetup into lowlevel_init (function name and source files)
+  Patch by Steven Scholz, 03 Apr 2005:
+  - create SoC specific directories include/asm-arm/arch-imx and
+    include/asm-arm/arch-s3c24x0
+
+* Fix problems with SNTP support;
+  enable SNTP support in some boards.
+
+* Patches by Martin Krause, 01 Apr 2005:
+  - Fix flash erase timeout on CMC_PU2
+  - Add automatic HW detection for CMC_PU2 and CMC_BASIC
+
+* Patch by Steven Scholz, 13 March 2005:
+  fix cache enabling for AT91RM9200
+
+* Patch by Masami Komiya, 30 Mar 2005:
+  add SNTP support and expand time server and time offset fields of
+  DHCP support. See doc/README.SNTP
+
+* Patch by Steven Scholz, 13 Dec 2004:
+  Fix bug in at91rm920 ethernet driver
+
+* Patch by Steven Scholz, 13 Dec 2004:
+  Remove duplicated code by merging memsetup.S files for
+  at91rm9200 boards into one cpu/at91rm9200/lowlevel.S
+
+* Patch by Detlev Zundel, 31 Mar 2005:
+  Cleanup duplicate definition of overwrite_console()
+
+* Update TQM5200 configuration;
+  prepare for Rev. 200 starter kit boards
+
+* Patch by Scott McNutt, 21 Oct 2004:
+  Add support for Nios-II EPCS Controller core.
+
+* Patch by Scott McNutt, 20 Oct 2004:
+  Nios-II cleanups:
+  - Add sysid command (Nios-II only).
+  - Locate default exception trampoline at proper offset.
+  - Implement I/O routines (readb, writeb, etc)
+  - Implement do_bootm_linux
+
+* Patches by Martin Krause, 22 Mar 2005:
+  - use TQM5200_auto as MAKEALL target for TQM5200 systems
+  - add support for SM501 graphics controller
+  - add support for graphic console on TQM5200
+  - add support for TQM5200 Rev 200
+  - cleanup, fix typo in include/configs/TQM5200.h
+
+* Patch by Manfred Baral, 17 Mar 2005:
+  Fix typo
+
+* Fix RTC configuration for PPChameleon board
+
+* Cleanup, fix typo in include/configs/TQM5200.h
+
+* Patch by Stefan Roese, 16 Mar 2005:
+  Update for esd auto_update and hh405 board
+
+* Adapt for U-Boot image size (new features enabled) on TQM5200
+
+* Update code for TQM8540 board (and 85xx in general):
+  - Change the name of the Ethernet driver: MOTO ENET -> ENET
+  - Reformat boot messages
+  - Enable redundant environment
+  - Replace the -O2 optimization flag with -mno-string
+
+* Patch by David Brownell, 10 Mar 2005:
+  Restore copyright statements in OHCI drivers.
+
+* Add support for TQM8540 board
+
+* Patch by Detlev Zundel, 14 Mar 2005:
+  NC650: changed NAND flash addressing to using UPMB
+
+* Patch by Stefan Roese, 14 Mar 2005:
+  Update for esd voh405 fpga image
+
+* INKA4x0: Allow initialization of LCD backlight dimming from
+  "brightness" environment variable.
+
+* Add port initialization for digital I/O on INKA4x0
+
+* Patch by Stefan Roese, 01 Mar 2005:
+  Update for esd boards dp405 and hub405
+
+* Fix get_partition_info() parameter error in all other calls
+  (common/cmd_ide.c, common/cmd_reiser.c, common/cmd_scsi.c).
+
+* Enable USB and IDE support for INKA4x0 board
+
+* Patch by Andrew Dyer, 28 Feb 2005:
+  fix ext2load passing an incorrect pointer to get_partition_info()
+  resulting in load failure for devices other than 0
+
+* Add support for SRAM and 2 x Quad UARTs on INKA4x0 board
+
+* Cleanup USB and partition defines
+
+* Add support for ext2 filesystems and image timestamps to TQM5200 board
+
+* Add reset code for Coral-P on INKA4x0 board
+
+* Patch by Martin Krause, 28 Jun 2004:
+  Update for TRAB board.
+
+* Fix some missing "volatile"s in MPC5xxx FEC driver
+
+* Fix cirrus voltage detection (for CPC45)
+
+* Fix byteorder problem in usbboot and scsiboot commands.
+
+* Patch by Cajus Hahn, 04 Feb 2005:
+  - don't insist on leading '/' for filename in ext2load
+  - set default partition to useful value (1) in ext2load
+
+* Patch by Andrew Dyer, 08 Jan 2005:
+  fix wrong return codes in ext2 code
+
+* Removed '--no-warn-mismatch' option from Makefile. This option
+  makes 'ld' to overlook binary objects compatibility.
+
+* Moved $(PLATFORM_LIBS) from the library group (--start-group ...
+  --end-group) outside of the group. This will make 'ld' to do
+  _multiple_ search in the library group when resolving symbol
+  references and do only a _single_ seach in libgcc.a after the group
+  search.
+
+* Fix stability problems on CPC45 board again.
+
+* Make image detection for diskboot / usbboot / scsiboot more robust
+  (also check header checksum)
+
+* Update CPC45 board configuration.
+
+* Add USB and PCI support for INKA4x0 board
+
+* Fix IDE stability problems on CPC45 board (needs 2 x EIEIO).
+
+* Code cleanup
+
+* Patch by Robin Getz, 13 Oct 2004:
+  Add standalone application to change SMC91C111 MAC addresses,
+  see examples/README.smc91111_eeprom
+
+* Patch by Xiaogeng (Shawn) Jin, 12 Oct 2004:
+  Fix Flash support for ARM Integrator CP.
+
+* Patch by Richard Woodruff, 10 Jan 2005:
+  Update support for OMAP2420 (ARM11) and H4 board:
+  o clean up and add new types to H4 memory probe code.
+  o fix to work with internal boot.
+  o added PRCM config III operation.
+  o fix marginal flash timings.
+  o add revison ATAG usage.
+  o enable voltage scaling at power chip.
+  o fix compile error for i2c.
+
+* Fix network problem (error when receiving multiple ARP packets)
+
+* Patch by Daniel Poirot, 12 Oct 2004:
+  Add support for Wind River sbc405 board
+
+* Patch by Rainer Brestan, 12 Oct 2004:
+  Make examples/Makefile more robust
+
+* Patch by Sam Song, 11 October 2004:
+  - Add RESET/PREBOOT/AUTOBOOT support for RPXlite_DW board
+  - Adjust CPU:BUS frequency ratio 1:1 when core frequency
+    less than 50MHz
+
+* Patch by Sam Song, 10 Oct 2004:
+  Fix a parameter error in run_command() in main.c
+
+* Patch by Richard Woodruff, 01 Oct 2004:
+  add support for the TI OMAP2420 processor and its H4 reference
+  board
+
+* Patch by Christian Pellegrin, 24 Sep 2004:
+  Added support for NE2000 compatible (DP8390, DP83902) NICs.
+
+* Patch by Leif Lindholm, 23 Sep 2004:
+  add support for the AMD db1550 board
+
+* Patch by Travis Sawyer, 15 Sep 2004:
+  Add CONFIG_SERIAL_MULTI support for ppc4xx,
+  update README.serial_multi
+
+* Patches by David Snowdon, 07 Sep 2004:
+  - add u-boot.hex target in the top level Makefile
+  - add support for the UNSW/NICTA PLEB 2 board (pleb2)
+  - use -mtune=xscale and -march=armv5 options for PXA
+
+* Patch by Florian Schlote, 08 Sep 2004:
+  Add support for SenTec-COBRA5272-board (Coldfire).
+
+* Patch by Gleb Natapov, 07 Sep 2004:
+  mpc824x: set PCI latency timer to a sane value
+  (is 0 after reset).
+
+* Patch by Kurt Stremerch, 03 Sep 2004:
+  Add bitstream configuration option for fpga command (Xilinx only).
+
+* Patch by Kurt Stremerch, 03 Sep 2004:
+  Add Xilinx Spartan2E family FPGA support
+
+* Patch by Jeff Angielski, 02 Sep 2004:
+  Add Added support for H2 revision of the EP8260 board.
+  Fixed formatting for some of the EP8260 related source files.
+
+* Patch by Jon Loeliger, 02 Sep 2004:
+  Reset monitor size back to 256 so environment can be written
+  to flash on MPC85xx ADS and CDS releases.
+
+* Patch by Paolo Broggini, 02 Sep 2004:
+  Make BSS clearing on ARM systems more robust
+
+* Patch by Yue Hu and Joe, 01 Sep 2004:
+  - add PCI support for ixp425;
+  - add EEPRO100 suppor tfor ixdp425 board.
+
+* Fix problem with protected sector detection in driver/cfi_flash.c
+
 ======================================================================
 Changes for U-Boot 1.1.2:
 ======================================================================

CREDITS

@@ -40,6 +40,7 @@ D: Unified support for Motorola MPC826xADS/MPC8272ADS/PQ2FADS boards.
 D: Support for Zephyr Engineering ZPC.1900 board.
 D: Support for Interphase iSPAN boards.
 D: Support for Analogue&Micro Adder boards.
+D: Support for Analogue&Micro Rattler boards.
 W: http://www.arabellasw.com
 
 N: Jerry van Baren
@@ -253,6 +254,10 @@ E: team@leox.org
 D: Support for LEOX boards, DS164x RTC
 W: http://www.leox.org
 
+N: Leif Lindholm
+E: leif.lindholm@i3micro.com
+D: Support for AMD dbau1550 board.
+
 N: Stephan Linz
 E: linz@li-pro.net
 D: Support for Nios Stratix Development Kit (DK-1S10)
@@ -329,7 +334,7 @@ D: BedBug embedded debugger code
 
 N: Daniel Poirot
 E: dan.poirot@windriver.com
-D: Support for the sbc8240 board
+D: Support for the Wind River sbc405, sbc8240 board
 W: http://www.windriver.com
 
 N: Stefan Roese
@@ -389,6 +394,10 @@ N: Rune Torgersen
 E: <runet@innovsys.com>
 D: Support for Motorola MPC8266ADS board
 
+N: Greg Ungerer
+E: greg.ungerer@opengear.com
+D: Support for ks8695 CPU, and OpenGear cmXXXX boards
+
 N: David Updegraff
 E: dave@cray.com
 D: Port to Cray L1 board; DHCP vendor extensions
@@ -397,6 +406,10 @@ N: Christian Vejlbo
 E: christian.vejlbo@tellabs.com
 D: FADS860T ethernet support
 
+N: Robert Whaley
+E: rwhaley@applieddata.net
+D: Port to ARM PXA27x adsvix SBC
+
 N: Martin Winistoerfer
 E: martinwinistoerfer@gmx.ch
 D: Port to MPC555/556 microcontrollers and support for cmi board

MAINTAINERS

@@ -34,6 +34,7 @@ Yuli Barcohen <yuli@arabellasw.com>
 	Adder			MPC87x/MPC852T
 	ISPAN			MPC8260
 	MPC8260ADS		MPC826x/MPC827x/MPC8280
+	Rattler			MPC8248
 	ZPC1900			MPC8265
 
 Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
@@ -225,7 +226,11 @@ Denis Peter <d.peter@mpl.ch>
 	MIP405			PPC4xx
 	PIP405			PPC4xx
 
-Stefan Roese <stefan.roese@esd-electronics.com>
+Daniel Poirot <dan.poirot@windriver.com>
+	sbc8240			MPC8240
+	sbc405			PPC405GP
+
+Matthias Fuchs <matthias.fuchs@esd-electronics.com>
 
 	ADCIOP			IOP480 (PPC401)
 	APC405			PPC405GP
@@ -293,11 +298,17 @@ Jon Loeliger <jdl@freescale.com>
 
 	MPC8540ADS		MPC8540
 	MPC8560ADS		MPC8560
+	MPC8541CDS		MPC8541
+	MPC8555CDS		MPC8555
 
 Dan Malek <dan@embeddededge.com>
 
 	STxGP3			MPC85xx
 
+Yusdi Santoso <yusdi_santoso@adaptec.com>
+
+	HIDDEN_DRAGON	MPC8241/MPC8245
+
 -------------------------------------------------------------------------
 
 Unknown / orphaned boards:
@@ -382,6 +393,10 @@ Rishi Bhattacharya <rishi@ti.com>
 
 	omap5912osk		ARM926EJS
 
+Richard Woodruff <r-woodruff2@ti.com>
+
+	omap2420h4		ARM1136EJS
+
 David M<>ller <d.mueller@elsoft.ch>
 
 	smdk2410		ARM920T
@@ -400,6 +415,12 @@ Andrea Scian <andrea.scian@dave-tech.it>
 
 	B2				ARM7TDMI (S3C44B0X)
 
+Greg Ungerer <greg.ungerer@opengear.com>
+
+	cm4008			ks8695p
+	cm4116			ks8695p
+	cm4148			ks8695p
+
 Alex Z<>pke <azu@sysgo.de>
 
 	lart			SA1100
@@ -477,7 +498,7 @@ Yasushi Shoji <yashi@atmark-techno.com>
 #	Board			CPU					#
 #########################################################################
 
-Stefan Roese <stefan.roese@esd-electronics.com>
+Matthias Fuchs <matthias.fuchs@esd-electronics.com>
 
 	TASREG			MCF5249
 

MAKEALL

@@ -26,7 +26,7 @@ LIST_5xx="	\
 
 LIST_5xxx="	\
 	icecube_5100	icecube_5200	EVAL5200	PM520		\
-	Total5100	Total5200	Total5200_Rev2	TQM5200_AA	\
+	Total5100	Total5200	Total5200_Rev2	TQM5200_auto	\
 "
 
 #########################################################################
@@ -86,9 +86,10 @@ LIST_8220="	\
 
 LIST_824x="	\
 	A3000		BMW		CPC45		CU824		\
-	debris		eXalion		MOUSSE		MUSENKI		\
-	MVBLUE		OXC		PN62		Sandpoint8240	\
-	Sandpoint8245	SL8245		utx8245		sbc8240	\
+	debris		eXalion		HIDDEN_DRAGON	MOUSSE		\
+	MUSENKI		MVBLUE		OXC		PN62		\
+	Sandpoint8240	Sandpoint8245	SL8245		utx8245		\
+	sbc8240	\
 "
 
 #########################################################################
@@ -96,12 +97,13 @@ LIST_824x="	\
 #########################################################################
 
 LIST_8260="	\
-	atc		cogent_mpc8260	CPU86		ep8260		\
-	gw8260		hymod		IPHASE4539	ISPAN		\
-	MPC8260ADS	MPC8266ADS	MPC8272ADS	PM826		\
-	PM828		ppmc8260	RPXsuper	rsdproto	\
-	sacsng		sbc8260		SCM		TQM8260_AC	\
-	TQM8260_AD	TQM8260_AE	ZPC1900				\
+	atc		cogent_mpc8260	CPU86		CPU87		\
+	ep8260		gw8260		hymod		IPHASE4539	\
+	ISPAN		MPC8260ADS	MPC8266ADS	MPC8272ADS	\
+	PM826		PM828		ppmc8260	Rattler8248	\
+	RPXsuper	rsdproto	sacsng		sbc8260		\
+	SCM		TQM8260_AC	TQM8260_AD	TQM8260_AE	\
+	ZPC1900								\
 "
 
 #########################################################################
@@ -110,7 +112,8 @@ LIST_8260="	\
 
 LIST_85xx="	\
 	MPC8540ADS	MPC8541CDS	MPC8555CDS	MPC8560ADS	\
-	sbc8540		sbc8560		stxgp3				\
+	PM854		sbc8540		sbc8560		stxgp3		\
+	TQM8540								\
 "
 
 #########################################################################
@@ -128,7 +131,7 @@ LIST_7xx="	\
 
 LIST_ppc="${LIST_5xx}  ${LIST_5xxx}		\
 	  ${LIST_8xx}				\
-	  ${LIST_824x} ${LIST_8260} \
+	  ${LIST_8220} ${LIST_824x} ${LIST_8260} \
 	  ${LIST_85xx}				\
 	  ${LIST_4xx}				\
 	  ${LIST_74xx} ${LIST_7xx}"
@@ -154,23 +157,32 @@ LIST_ARM9="	\
 	lpd7a400	mx1ads		mx1fs2		omap1510inn	\
 	omap1610h2	omap1610inn	omap730p2	scb9328		\
 	smdk2400	smdk2410	trab		VCMA9		\
-	versatile							\
+	versatile	voiceblue					\
 "
 
+#########################################################################
+## ARM11 Systems
+#########################################################################
+LIST_ARM11="omap2420h4"
+
 #########################################################################
 ## Xscale Systems
 #########################################################################
 
 LIST_pxa="	\
-	cerf250		cradle		csb226		innokom		\
-	lubbock		wepep250	xaeniax		xm250		\
-	xsengine							\
+	adsvix		cerf250		cradle		csb226		\
+	innokom		lubbock		wepep250	xaeniax		\
+	xm250		xsengine							\
 "
 
 LIST_ixp="ixdp425"
 
 
-LIST_arm="${LIST_SA} ${LIST_ARM7} ${LIST_ARM9} ${LIST_pxa} ${LIST_ixp}"
+LIST_arm="	\
+	${LIST_SA}							\
+	${LIST_ARM7} ${LIST_ARM9} ${LIST_ARM11}				\
+	${LIST_pxa} ${LIST_ixp}						\
+"
 
 #########################################################################
 ## MIPS Systems
@@ -180,9 +192,9 @@ LIST_mips4kc="incaip"
 
 LIST_mips5kc="purple"
 
-LIST_au1x00="dbau1000 dbau1100 dbau1500"
+LIST_au1xx0="dbau1000 dbau1100 dbau1500 dbau1550 dbau1550_el"
 
-LIST_mips="${LIST_mips4kc} ${LIST_mips5kc} ${LIST_au1x00}"
+LIST_mips="${LIST_mips4kc} ${LIST_mips5kc} ${LIST_au1xx0}"
 
 #########################################################################
 ## i386 Systems
@@ -238,7 +250,7 @@ for arg in $@
 do
 	case "$arg" in
 	ppc|5xx|5xxx|8xx|8220|824x|8260|85xx|4xx|7xx|74xx| \
-	arm|SA|ARM7|ARM9|pxa|ixp| \
+	arm|SA|ARM7|ARM9|ARM11|pxa|ixp| \
 	microblaze| \
 	mips| \
 	nios|nios2| \

Makefile

@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000-2004
+# (C) Copyright 2000-2005
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -121,7 +121,7 @@ LIBS += common/libcommon.a
 .PHONY : $(LIBS)
 
 # Add GCC lib
-PLATFORM_LIBS += --no-warn-mismatch -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
+PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
 
 
 # The "tools" are needed early, so put this first
@@ -139,6 +139,9 @@ ALL = u-boot.srec u-boot.bin System.map
 
 all:		$(ALL)
 
+u-boot.hex:	u-boot
+		$(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@
+
 u-boot.srec:	u-boot
 		$(OBJCOPY) ${OBJCFLAGS} -O srec $< $@
 
@@ -158,7 +161,7 @@ u-boot.dis:	u-boot
 u-boot:		depend $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT)
 		UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed  -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
 		$(LD) $(LDFLAGS) $$UNDEF_SYM $(OBJS) \
-			--start-group $(LIBS) $(PLATFORM_LIBS) --end-group \
+			--start-group $(LIBS) --end-group $(PLATFORM_LIBS) \
 			-Map u-boot.map -o u-boot
 
 $(LIBS):
@@ -212,6 +215,9 @@ unconfig:
 ## MPC5xx Systems
 #########################################################################
 
+canmb_config:	unconfig
+	@./mkconfig -a canmb ppc mpc5xxx canmb
+
 cmi_mpc5xx_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc5xx cmi
 
@@ -221,6 +227,10 @@ PATI_config:		unconfig
 #########################################################################
 ## MPC5xxx Systems
 #########################################################################
+
+hmi1001_config:         unconfig
+	@./mkconfig hmi1001 ppc mpc5xxx hmi1001
+
 Lite5200_config				\
 Lite5200_LOWBOOT_config			\
 Lite5200_LOWBOOT08_config		\
@@ -833,6 +843,9 @@ PPChameleonEVB_HI_33_config:	unconfig
 		}
 	@./mkconfig -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave
 
+sbc405_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx sbc405
+
 VOH405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx voh405 esd
 
@@ -858,6 +871,9 @@ XPEDITE1K_config:	unconfig
 Alaska8220_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8220 alaska
 
+sorcery_config:		unconfig
+	@./mkconfig $(@:_config=) ppc mpc8220 sorcery
+
 Yukon8220_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8220 yukon
 
@@ -894,6 +910,9 @@ debris_config: unconfig
 eXalion_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x eXalion
 
+HIDDEN_DRAGON_config: unconfig
+	@./mkconfig $(@:_config=) ppc mpc824x hidden_dragon
+
 MOUSSE_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x mousse
 
@@ -924,6 +943,9 @@ SL8245_config: unconfig
 utx8245_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc824x utx8245
 
+cobra5272_config :		unconfig
+	@./mkconfig $(@:_config=) m68k mcf52x2 cobra5272
+
 #########################################################################
 ## MPC8260 Systems
 #########################################################################
@@ -947,6 +969,19 @@ CPU86_ROMBOOT_config: unconfig
 	fi; \
 	echo "export CONFIG_BOOT_ROM" >> config.mk;
 
+CPU87_config	\
+CPU87_ROMBOOT_config: unconfig
+	@./mkconfig $(call xtract_82xx,$@) ppc mpc8260 cpu87
+	@cd ./include ;				\
+	if [ "$(findstring _ROMBOOT_,$@)" ] ; then \
+		echo "CONFIG_BOOT_ROM = y" >> config.mk ; \
+		echo "... booting from 8-bit flash" ; \
+	else \
+		echo "CONFIG_BOOT_ROM = n" >> config.mk ; \
+		echo "... booting from 64-bit flash" ; \
+	fi; \
+	echo "export CONFIG_BOOT_ROM" >> config.mk;
+
 ep8260_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 ep8260
 
@@ -956,6 +991,9 @@ gw8260_config:	unconfig
 hymod_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 hymod
 
+IDS8247_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc8260 ids8247
+
 IPHASE4539_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 iphase4539
 
@@ -967,13 +1005,21 @@ ISPAN_REVB_config:	unconfig
 	@./mkconfig -a ISPAN ppc mpc8260 ispan
 
 MPC8260ADS_config	\
+MPC8260ADS_lowboot_config	\
 MPC8260ADS_33MHz_config	\
+MPC8260ADS_33MHz_lowboot_config	\
 MPC8260ADS_40MHz_config	\
+MPC8260ADS_40MHz_lowboot_config	\
 MPC8272ADS_config	\
+MPC8272ADS_lowboot_config	\
 PQ2FADS_config		\
+PQ2FADS_lowboot_config		\
 PQ2FADS-VR_config	\
+PQ2FADS-VR_lowboot_config	\
 PQ2FADS-ZU_config	\
+PQ2FADS-ZU_lowboot_config	\
 PQ2FADS-ZU_66MHz_config	\
+PQ2FADS-ZU_66MHz_lowboot_config	\
 	:		unconfig
 	$(if $(findstring PQ2FADS,$@), \
 	@echo "#define CONFIG_ADSTYPE CFG_PQ2FADS" > include/config.h, \
@@ -982,6 +1028,10 @@ PQ2FADS-ZU_66MHz_config	\
 	@echo "#define CONFIG_8260_CLKIN" $(subst MHz,,$(word 2,$(subst _, ,$@)))"000000" >> include/config.h, \
 	$(if $(findstring VR,$@), \
 	@echo "#define CONFIG_8260_CLKIN 66000000" >> include/config.h))
+	@[ -z "$(findstring lowboot_,$@)" ] || \
+		{ echo "TEXT_BASE = 0xFF800000" >board/mpc8260ads/config.tmp ; \
+		  echo "... with lowboot configuration" ; \
+		}
 	@./mkconfig -a MPC8260ADS ppc mpc8260 mpc8260ads
 
 MPC8266ADS_config:	unconfig
@@ -1041,6 +1091,12 @@ PM828_ROMBOOT_PCI_config:	unconfig
 ppmc8260_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 ppmc8260
 
+Rattler8248_config	\
+Rattler_config:		unconfig
+	$(if $(findstring 8248,$@), \
+	@echo "#define CONFIG_MPC8248" > include/config.h)
+	@./mkconfig -a Rattler ppc mpc8260 rattler
+
 RPXsuper_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 rpxsuper
 
@@ -1100,6 +1156,11 @@ TQM8265_AA_config:  unconfig
 	fi
 	@./mkconfig -a TQM8260 ppc mpc8260 tqm8260
 
+VoVPN-GW_66MHz_config	\
+VoVPN-GW_100MHz_config:		unconfig
+	@echo "#define CONFIG_CLKIN_$(word 2,$(subst _, ,$@))" > include/config.h
+	@./mkconfig -a VoVPN-GW ppc mpc8260 vovpn-gw funkwerk
+
 ZPC1900_config: unconfig
 	@./mkconfig $(@:_config=) ppc mpc8260 zpc1900
 
@@ -1135,6 +1196,9 @@ MPC8541CDS_config:	unconfig
 MPC8555CDS_config:	unconfig
 	@./mkconfig $(@:_config=) ppc mpc85xx mpc8555cds cds
 
+PM854_config:	unconfig
+	@./mkconfig $(@:_config=) ppc mpc85xx pm854
+
 sbc8540_config \
 sbc8540_33_config \
 sbc8540_66_config:	unconfig
@@ -1162,6 +1226,12 @@ sbc8560_66_config:      unconfig
 stxgp3_config:		unconfig
 	@./mkconfig $(@:_config=) ppc mpc85xx stxgp3
 
+TQM8540_config:      unconfig
+	@./mkconfig $(@:_config=) ppc mpc85xx tqm8540
+
+TQM8560_config:      unconfig
+	@./mkconfig $(@:_config=) ppc mpc85xx tqm8560
+
 #########################################################################
 ## 74xx/7xx Systems
 #########################################################################
@@ -1230,6 +1300,12 @@ xtract_omap1610xxx = $(subst _cs0boot,,$(subst _cs3boot,,$(subst _cs_autoboot,,$
 
 xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))
 
+at91rm9200dk_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t at91rm9200dk NULL at91rm9200
+
+cmc_pu2_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200
+
 integratorap_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm926ejs integratorap
 
@@ -1327,6 +1403,25 @@ VCMA9_config	:	unconfig
 versatile_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm926ejs versatile
 
+voiceblue_smallflash_config	\
+voiceblue_config:	unconfig
+	@if [ "$(findstring _smallflash_,$@)" ] ; then \
+		echo "... boot from lower flash bank" ; \
+		echo "#define VOICEBLUE_SMALL_FLASH" >>include/config.h ; \
+		echo "VOICEBLUE_SMALL_FLASH=y" >board/voiceblue/config.tmp ; \
+	else \
+		echo "... boot from upper flash bank" ; \
+		>include/config.h ; \
+		echo "VOICEBLUE_SMALL_FLASH=n" >board/voiceblue/config.tmp ; \
+	fi
+	@./mkconfig -a voiceblue arm arm925t voiceblue
+
+cm4008_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t cm4008 NULL ks8695
+
+cm41xx_config	:	unconfig
+	@./mkconfig $(@:_config=) arm arm920t cm41xx NULL ks8695
+
 #########################################################################
 ## S3C44B0 Systems
 #########################################################################
@@ -1350,20 +1445,13 @@ modnet50_config :	unconfig
 evb4510_config :	unconfig
 	@./mkconfig $(@:_config=) arm arm720t evb4510
 
-#########################################################################
-## AT91RM9200 Systems
-#########################################################################
-
-at91rm9200dk_config	:	unconfig
-	@./mkconfig $(@:_config=) arm at91rm9200 at91rm9200dk
-
-cmc_pu2_config	:	unconfig
-	@./mkconfig $(@:_config=) arm at91rm9200 cmc_pu2
-
 #########################################################################
 ## XScale Systems
 #########################################################################
 
+adsvix_config	:	unconfig
+	@./mkconfig $(@:_config=) arm pxa adsvix
+
 cerf250_config :	unconfig
 	@./mkconfig $(@:_config=) arm pxa cerf250
 
@@ -1397,6 +1485,12 @@ xm250_config	:	unconfig
 xsengine_config :	unconfig
 	@./mkconfig $(@:_config=) arm pxa xsengine
 
+#########################################################################
+## ARM1136 Systems
+#########################################################################
+omap2420h4_config :    unconfig
+	@./mkconfig $(@:_config=) arm arm1136 omap2420h4
+
 #========================================================================
 # i386
 #========================================================================
@@ -1461,6 +1555,16 @@ dbau1500_config		: 	unconfig
 	@echo "#define CONFIG_DBAU1500 1" >>include/config.h
 	@./mkconfig -a dbau1x00 mips mips dbau1x00
 
+dbau1550_config		:	unconfig
+	@ >include/config.h
+	@echo "#define CONFIG_DBAU1550 1" >>include/config.h
+	@./mkconfig -a dbau1x00 mips mips dbau1x00
+
+dbau1550_el_config	:	unconfig
+	@ >include/config.h
+	@echo "#define CONFIG_DBAU1550 1" >>include/config.h
+	@./mkconfig -a dbau1x00 mips mips dbau1x00 "" little
+
 #########################################################################
 ## MIPS64 5Kc
 #########################################################################
@@ -1565,7 +1669,8 @@ clean:
 		| xargs rm -f
 	rm -f examples/hello_world examples/timer \
 	      examples/eepro100_eeprom examples/sched \
-	      examples/mem_to_mem_idma2intr examples/82559_eeprom
+	      examples/mem_to_mem_idma2intr examples/82559_eeprom \
+	      examples/test_burst
 	rm -f tools/img2srec tools/mkimage tools/envcrc tools/gen_eth_addr
 	rm -f tools/mpc86x_clk tools/ncb
 	rm -f tools/easylogo/easylogo tools/bmp_logo
@@ -1581,7 +1686,7 @@ clobber:	clean
 		| xargs -0 rm -f
 	rm -f $(OBJS) *.bak tags TAGS
 	rm -fr *.*~
-	rm -f u-boot u-boot.map $(ALL)
+	rm -f u-boot u-boot.map u-boot.hex $(ALL)
 	rm -f tools/crc32.c tools/environment.c tools/env/crc32.c
 	rm -f tools/inca-swap-bytes cpu/mpc824x/bedbug_603e.c
 	rm -f include/asm/proc include/asm/arch include/asm

README

@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000 - 2004
+# (C) Copyright 2000 - 2005
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -126,11 +126,12 @@ Directory Hierarchy:
   - 74xx_7xx	Files specific to Freescale MPC74xx and 7xx CPUs
   - arm720t	Files specific to ARM 720 CPUs
   - arm920t	Files specific to ARM 920 CPUs
+    - at91rm9200 Files specific to Atmel AT91RM9200 CPU
     - imx	Files specific to Freescale MC9328 i.MX CPUs
     - s3c24x0	Files specific to Samsung S3C24X0 CPUs
   - arm925t	Files specific to ARM 925 CPUs
   - arm926ejs	Files specific to ARM 926 CPUs
-  - at91rm9200	Files specific to Atmel AT91RM9200 CPUs
+  - arm1136	Files specific to ARM 1136 CPUs
   - i386	Files specific to i386 CPUs
   - ixp		Files specific to Intel XScale IXP CPUs
   - mcf52x2	Files specific to Freescale ColdFire MCF52x2 CPUs
@@ -305,9 +306,9 @@ The following options need to be configured:
 		CONFIG_EP7312,		CONFIG_H2_OMAP1610,	CONFIG_HHP_CRADLE,
 		CONFIG_IMPA7,		CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610,
 		CONFIG_LART,		CONFIG_LPD7A400		CONFIG_LUBBOCK,
-		CONFIG_OSK_OMAP5912,		CONFIG_SHANNON,		CONFIG_P2_OMAP730,
-		CONFIG_SMDK2400,		CONFIG_SMDK2410,	CONFIG_TRAB,
-		CONFIG_VCMA9
+		CONFIG_OSK_OMAP5912,	CONFIG_OMAP2420H4,	CONFIG_SHANNON,
+		CONFIG_P2_OMAP730,	CONFIG_SMDK2400,	CONFIG_SMDK2410,
+		CONFIG_TRAB,		CONFIG_VCMA9
 
 		MicroBlaze based boards:
 		------------------------
@@ -626,6 +627,7 @@ The following options need to be configured:
 		CFG_CMD_SAVES	* save S record dump
 		CFG_CMD_SCSI	* SCSI Support
 		CFG_CMD_SDRAM	* print SDRAM configuration information
+				  (requires CFG_CMD_I2C)
 		CFG_CMD_SETGETDCR Support for DCR Register access (4xx only)
 		CFG_CMD_SPI	* SPI serial bus support
 		CFG_CMD_USB	* USB support
@@ -2127,6 +2129,19 @@ Low Level (hardware related) configuration options:
 		This only takes effect if the memory commands are activated
 		globally (CFG_CMD_MEM).
 
+- CONFIG_SKIP_LOWLEVEL_INIT
+- CONFIG_SKIP_RELOCATE_UBOOT
+
+		[ARM only] If these variables are defined, then
+		certain low level initializations (like setting up
+		the memory controller) are omitted and/or U-Boot does
+		not relocate itself into RAM.
+		Normally these variables MUST NOT be defined. The
+		only exception is when U-Boot is loaded (to RAM) by
+		some other boot loader or by a debugger which
+		performs these intializations itself.
+
+
 Building the Software:
 ======================
 
@@ -2177,7 +2192,7 @@ configurations; the following names are supported:
 	FADS850SAR_config	omap1610h2_config	TQM850L_config
 	FADS860T_config		omap1610inn_config	TQM855L_config
 	FPS850L_config		omap5912osk_config	TQM860L_config
-							WALNUT405_config
+				omap2420h4_config	WALNUT405_config
 							Yukon8220_config
 							ZPC1900_config
 
@@ -3066,8 +3081,7 @@ Booting assumes that (the first part of) the image booted is a
 stage-2 loader which in turn loads and then invokes the kernel
 proper. Loader sources will eventually appear in the NetBSD source
 tree (probably in sys/arc/mpc8xx/stand/u-boot_stage2/); in the
-meantime, send mail to bruno@exet-ag.de and/or wd@denx.de for
-details.
+meantime, see ftp://ftp.denx.de/pub/u-boot/ppcboot_stage2.tar.gz
 
 
 Implementation Internals:
@@ -3367,6 +3381,7 @@ Since the number of patches for U-Boot is growing, we need to
 establish some rules. Submissions which do not conform to these rules
 may be rejected, even when they contain important and valuable stuff.
 
+Patches shall be sent to the u-boot-users mailing list.
 
 When you send a patch, please include the following information with
 it:
@@ -3424,3 +3439,6 @@ Notes:
   (using #ifdef), and the resulting code with the new feature
   disabled must not need more memory than the old code without your
   modification.
+
+* Remember that there is a size limit of 40 kB per message on the
+  u-boot-users mailing list. Compression may help.

board/Marvell/common/ecctest.c

@@ -1,5 +1,3 @@
-indent: Standard input:49: Warning:old style assignment ambiguity in "=*".  Assuming "= *"
-
 /*
  * (C) Copyright 2001
  *

board/RPXlite_dw/README

@@ -2,11 +2,11 @@
 After following the step of Yoo. Jonghoon and Wolfgang Denk,
 I ported u-boot on RPXlite DW version board: RPXlite_DW or LITE_DW.
 
-There are three differences between the Yoo-ported RPXlite and the RPXlite_DW.
+There are at least three differences between the Yoo-ported RPXlite and the RPXlite_DW.
 
-Board(in U-BOOT)	version(in EmbeddedPlanet)	CPU	SDRAM	FLASH
+Board(in U-Boot)	version(in EmbeddedPlanet)	CPU	SDRAM	FLASH
 RPXlite				RPXlite CW		850	16MB	4MB
-RPXlite_DW			RPXlite DW		823e	64MB	16MB
+RPXlite_DW		RPXlite DW(EP 823 H1 DW)	823e	64MB	16MB
 
 This fireware is specially coded for EmbeddedPlanet Co. Software Development
 Platform(RPXlite DW),which has a NEC NL6448BC20-08 LCD panel.
@@ -17,6 +17,7 @@ It has the following three features:
 The default setting is 48MHz.To get a 64MHz u-boot,just add
 '64' in make command,like
 
+make distclean
 make RPXlite_DW_64_config
 make all
 
@@ -28,19 +29,21 @@ didn't use EEPROM for ENV is that PlanetCore V2.0 use EEPROM as environment para
 home.Because of the possibility of using two firewares on this board,I didn't
 'disturb' EEPROM.To get NVRAM support,you may use the following build command:
 
+make distclean
 make RPXlite_DW_NVRAM_config
 make all
 
 3. LCD panel support
 
-To support the Platform better,I added LCD panel(NL6448BC20-08) function.But bewear of
-the fact that once you build this support and program it to FLASH,you should make sure
-you put workable kernel and ramdisk at the right place in FLASH or through NFS.
-Otherwise, you must erase this fireware manually via BDI2000 or ICE tools.So this
-function is used for deployment and demo only.Pls look before you leap.
+To support the Platform better,I added LCD panel(NL6448BC20-08) function.
+For the convenience of debug, CONFIG_PERBOOT was supported. So you just
+perss ENTER if you want to get a serial console in boot downcounting.
+Then you can switch to LCD and serial console freely just typing
+'run lcd' or 'run ser'. They are only vaild when CONFIG_LCD was enabled.
 
 To get a LCD support u-boot,you can do the following:
 
+make distclean
 make RPXlite_DW_LCD_config
 make all
 
@@ -68,7 +71,7 @@ make RPXlite_DW_64_LCD_config
 
 The boot process by "make RPXlite_DW_config" could be:
 
-U-Boot 1.1.1 (Jun  8 2004 - 11:16:30)
+U-Boot 1.1.2 (Aug 29 2004 - 15:11:27)
 
 CPU:   PPC823EZTnnB2 at 48 MHz: 16 kB I-Cache 8 kB D-Cache
 Board: RPXlite_DW
@@ -84,6 +87,68 @@ u-boot>
 
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
+A word on the U-Boot enviroment variable setting and usage :
+
+In the beginning, you could just need very simple defult environment variable setting,
+like[include/configs/RPXlite.h] :
+
+#define CONFIG_BOOTCOMMAND                                                      \
+	"bootp; "                                                               \
+	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "     \
+	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; "   \
+	"bootm"
+
+This is enough for kernel NFS test. But as debug process goes on, you would expect
+to save some time on environment variable setting and u-boot/kernel updating.
+So the default environment variable setting would become more complicated. Just like
+the one I did in include/configs/RPXlite_DW.h.
+
+Two u-boot commands, ku and uu, should be careful to use. They were designed to update
+kernel and u-boot image file respectively. You must tftp your image to default address
+'100000' and then use them correctly. Yeah, you can create your own command to do this
+job. :-) The example u-boot image updating process could be :
+
+u-boot>t 100000 RPXlite_DW_LCD.bin
+Using SCC ETHERNET device
+TFTP from server 172.16.115.6; our IP address is 172.16.115.7
+Filename 'RPXlite_DW_LCD.bin'.
+Load address: 0x100000
+Loading: #############################
+done
+Bytes transferred = 144700 (2353c hex)
+u-boot>run uu
+Un-Protect Flash Sectors 0-4 in Bank # 1
+Erase Flash Sectors 0-4 in Bank # 1
+.... done
+Copy to Flash... done
+ff000000: 27051956 552d426f 6f742031 2e312e32    '..VU-Boot 1.1.2
+ff000010: 20284175 67203239 20323030 34202d20     (Aug 29 2004 -
+ff000020: 31353a32 303a3238 29000000 00000000    15:20:28).......
+ff000030: 00000000 00000000 00000000 00000000    ................
+ff000040: 00000000 00000000 00000000 00000000    ................
+ff000050: 00000000 00000000 00000000 00000000    ................
+ff000060: 00000000 00000000 00000000 00000000    ................
+ff000070: 00000000 00000000 00000000 00000000    ................
+ff000080: 00000000 00000000 00000000 00000000    ................
+ff000090: 00000000 00000000 00000000 00000000    ................
+ff0000a0: 00000000 00000000 00000000 00000000    ................
+ff0000b0: 00000000 00000000 00000000 00000000    ................
+ff0000c0: 00000000 00000000 00000000 00000000    ................
+ff0000d0: 00000000 00000000 00000000 00000000    ................
+ff0000e0: 00000000 00000000 00000000 00000000    ................
+ff0000f0: 00000000 00000000 00000000 00000000    ................
+u-boot updating finished
+u-boot>
+
+Also for environment updating, 'run eu' could let you erase OLD default environment variable
+and then use the working u-boot environment setting.
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Finally, if you want to keep the serial port to possible debug on spot for deployment, you
+just need to enable 'DEPLOYMENT' in RPXlite_DW.h as 'DEBUG' does. Only the special string
+defined by CONFIG_AUTOBOOT_STOP_STR like 'st' can stop the autoboot.
+
 I'd like to extend my heartfelt gratitute to kind people for helping me work it out.
 I would particually thank Wolfgang Denk for his nice help.
 
@@ -93,4 +158,4 @@ Sam Song, samsongshu@yahoo.com.cn
 Institute of Electrical Machinery and Controls
 Shanghai University
 
-June 8,2004
+Oct. 11, 2004

board/adsvix/Makefile

@@ -0,0 +1,48 @@
+
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= adsvix.o pcmcia.o
+SOBJS	:= lowlevel_init.o pxavoltage.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/adsvix/adsvix.c

@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* memory and cpu-speed are setup before relocation */
+	/* so we do _nothing_ here */
+
+	/* arch number of ADSVIX-Board */
+	gd->bd->bi_arch_number = 620;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0xa000003c;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	setenv("stdout", "serial");
+	setenv("stderr", "serial");
+	return 0;
+}
+
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
+	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
+
+	return 0;
+}

board/adsvix/config.mk

@@ -0,0 +1 @@
+TEXT_BASE = 0xa1700000

board/adsvix/lowlevel_init.S

@@ -0,0 +1,466 @@
+/*
+ * This was originally from the Lubbock u-boot port.
+ *
+ * Most of this taken from Redboot hal_platform_setup.h with cleanup
+ *
+ * NOTE: I haven't clean this up considerably, just enough to get it
+ * running. See hal_platform_setup.h for the source. See
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
+ * much cleaner.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/pxa-regs.h>
+
+/* wait for coprocessor write complete */
+   .macro CPWAIT reg
+   mrc	p15,0,\reg,c2,c0,0
+   mov	\reg,\reg
+   sub	pc,pc,#4
+   .endm
+
+
+/*
+ *	Memory setup
+ */
+
+.globl lowlevel_init
+lowlevel_init:
+
+	/* Set up GPIO pins first ----------------------------------------- */
+
+	ldr		r0,	=GPSR0
+	ldr		r1,	=CFG_GPSR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPSR1
+	ldr		r1,	=CFG_GPSR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPSR2
+	ldr		r1,	=CFG_GPSR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPSR3
+	ldr		r1,	=CFG_GPSR3_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR0
+	ldr		r1,	=CFG_GPCR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR1
+	ldr		r1,	=CFG_GPCR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR2
+	ldr		r1,	=CFG_GPCR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPCR3
+	ldr		r1,	=CFG_GPCR3_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR0
+	ldr		r1,	=CFG_GPDR0_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR1
+	ldr		r1,	=CFG_GPDR1_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR2
+	ldr		r1,	=CFG_GPDR2_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GPDR3
+	ldr		r1,	=CFG_GPDR3_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR0_L
+	ldr		r1,	=CFG_GAFR0_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR0_U
+	ldr		r1,	=CFG_GAFR0_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR1_L
+	ldr		r1,	=CFG_GAFR1_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR1_U
+	ldr		r1,	=CFG_GAFR1_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR2_L
+	ldr		r1,	=CFG_GAFR2_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR2_U
+	ldr		r1,	=CFG_GAFR2_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR3_L
+	ldr		r1,	=CFG_GAFR3_L_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=GAFR3_U
+	ldr		r1,	=CFG_GAFR3_U_VAL
+	str		r1,   [r0]
+
+	ldr		r0,	=PSSR		/* enable GPIO pins */
+	ldr		r1,	=CFG_PSSR_VAL
+	str		r1,   [r0]
+
+	/* ---------------------------------------------------------------- */
+	/* Enable memory interface					    */
+	/*								    */
+	/* The sequence below is based on the recommended init steps	    */
+	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
+	/* Chapter 10.							    */
+	/* ---------------------------------------------------------------- */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 1: Wait for at least 200 microsedonds to allow internal	    */
+	/*	   clocks to settle. Only necessary after hard reset...	    */
+	/*	   FIXME: can be optimized later			    */
+	/* ---------------------------------------------------------------- */
+
+	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
+	mov r2, #0
+	str r2, [r3]
+	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
+					/* so 0x300 should be plenty	    */
+1:
+	ldr r2, [r3]
+	cmp r4, r2
+	bgt 1b
+
+mem_init:
+
+	ldr	r1,  =MEMC_BASE		/* get memory controller base addr. */
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2a: Initialize Asynchronous static memory controller	    */
+	/* ---------------------------------------------------------------- */
+
+	/* MSC registers: timing, bus width, mem type			    */
+
+	/* MSC0: nCS(0,1)						    */
+	ldr	r2,   =CFG_MSC0_VAL
+	str	r2,   [r1, #MSC0_OFFSET]
+	ldr	r2,   [r1, #MSC0_OFFSET]	/* read back to ensure	    */
+						/* that data latches	    */
+	/* MSC1: nCS(2,3)						    */
+	ldr	r2,  =CFG_MSC1_VAL
+	str	r2,  [r1, #MSC1_OFFSET]
+	ldr	r2,  [r1, #MSC1_OFFSET]
+
+	/* MSC2: nCS(4,5)						    */
+	ldr	r2,  =CFG_MSC2_VAL
+	str	r2,  [r1, #MSC2_OFFSET]
+	ldr	r2,  [r1, #MSC2_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2b: Initialize Card Interface				    */
+	/* ---------------------------------------------------------------- */
+
+	/* MECR: Memory Expansion Card Register				    */
+	ldr	r2,  =CFG_MECR_VAL
+	str	r2,  [r1, #MECR_OFFSET]
+	ldr	r2,	[r1, #MECR_OFFSET]
+
+	/* MCMEM0: Card Interface slot 0 timing				    */
+	ldr	r2,  =CFG_MCMEM0_VAL
+	str	r2,  [r1, #MCMEM0_OFFSET]
+	ldr	r2,	[r1, #MCMEM0_OFFSET]
+
+	/* MCMEM1: Card Interface slot 1 timing				    */
+	ldr	r2,  =CFG_MCMEM1_VAL
+	str	r2,  [r1, #MCMEM1_OFFSET]
+	ldr	r2,	[r1, #MCMEM1_OFFSET]
+
+	/* MCATT0: Card Interface Attribute Space Timing, slot 0	    */
+	ldr	r2,  =CFG_MCATT0_VAL
+	str	r2,  [r1, #MCATT0_OFFSET]
+	ldr	r2,	[r1, #MCATT0_OFFSET]
+
+	/* MCATT1: Card Interface Attribute Space Timing, slot 1	    */
+	ldr	r2,  =CFG_MCATT1_VAL
+	str	r2,  [r1, #MCATT1_OFFSET]
+	ldr	r2,	[r1, #MCATT1_OFFSET]
+
+	/* MCIO0: Card Interface I/O Space Timing, slot 0		    */
+	ldr	r2,  =CFG_MCIO0_VAL
+	str	r2,  [r1, #MCIO0_OFFSET]
+	ldr	r2,	[r1, #MCIO0_OFFSET]
+
+	/* MCIO1: Card Interface I/O Space Timing, slot 1		    */
+	ldr	r2,  =CFG_MCIO1_VAL
+	str	r2,  [r1, #MCIO1_OFFSET]
+	ldr	r2,	[r1, #MCIO1_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2c: Write FLYCNFG  FIXME: what's that???		    */
+	/* ---------------------------------------------------------------- */
+	ldr	r2,  =CFG_FLYCNFG_VAL
+	str	r2,  [r1, #FLYCNFG_OFFSET]
+	str	r2,	[r1, #FLYCNFG_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)		    */
+	/* ---------------------------------------------------------------- */
+
+	/* Before accessing MDREFR we need a valid DRI field, so we set	    */
+	/* this to power on defaults + DRI field.			    */
+
+	ldr	r4,	[r1, #MDREFR_OFFSET]
+	ldr	r2,	=0xFFF
+	bic	r4,	r4, r2
+
+	ldr	r3,	=CFG_MDREFR_VAL
+	and	r3,	r3,  r2
+
+	orr	r4,	r4, r3
+	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR	    */
+
+	orr	r4,  r4, #MDREFR_K0RUN
+	orr	r4,  r4, #MDREFR_K0DB4
+	orr	r4,  r4, #MDREFR_K0FREE
+	orr	r4,  r4, #MDREFR_K0DB2
+	orr	r4,  r4, #MDREFR_K1DB2
+	bic	r4,  r4, #MDREFR_K1FREE
+	bic	r4,  r4, #MDREFR_K2FREE
+
+	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR	    */
+	ldr	r4,  [r1, #MDREFR_OFFSET]
+
+	/* Note: preserve the mdrefr value in r4			    */
+
+
+	/* ---------------------------------------------------------------- */
+	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
+	/* ---------------------------------------------------------------- */
+
+	/* Initialize SXCNFG register. Assert the enable bits		    */
+
+	/* Write SXMRS to cause an MRS command to all enabled banks of	    */
+	/* synchronous static memory. Note that SXLCR need not be written   */
+	/* at this time.						    */
+
+	ldr	r2,  =CFG_SXCNFG_VAL
+	str	r2,  [r1, #SXCNFG_OFFSET]
+
+	/* ---------------------------------------------------------------- */
+	/* Step 4: Initialize SDRAM					    */
+	/* ---------------------------------------------------------------- */
+
+	bic	r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE)
+
+	orr	r4, r4, #MDREFR_K1RUN
+	bic	r4, r4, #MDREFR_K2DB2
+	str	r4, [r1, #MDREFR_OFFSET]
+	ldr	r4, [r1, #MDREFR_OFFSET]
+
+	bic	r4, r4, #MDREFR_SLFRSH
+	str	r4, [r1, #MDREFR_OFFSET]
+	ldr	r4, [r1, #MDREFR_OFFSET]
+
+	orr	r4, r4, #MDREFR_E1PIN
+	str	r4, [r1, #MDREFR_OFFSET]
+	ldr	r4, [r1, #MDREFR_OFFSET]
+
+	nop
+	nop
+
+
+	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
+	/*	    configure but not enable each SDRAM partition pair.	    */
+
+	ldr	r4,	=CFG_MDCNFG_VAL
+	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
+	bic	r4,	r4,	#(MDCNFG_DE2|MDCNFG_DE3)
+
+	str	r4,	[r1, #MDCNFG_OFFSET]	/* write back MDCNFG	    */
+	ldr	r4,	[r1, #MDCNFG_OFFSET]
+
+
+	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,	    */
+	/*	    100..200 <20>sec.					    */
+
+	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
+	mov r2, #0
+	str r2, [r3]
+	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
+					/* so 0x300 should be plenty	    */
+1:
+	    ldr r2, [r3]
+	    cmp r4, r2
+	    bgt 1b
+
+
+	/* Step 4f: Trigger a number (usually 8) refresh cycles by	    */
+	/*	    attempting non-burst read or write accesses to disabled */
+	/*	    SDRAM, as commonly specified in the power up sequence   */
+	/*	    documented in SDRAM data sheets. The address(es) used   */
+	/*	    for this purpose must not be cacheable.		    */
+
+	ldr	r3,	=CFG_DRAM_BASE
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+	str	r2,	[r3]
+
+
+	/* Step 4g: Write MDCNFG with enable bits asserted		    */
+	/*	    (MDCNFG:DEx set to 1).				    */
+
+	ldr	r3,	[r1, #MDCNFG_OFFSET]
+	mov	r4, r3
+	orr	r3,	r3,	#MDCNFG_DE0
+	str	r3,	[r1, #MDCNFG_OFFSET]
+	mov	r0, r3
+
+	/* Step 4h: Write MDMRS.					    */
+
+	ldr	r2,  =CFG_MDMRS_VAL
+	str	r2,  [r1, #MDMRS_OFFSET]
+
+	/* enable APD */
+	ldr	r3,  [r1, #MDREFR_OFFSET]
+	orr	r3,  r3,  #MDREFR_APD
+	str	r3,  [r1, #MDREFR_OFFSET]
+
+	/* We are finished with Intel's memory controller initialisation    */
+
+setvoltage:
+
+	mov	r10,	lr
+	bl	initPXAvoltage	/* In case the board is rebooting with a    */
+	mov	lr,	r10	/* low voltage raise it up to a good one.   */
+
+wakeup:
+	/* Are we waking from sleep? */
+	ldr	r0,	=RCSR
+	ldr	r1,	[r0]
+	and	r1,	r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
+	str	r1,	[r0]
+	teq	r1,	#RCSR_SMR
+
+	bne	initirqs
+
+	ldr	r0,	=PSSR
+	mov	r1,	#PSSR_PH
+	str	r1,	[r0]
+
+	/* if so, resume at PSPR */
+	ldr	r0,	=PSPR
+	ldr	r1,	[r0]
+	mov	pc,	r1
+
+	/* ---------------------------------------------------------------- */
+	/* Disable (mask) all interrupts at interrupt controller	    */
+	/* ---------------------------------------------------------------- */
+
+initirqs:
+
+	mov	r1,  #0		/* clear int. level register (IRQ, not FIQ) */
+	ldr	r2,  =ICLR
+	str	r1,  [r2]
+
+	ldr	r2,  =ICMR	/* mask all interrupts at the controller    */
+	str	r1,  [r2]
+
+	/* ---------------------------------------------------------------- */
+	/* Clock initialisation						    */
+	/* ---------------------------------------------------------------- */
+
+initclks:
+
+	/* Disable the peripheral clocks, and set the core clock frequency  */
+
+	/* Turn Off on-chip peripheral clocks (except for memory)	    */
+	/* for re-configuration.					    */
+	ldr	r1,  =CKEN
+	ldr	r2,  =CFG_CKEN
+	str	r2,  [r1]
+
+	/* ... and write the core clock config register			    */
+	ldr	r2,  =CFG_CCCR
+	ldr	r1,  =CCCR
+	str	r2,  [r1]
+
+	/* Turn on turbo mode */
+	mrc	p14, 0, r2, c6, c0, 0
+	orr	r2, r2, #0xB		/* Turbo, Fast-Bus, Freq change**/
+	mcr	p14, 0, r2, c6, c0, 0
+
+	/* Re-write MDREFR */
+	ldr	r1, =MEMC_BASE
+	ldr	r2, [r1, #MDREFR_OFFSET]
+	str	r2, [r1, #MDREFR_OFFSET]
+#ifdef RTC
+	/* enable the 32Khz oscillator for RTC and PowerManager		    */
+	ldr	r1,  =OSCC
+	mov	r2,  #OSCC_OON
+	str	r2,  [r1]
+
+	/* NOTE:  spin here until OSCC.OOK get set, meaning the PLL	    */
+	/* has settled.							    */
+60:
+	ldr	r2, [r1]
+	ands	r2, r2, #1
+	beq	60b
+#else
+#error "RTC not defined"
+#endif
+
+	/* Interrupt init: Mask all interrupts				    */
+    ldr r0, =ICMR /* enable no sources */
+	mov r1, #0
+    str r1, [r0]
+	/* FIXME */
+
+#ifdef NODEBUG
+	/*Disable software and data breakpoints */
+	mov	r0,#0
+	mcr	p15,0,r0,c14,c8,0  /* ibcr0 */
+	mcr	p15,0,r0,c14,c9,0  /* ibcr1 */
+	mcr	p15,0,r0,c14,c4,0  /* dbcon */
+
+	/*Enable all debug functionality */
+	mov	r0,#0x80000000
+	mcr	p14,0,r0,c10,c0,0  /* dcsr */
+#endif
+
+	/* ---------------------------------------------------------------- */
+	/* End lowlevel_init							    */
+	/* ---------------------------------------------------------------- */
+
+endlowlevel_init:
+
+	mov	pc, lr

board/adsvix/pcmcia.c

@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pxa-regs.h>
+
+void pcmcia_power_on(void)
+{
+#if 0
+	if (!(GPLR(20) & GPIO_bit(20))) { /* 3.3V */
+		GPCR(81) = GPIO_bit(81);
+		GPSR(82) = GPIO_bit(82);
+	}
+	else if (!(GPLR(21) & GPIO_bit(21))) { /* 5.0V */
+		GPCR(81) = GPIO_bit(81);
+		GPCR(82) = GPIO_bit(82);
+	}
+#else
+#warning "Board will only supply 5V, wait for next HW spin for selectable power"
+	/* 5.0V */
+	GPCR(81) = GPIO_bit(81);
+	GPCR(82) = GPIO_bit(82);
+#endif
+
+	udelay(300000);
+
+	/* reset the card */
+	GPSR(52) = GPIO_bit(52);
+
+	/* enable PCMCIA */
+	GPCR(83) = GPIO_bit(83);
+
+	/* clear reset */
+	udelay(10);
+	GPCR(52) = GPIO_bit(52);
+
+	udelay(20000);
+}
+
+void pcmcia_power_off(void)
+{
+	/* 0V */
+	GPSR(81) = GPIO_bit(81);
+	GPSR(82) = GPIO_bit(82);
+	/* disable PCMCIA */
+	GPSR(83) = GPIO_bit(83);
+}

board/adsvix/pxavoltage.S

@@ -0,0 +1,230 @@
+/*
+ * (C) Copyright 2004
+ * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/pxa-regs.h>
+
+#define LTC1663_ADDR    0x20
+
+#define LTC1663_SY	0x01	/* Sync ACK */
+#define LTC1663_SD	0x04	/* shutdown */
+#define LTC1663_BG	0x04	/* Internal Voltage Ref */
+
+#define VOLT_1_55         18    /* DAC value for 1.55V */
+
+		.global	initPXAvoltage
+
+@ Set the voltage to 1.55V early in the boot process so we can run
+@ at a high clock speed and boot quickly.  Note that this is necessary
+@ because the reset button does not reset the CPU voltage, so if the
+@ voltage was low (say 0.85V) then the CPU would crash without this
+@ routine
+
+@ This routine clobbers r0-r4
+
+initializei2c:
+
+		ldr	r2, =CKEN
+		ldr	r3, [r2]
+		orr	r3, r3, #CKEN15_PWRI2C
+		str	r3, [r2]
+
+		ldr	r2, =PCFR
+		ldr	r3, [r2]
+		orr	r3, r3, #PCFR_PI2C_EN
+		str	r3, [r2]
+
+		/* delay for about 250msec
+		 */
+		ldr	r3, =OSCR
+		mov	r2, #0
+		str	r2, [r3]
+		ldr	r1, =0xC0000
+
+1:
+		ldr	r2, [r3]
+		cmp	r1, r2
+		bgt	1b
+		ldr	r0, =PWRICR
+		ldr	r1, [r0]
+		bic	r1, r1, #(ICR_MA | ICR_START | ICR_STOP)
+		str	r1, [r0]
+
+		orr	r1, r1, #ICR_UR
+		str	r1, [r0]
+
+		ldr	r2, =PWRISR
+		ldr	r3, =0x7ff
+		str	r3, [r2]
+
+		bic	r1, r1, #ICR_UR
+		str	r1, [r0]
+
+		mov	r1, #(ICR_GCD | ICR_SCLE)
+		str	r1, [r0]
+
+		orr	r1, r1, #ICR_IUE
+		str	r1, [r0]
+
+		orr	r1, r1, #ICR_FM
+		str	r1, [r0]
+
+		/* delay for about 1msec
+		 */
+		ldr	r3, =OSCR
+		mov	r2, #0
+		str	r2, [r3]
+		ldr	r1, =0xC00
+
+1:
+		ldr	r2, [r3]
+		cmp	r1, r2
+		bgt	1b
+		mov	pc, lr
+
+sendbytei2c:
+		ldr	r3, =PWRIDBR
+		str	r0, [r3]
+		ldr	r3, =PWRICR
+		ldr	r0, [r3]
+		orr	r0, r0, r1
+		bic	r0, r0, r2
+		str	r0, [r3]
+		orr	r0, r0, #ICR_TB
+		str	r0, [r3]
+
+		mov	r2, #0x100000
+
+waitfortxemptyi2c:
+
+		ldr	r0, =PWRISR
+		ldr	r1, [r0]
+
+		/* take it from the top if we don't get empty after a while */
+		subs	r2, r2, #1
+		moveq	lr, r4
+		beq	initPXAvoltage
+
+		tst	r1, #ISR_ITE
+
+		beq	waitfortxemptyi2c
+
+		orr	r1, r1, #ISR_ITE
+		str	r1, [r0]
+
+		mov	pc, lr
+
+initPXAvoltage:
+
+		mov	r4, lr
+
+		bl	setleds
+
+		bl	initializei2c
+
+		bl	setleds
+
+		/* now send the real message to set the correct voltage */
+		ldr	r0, =LTC1663_ADDR
+		mov	r0, r0, LSL #1
+		mov	r1, #ICR_START
+		ldr	r2, =(ICR_STOP | ICR_ALDIE | ICR_ACKNAK)
+		bl	sendbytei2c
+
+		bl	setleds
+
+		mov	r0, #LTC1663_BG
+		mov	r1, #0
+		mov	r2, #(ICR_STOP | ICR_START)
+		bl	sendbytei2c
+
+		bl	setleds
+
+		ldr	r0, =VOLT_1_55
+		and	r0, r0, #0xff
+		mov	r1, #0
+		mov	r2, #(ICR_STOP | ICR_START)
+		bl	sendbytei2c
+
+		bl	setleds
+
+		ldr	r0, =VOLT_1_55
+		mov	r0, r0, ASR #8
+		and	r0, r0, #0xff
+		mov	r1, #ICR_STOP
+		mov	r2, #ICR_START
+		bl	sendbytei2c
+
+		bl	setleds
+
+		@ delay a little for the volatage to stablize
+		ldr	r3, =OSCR
+		mov	r2, #0
+		str	r2, [r3]
+		ldr	r1, =0xC0
+
+1:
+		ldr	r2, [r3]
+		cmp	r1, r2
+		bgt	1b
+		mov	pc, r4
+
+setleds:
+	mov		pc, lr
+
+	ldr		r5, =0x40e00058
+	ldr		r3, [r5]
+	bic		r3, r3, #0x3
+	str		r3, [r5]
+	ldr		r5, =0x40e0000c
+	ldr		r3, [r5]
+	orr		r3, r3, #0x00010000
+	str		r3, [r5]
+
+	@ inner loop
+	mov		r0, #0x2
+1:
+
+	ldr		r5, =0x40e00018
+	mov		r3, #0x00010000
+	str		r3, [r5]
+
+	@ outer loop
+	mov		r3, #0x00F00000
+2:
+	subs		r3, r3, #1
+	bne		2b
+
+	ldr		r5, =0x40e00024
+	mov		r3, #0x00010000
+	str		r3, [r5]
+
+	@ outer loop
+	mov		r3, #0x00F00000
+3:
+	subs		r3, r3, #1
+	bne		3b
+
+	subs		r0, r0, #1
+	bne		1b
+
+	mov		pc, lr

board/adsvix/u-boot.lds

@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/pxa/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/alaska/Makefile

@@ -1,4 +1,4 @@
-# (C) Copyright 2003-2004
+# (C) Copyright 2003-2005
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -24,7 +24,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= lib$(BOARD).a
 
-OBJS	:= $(BOARD).o flash.o extserial.o serial.o
+OBJS	:= $(BOARD).o flash.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS)

board/alaska/extserial.c

@@ -1,110 +0,0 @@
-/*
- * (C) Copyright 2004, Freescale, Inc
- * TsiChung Liew, Tsi-Chung.Liew@freescale.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-/*
- * Minimal serial functions needed to use one of the PSC ports
- * as serial console interface.
- */
-
-#include <common.h>
-#include <mpc8220.h>
-
-#if defined (CONFIG_EXTUART_CONSOLE)
-#   include <ns16550.h>
-
-#   define PADSERIAL_BAUD_115200   0x40
-#   define PADSERIAL_BAUD_57600    0x20
-#   define PADSERIAL_BAUD_9600     0
-#   define PADCARD_FREQ            18432000
-
-const NS16550_t com_port = (NS16550_t) CFG_NS16550_COM1;
-
-int ext_serial_init (void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-	volatile u8 *dipswitch = (volatile u8 *) (CFG_CPLD_BASE + 0x1002);
-	int baud_divisor;
-
-	/* Find out the baud rate speed on debug card dip switches */
-	if (*dipswitch & PADSERIAL_BAUD_115200)
-		gd->baudrate = 115200;
-	else if (*dipswitch & PADSERIAL_BAUD_57600)
-		gd->baudrate = 57600;
-	else
-		gd->baudrate = 9600;
-
-	/* Debug card frequency */
-	baud_divisor = PADCARD_FREQ / (16 * gd->baudrate);
-
-	NS16550_init (com_port, baud_divisor);
-
-	return (0);
-}
-
-void ext_serial_putc (const char c)
-{
-	if (c == '\n')
-		NS16550_putc (com_port, '\r');
-
-	NS16550_putc (com_port, c);
-}
-
-void ext_serial_puts (const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
-
-int ext_serial_getc (void)
-{
-	return NS16550_getc (com_port);
-}
-
-int ext_serial_tstc (void)
-{
-	return NS16550_tstc (com_port);
-}
-
-void ext_serial_setbrg (void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	volatile u8 *dipswitch = (volatile u8 *) (CFG_CPLD_BASE + 0x1002);
-	int baud_divisor;
-
-	/* Find out the baud rate speed on debug card dip switches */
-	if (*dipswitch & PADSERIAL_BAUD_115200)
-		gd->baudrate = 115200;
-	else if (*dipswitch & PADSERIAL_BAUD_57600)
-		gd->baudrate = 57600;
-	else
-		gd->baudrate = 9600;
-
-	/* Debug card frequency */
-	baud_divisor = PADCARD_FREQ / (16 * gd->baudrate);
-
-	NS16550_reinit (com_port, baud_divisor);
-}
-#endif /* CONFIG_EXTUART_CONSOLE */

board/alaska/serial.c

@@ -1,131 +0,0 @@
-/*
- * (C) Copyright 2004, Freescale, Inc
- * TsiChung Liew, Tsi-Chung.Liew@freescale.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-/*
- * Minimal serial functions needed to use one of the PSC ports
- * as serial console interface.
- */
-
-#include <common.h>
-#include <mpc8220.h>
-
-int serial_init (void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-#if defined (CONFIG_EXTUART_CONSOLE)
-	volatile uchar *cpld = (volatile uchar *) CFG_CPLD_BASE;
-#endif
-
-	/* Check CPLD Switch 2 whether is external or internal */
-#if defined (CONFIG_EXTUART_CONSOLE)
-	if ((*cpld & 0x02) == 0x02) {
-		gd->bExtUart = 1;
-		return ext_serial_init ();
-	} else
-#endif
-	{
-#if defined(CONFIG_PSC_CONSOLE)
-		gd->bExtUart = 0;
-		return psc_serial_init ();
-#endif
-	}
-
-	return (0);
-}
-
-void serial_putc (const char c)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	if (gd->bExtUart) {
-#if defined (CONFIG_EXTUART_CONSOLE)
-		ext_serial_putc (c);
-#endif
-	} else {
-#if defined(CONFIG_PSC_CONSOLE)
-		psc_serial_putc (c);
-#endif
-	}
-}
-
-void serial_puts (const char *s)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	if (gd->bExtUart) {
-#if defined (CONFIG_EXTUART_CONSOLE)
-		ext_serial_puts (s);
-#endif
-	} else {
-#if defined(CONFIG_PSC_CONSOLE)
-		psc_serial_puts (s);
-#endif
-	}
-}
-
-int serial_getc (void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	if (gd->bExtUart) {
-#if defined (CONFIG_EXTUART_CONSOLE)
-		return ext_serial_getc ();
-#endif
-	} else {
-#if defined(CONFIG_PSC_CONSOLE)
-		return psc_serial_getc ();
-#endif
-	}
-}
-
-int serial_tstc (void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	if (gd->bExtUart) {
-#if defined (CONFIG_EXTUART_CONSOLE)
-		return ext_serial_tstc ();
-#endif
-	} else {
-#if defined(CONFIG_PSC_CONSOLE)
-		return psc_serial_tstc ();
-#endif
-	}
-}
-
-void serial_setbrg (void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	if (gd->bExtUart) {
-#if defined (CONFIG_EXTUART_CONSOLE)
-		ext_serial_setbrg ();
-#endif
-	} else {
-#if defined(CONFIG_PSC_CONSOLE)
-		psc_serial_setbrg ();
-#endif
-	}
-}

board/assabet/setup.S

@@ -80,8 +80,8 @@ BCR_DB1110:	.long	ASSABET_BCR_DB1110
 LEDS:		.long	NEPONSET_LEDS
 
 
-	.globl memsetup
-memsetup:
+	.globl lowlevel_init
+lowlevel_init:
 
 	/* Setting up the memory and stuff */
 

board/at91rm9200dk/Makefile

@@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	:= at91rm9200dk.o at45.o dm9161.o flash.o
-SOBJS	:= memsetup.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)

board/at91rm9200dk/memsetup.S

@@ -1,200 +0,0 @@
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- *		       Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Modified for the at91rm9200dk board by
- * (C) Copyright 2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-
-#ifdef CONFIG_BOOTBINFUNC
-/*
- * some parameters for the board
- *
- * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in
- * turn is based on the boot.bin code from ATMEL
- *
- */
-
-/* flash */
-#define MC_PUIA 0xFFFFFF10
-#define MC_PUIA_VAL 0x00000000
-#define MC_PUP 0xFFFFFF50
-#define MC_PUP_VAL 0x00000000
-#define MC_PUER 0xFFFFFF54
-#define MC_PUER_VAL 0x00000000
-#define MC_ASR 0xFFFFFF04
-#define MC_ASR_VAL 0x00000000
-#define MC_AASR 0xFFFFFF08
-#define MC_AASR_VAL 0x00000000
-#define EBI_CFGR 0xFFFFFF64
-#define EBI_CFGR_VAL 0x00000000
-#define SMC2_CSR 0xFFFFFF70
-#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
-
-/* clocks */
-#define PLLAR 0xFFFFFC28
-#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
-#define PLLBR 0xFFFFFC2C
-#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
-#define MCKR 0xFFFFFC30
-#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
-
-/* sdram */
-#define PIOC_ASR 0xFFFFF870
-#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
-#define PIOC_BSR 0xFFFFF874
-#define PIOC_BSR_VAL 0x00000000
-#define PIOC_PDR 0xFFFFF804
-#define PIOC_PDR_VAL 0xFFFF0000
-#define EBI_CSA 0xFFFFFF60
-#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
-#define SDRC_CR 0xFFFFFF98
-#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */
-#define SDRAM 0x20000000 /* address of the SDRAM */
-#define SDRAM1 0x20000080 /* address of the SDRAM */
-#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
-#define SDRC_MR 0xFFFFFF90
-#define SDRC_MR_VAL 0x00000002 /* Precharge All */
-#define SDRC_MR_VAL1 0x00000004 /* refresh */
-#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
-#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
-#define SDRC_TR 0xFFFFFF94
-#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
-
-
-_TEXT_BASE:
-	.word	TEXT_BASE
-
-.globl lowlevelinit
-lowlevelinit:
-	/* memory control configuration */
-	/* this isn't very elegant, but	 what the heck */
-	ldr	r0, =SMRDATA
-	ldr	r1, _TEXT_BASE
-	sub	r0, r0, r1
-	add	r2, r0, #80
-0:
-	/* the address */
-	ldr	r1, [r0], #4
-	/* the value */
-	ldr	r3, [r0], #4
-	str	r3, [r1]
-	cmp	r2, r0
-	bne	0b
-	/* delay - this is all done by guess */
-	ldr	r0, =0x00010000
-1:
-	subs	r0, r0, #1
-	bhi	1b
-	ldr	r0, =SMRDATA1
-	ldr	r1, _TEXT_BASE
-	sub	r0, r0, r1
-	add	r2, r0, #176
-2:
-	/* the address */
-	ldr	r1, [r0], #4
-	/* the value */
-	ldr	r3, [r0], #4
-	str	r3, [r1]
-	cmp	r2, r0
-	bne	2b
-
-	/* everything is fine now */
-	mov	pc, lr
-
-	.ltorg
-
-SMRDATA:
-	.word MC_PUIA
-	.word MC_PUIA_VAL
-	.word MC_PUP
-	.word MC_PUP_VAL
-	.word MC_PUER
-	.word MC_PUER_VAL
-	.word MC_ASR
-	.word MC_ASR_VAL
-	.word MC_AASR
-	.word MC_AASR_VAL
-	.word EBI_CFGR
-	.word EBI_CFGR_VAL
-	.word SMC2_CSR
-	.word SMC2_CSR_VAL
-	.word PLLAR
-	.word PLLAR_VAL
-	.word PLLBR
-	.word PLLBR_VAL
-	.word MCKR
-	.word MCKR_VAL
-	/* SMRDATA is 80 bytes long */
-	/* here there's a delay of 100 */
-SMRDATA1:
-	.word PIOC_ASR
-	.word PIOC_ASR_VAL
-	.word PIOC_BSR
-	.word PIOC_BSR_VAL
-	.word PIOC_PDR
-	.word PIOC_PDR_VAL
-	.word EBI_CSA
-	.word EBI_CSA_VAL
-	.word SDRC_CR
-	.word SDRC_CR_VAL
-	.word SDRC_MR
-	.word SDRC_MR_VAL
-	.word SDRAM
-	.word SDRAM_VAL
-	.word SDRC_MR
-	.word SDRC_MR_VAL1
-	.word SDRAM
-	.word SDRAM_VAL
-	.word SDRAM
-	.word SDRAM_VAL
-	.word SDRAM
-	.word SDRAM_VAL
-	.word SDRAM
-	.word SDRAM_VAL
-	.word SDRAM
-	.word SDRAM_VAL
-	.word SDRAM
-	.word SDRAM_VAL
-	.word SDRAM
-	.word SDRAM_VAL
-	.word SDRAM
-	.word SDRAM_VAL
-	.word SDRC_MR
-	.word SDRC_MR_VAL2
-	.word SDRAM1
-	.word SDRAM_VAL
-	.word SDRC_TR
-	.word SDRC_TR_VAL
-	.word SDRAM
-	.word SDRAM_VAL
-	.word SDRC_MR
-	.word SDRC_MR_VAL3
-	.word SDRAM
-	.word SDRAM_VAL
-	/* SMRDATA1 is 176 bytes long */
-#endif /* CONFIG_BOOTBINFUNC */

board/at91rm9200dk/u-boot.lds

@@ -32,7 +32,7 @@ SECTIONS
 	. = ALIGN(4);
 	.text      :
 	{
-	  cpu/at91rm9200/start.o	(.text)
+	  cpu/arm920t/start.o	(.text)
 	  *(.text)
 	}
 

board/canmb/Makefile

@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o
+#../common/flash.o ../common/vpd.o ../common/am79c874.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/canmb/canmb.c

@@ -0,0 +1,251 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#if defined(CONFIG_MPC5200_DDR)
+#include "mt46v16m16-75.h"
+#else
+#include "mt48lc16m32s2-75.h"
+#endif
+
+#ifndef CFG_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+#if defined(CONFIG_MPC5200)
+long int initdram (int board_type)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+#ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set tap delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	/* let SDRAM CS1 start right after CS0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+	/* find RAM size using SDRAM CS1 only */
+	if (!dramsize)
+		sdram_start(0);
+	test2 = test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	if (!dramsize) {
+		sdram_start(1);
+		test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	}
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize2 = test1;
+	} else {
+		dramsize2 = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize2 < (1 << 20)) {
+		dramsize2 = 0;
+	}
+
+	/* set SDRAM CS1 size according to the amount of RAM found */
+	if (dramsize2 > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+	}
+
+#else /* CFG_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CFG_RAMBOOT */
+
+	return dramsize + dramsize2;
+}
+
+#elif defined(CONFIG_MGT5100)
+
+long int initdram (int board_type)
+{
+	ulong dramsize = 0;
+#ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
+	/* setup and enable SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
+	*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+
+	/* address select register */
+	*(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
+	__asm__ volatile ("sync");
+
+	/* find RAM size */
+	sdram_start(0);
+	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* set SDRAM end address according to size */
+	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
+
+#else /* CFG_RAMBOOT */
+
+	/* Retrieve amount of SDRAM available */
+	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
+
+#endif /* CFG_RAMBOOT */
+
+	return dramsize;
+}
+
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif
+
+int checkboard (void)
+{
+	puts ("Board: CANMB\n");
+	return 0;
+}
+
+int board_early_init_r (void)
+{
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+	*(vu_long *)MPC5XXX_BOOTCS_START =
+	*(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE);
+	*(vu_long *)MPC5XXX_BOOTCS_STOP =
+	*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE);
+	return 0;
+}

board/canmb/config.mk

@@ -0,0 +1,39 @@
+#
+# (C) Copyright 2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2003
+# Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# CANMB board
+#
+# allowed and functional TEXT_BASE values:
+#
+#   0xfe000000		low boot at 0x00000100 (default board setting)
+#	0x00100000		RAM load and test
+#
+
+TEXT_BASE = 0xFE000000
+#TEXT_BASE = 0x00100000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board

board/canmb/mt48lc16m32s2-75.h

@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_DDR	0		/* is SDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+#define SDRAM_CONFIG2	0x8AD70000
+
+#elif defined(CONFIG_MGT5100)
+/* Settings for XLB = 66 MHz */
+#define SDRAM_MODE	0x008D0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xC2222600
+#define SDRAM_CONFIG2	0x88B70004
+#define SDRAM_ADDRSEL	0x02000000
+
+#else
+#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
+#endif

board/canmb/u-boot.lds

@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc5xxx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/cerf250/Makefile

@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	:= cerf250.o flash.o
-SOBJS	:= memsetup.o
+SOBJS	:= lowlevel_init.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)

board/cerf250/lowlevel_init.S

@@ -3,7 +3,7 @@
  *
  * NOTE: I haven't clean this up considerably, just enough to get it
  * running. See hal_platform_setup.h for the source. See
- * board/cradle/memsetup.S for another PXA250 setup that is
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
  * much cleaner.
  *
  * See file CREDITS for list of people who contributed to this
@@ -43,8 +43,8 @@ DRAM_SIZE:  .long   CFG_DRAM_SIZE
  * 	Memory setup
  */
 
-.globl memsetup
-memsetup:
+.globl lowlevel_init
+lowlevel_init:
 
 	/* Set up GPIO pins first ----------------------------------------- */
 
@@ -403,9 +403,9 @@ initclks:
 #endif
 
 	/* ---------------------------------------------------------------- */
-	/* End memsetup                                                     */
+	/* End lowlevel_init                                                     */
 	/* ---------------------------------------------------------------- */
 
-endmemsetup:
+endlowlevel_init:
 
     mov     pc,	lr

board/cm4008/Makefile

@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= cm4008.o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/cm4008/cm4008.c

@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2005
+ * Greg Ungerer, OpenGear Inc, <greg.ungerer@opengear.com>
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/platform.h>
+
+/* ------------------------------------------------------------------------- */
+
+#define	ks8695_read(a)	  *((volatile unsigned int *) (KS8695_IO_BASE+(a)))
+#define	ks8695_write(a,b) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) = (b)
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+int env_flash_cmdline (void)
+{
+	unsigned char *sp = (unsigned char *) 0x0201c020;
+	unsigned char *ep;
+	int len;
+
+	/* Check if "erase" push button is depressed */
+	if ((ks8695_read(KS8695_GPIO_DATA) & 0x8) == 0) {
+		printf("### Entering network recovery mode...\n");
+		setenv("bootargs", "console=ttyAM0,115200 mem=16M initrd=0x400000,6M root=/dev/ram0");
+		setenv("bootcmd", "bootp 0x400000; gofsk 0x400000");
+		setenv("bootdelay", "2");
+		return 0;
+	}
+
+	/* Check for flash based kernel boot args to use as default */
+	for (ep = sp, len = 0; ((len < 1024) && (*ep != 0)); ep++, len++)
+		;
+
+	if ((len > 0) && (len <1024))
+		setenv("bootargs", sp);
+
+	return 0;
+}
+
+int board_late_init (void)
+{
+	return 0;
+}
+
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* arch number of CM4008 */
+	gd->bd->bi_arch_number = 624;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	/* power down all but port 0 on the switch */
+	ks8695_write(KS8695_SWITCH_LPPM12, 0x00000005);
+	ks8695_write(KS8695_SWITCH_LPPM34, 0x00050005);
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}

board/cm4008/config.mk

@@ -0,0 +1 @@
+TEXT_BASE = 0x00f00000

board/cm4008/flash.c

@@ -0,0 +1,409 @@
+/*
+ * (C) Copyright 2005
+ * Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com
+ *
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (unsigned char * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, unsigned char data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		case 1:
+			/* ignore for now */
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_FLASH_BASE,
+		       CFG_FLASH_BASE + _bss_start - _armboot_start,
+		       &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return;
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (unsigned char * addr, flash_info_t * info)
+{
+	volatile unsigned char value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = 0xAA;
+	addr[0x2AAA] = 0x55;
+	addr[0x5555] = 0x90;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (unsigned char)INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = 0xFF;	/* restore read mode */
+		return (0);	/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[2];	/* device ID            */
+
+	switch (value) {
+
+	case (unsigned char)INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;		/* => 8 MB     */
+
+	case (unsigned char)INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;		/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = 0xFF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot)
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	else
+		printf ("\n");
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			volatile unsigned char *addr;
+			unsigned char status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			addr = (volatile unsigned char *) (info->start[sect]);
+			*addr = 0x50;	/* clear status register */
+			*addr = 0x20;	/* erase setup */
+			*addr = 0xD0;	/* erase confirm */
+
+			while (((status = *addr) & 0x80) != 0x80) {
+				if (get_timer_masked () >
+				    CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = 0xB0;	/* suspend erase */
+					*addr = 0xFF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = 0x50;	/* clear status register cmd */
+			*addr = 0xFF;	/* resest to read mode */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	unsigned char data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return 4;
+
+	wp = addr;
+	port_width = 1;
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, unsigned char data)
+{
+	volatile unsigned char *addr = (volatile unsigned char *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr,
+			(ulong) * addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = 0x40;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & 0x80) != 0x80) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = 0xFF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = 0xFF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}

board/cm4008/u-boot.lds

@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm920t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/cm41xx/Makefile

@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= cm41xx.o flash.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/cm41xx/cm41xx.c

@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2005
+ * Greg Ungerer, OpenGear Inc, <greg.ungerer@opengear.com>
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/platform.h>
+
+/* ------------------------------------------------------------------------- */
+
+#define	ks8695_read(a)	  *((volatile unsigned int *) (KS8695_IO_BASE+(a)))
+#define	ks8695_write(a,b) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) = (b)
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+int env_flash_cmdline (void)
+{
+	unsigned char *sp = (unsigned char *) 0x0201c020;
+	unsigned char *ep;
+	int len;
+
+	/* Check if "erase" push button is depressed */
+	if ((ks8695_read(KS8695_GPIO_DATA) & 0x8) == 0) {
+		printf("### Entering network recovery mode...\n");
+		setenv("bootargs", "console=ttyAM0,115200 mem=32M initrd=0x400000,8M root=/dev/ram0");
+		setenv("bootcmd", "bootp 0x400000; gofsk 0x400000");
+		setenv("bootdelay", "2");
+		return 0;
+	}
+
+	/* Check for flash based kernel boot args to use as default */
+	for (ep = sp, len = 0; ((len < 1024) && (*ep != 0)); ep++, len++)
+		;
+
+	if ((len > 0) && (len <1024))
+		setenv("bootargs", sp);
+
+	return 0;
+}
+
+int board_late_init (void)
+{
+	return 0;
+}
+
+
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* arch number of CM41xx */
+	gd->bd->bi_arch_number = 672;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	/* power down all but port 0 on the switch */
+	ks8695_write(KS8695_SWITCH_LPPM12, 0x00000005);
+	ks8695_write(KS8695_SWITCH_LPPM34, 0x00050005);
+
+	return 0;
+}
+
+int dram_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}

board/cm41xx/config.mk

@@ -0,0 +1 @@
+TEXT_BASE = 0x00f00000

board/cm41xx/flash.c

@@ -0,0 +1,409 @@
+/*
+ * (C) Copyright 2005
+ * Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com
+ *
+ * (C) Copyright 2001
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/byteorder/swab.h>
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (unsigned char * addr, flash_info_t * info);
+static int write_data (flash_info_t * info, ulong dest, unsigned char data);
+static void flash_get_offsets (ulong base, flash_info_t * info);
+void inline spin_wheel (void);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+	int i;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		switch (i) {
+		case 0:
+			flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]);
+			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
+			break;
+		case 1:
+			/* ignore for now */
+			flash_info[i].flash_id = FLASH_UNKNOWN;
+			break;
+		default:
+			panic ("configured too many flash banks!\n");
+			break;
+		}
+		size += flash_info[i].size;
+	}
+
+	/* Protect monitor and environment sectors
+	 */
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_FLASH_BASE,
+		       CFG_FLASH_BASE + _bss_start - _armboot_start,
+		       &flash_info[0]);
+
+	return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return;
+
+	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
+			info->protect[i] = 0;
+		}
+	}
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:
+		printf ("INTEL ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		printf ("28F128J3A\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+	return;
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size (unsigned char * addr, flash_info_t * info)
+{
+	volatile unsigned char value;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x5555] = 0xAA;
+	addr[0x2AAA] = 0x55;
+	addr[0x5555] = 0x90;
+
+	mb ();
+	value = addr[0];
+
+	switch (value) {
+
+	case (unsigned char)INTEL_MANUFACT:
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		addr[0] = 0xFF;	/* restore read mode */
+		return (0);	/* no or unknown flash  */
+	}
+
+	mb ();
+	value = addr[2];	/* device ID            */
+
+	switch (value) {
+
+	case (unsigned char)INTEL_ID_28F640J3A:
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;		/* => 8 MB     */
+
+	case (unsigned char)INTEL_ID_28F128J3A:
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;		/* => 16 MB     */
+
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		break;
+	}
+
+	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+		printf ("** ERROR: sector count %d > max (%d) **\n",
+			info->sector_count, CFG_MAX_FLASH_SECT);
+		info->sector_count = CFG_MAX_FLASH_SECT;
+	}
+
+	addr[0] = 0xFF;	/* restore read mode */
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	int flag, prot, sect;
+	ulong type;
+	int rcode = 0;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	type = (info->flash_id & FLASH_VENDMASK);
+	if ((type != FLASH_MAN_INTEL)) {
+		printf ("Can't erase unknown flash type %08lx - aborted\n",
+			info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot)
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	else
+		printf ("\n");
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			volatile unsigned char *addr;
+			unsigned char status;
+
+			printf ("Erasing sector %2d ... ", sect);
+
+			/* arm simple, non interrupt dependent timer */
+			reset_timer_masked ();
+
+			addr = (volatile unsigned char *) (info->start[sect]);
+			*addr = 0x50;	/* clear status register */
+			*addr = 0x20;	/* erase setup */
+			*addr = 0xD0;	/* erase confirm */
+
+			while (((status = *addr) & 0x80) != 0x80) {
+				if (get_timer_masked () >
+				    CFG_FLASH_ERASE_TOUT) {
+					printf ("Timeout\n");
+					*addr = 0xB0;	/* suspend erase */
+					*addr = 0xFF;	/* reset to read mode */
+					rcode = 1;
+					break;
+				}
+			}
+
+			*addr = 0x50;	/* clear status register cmd */
+			*addr = 0xFF;	/* resest to read mode */
+
+			printf (" done\n");
+		}
+	}
+	return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp;
+	unsigned char data;
+	int count, i, l, rc, port_width;
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return 4;
+
+	wp = addr;
+	port_width = 1;
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+		for (; i < port_width && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+		for (; cnt == 0 && i < port_width; ++i, ++cp) {
+			data = (data << 8) | (*(uchar *) cp);
+		}
+
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	count = 0;
+	while (cnt >= port_width) {
+		data = 0;
+		for (i = 0; i < port_width; ++i) {
+			data = (data << 8) | *src++;
+		}
+		if ((rc = write_data (info, wp, data)) != 0) {
+			return (rc);
+		}
+		wp += port_width;
+		cnt -= port_width;
+		if (count++ > 0x800) {
+			spin_wheel ();
+			count = 0;
+		}
+	}
+
+	if (cnt == 0) {
+		return (0);
+	}
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < port_width; ++i, ++cp) {
+		data = (data << 8) | (*(uchar *) cp);
+	}
+
+	return (write_data (info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word or halfword to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_data (flash_info_t * info, ulong dest, unsigned char data)
+{
+	volatile unsigned char *addr = (volatile unsigned char *) dest;
+	ulong status;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*addr & data) != data) {
+		printf ("not erased at %08lx (%lx)\n", (ulong) addr,
+			(ulong) * addr);
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts ();
+
+	*addr = 0x40;	/* write setup */
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	reset_timer_masked ();
+
+	/* wait while polling the status register */
+	while (((status = *addr) & 0x80) != 0x80) {
+		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+			*addr = 0xFF;	/* restore read mode */
+			return (1);
+		}
+	}
+
+	*addr = 0xFF;	/* restore read mode */
+
+	return (0);
+}
+
+void inline spin_wheel (void)
+{
+	static int p = 0;
+	static char w[] = "\\/-";
+
+	printf ("\010%c", w[p]);
+	(++p == 3) ? (p = 0) : 0;
+}

board/cm41xx/u-boot.lds

@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm920t/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}

board/cmc_pu2/Makefile

@@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	:= cmc_pu2.o at45.o dm9161.o flash.o
-SOBJS	:= memsetup.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)

board/cmc_pu2/cmc_pu2.c

@@ -6,6 +6,8 @@
  * Modified for CMC_PU2 (removed Smart Media support) by Gary Jennejohn
  * (2004) garyj@denx.de
  *
+ * Modified for CMC_BASIC by Martin Krause (2005), TQ-Systems GmbH
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -33,22 +35,67 @@
 /*
  * Miscelaneous platform dependent initialisations
  */
+#define CMC_BASIC	1
+#define CMC_PU2		2
+
+int hw_detect (void);
 
 int board_init (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
+	AT91PS_PIO piob = AT91C_BASE_PIOB;
+	AT91PS_PIO pioc = AT91C_BASE_PIOC;
 
 	/* Enable Ctrlc */
 	console_init_f ();
 
 	/* Correct IRDA resistor problem */
 	/* Set PA23_TXD in Output */
-	(AT91PS_PIO) AT91C_BASE_PIOA->PIO_OER = AT91C_PA23_TXD2;
+	/* (AT91PS_PIO) AT91C_BASE_PIOA->PIO_OER = AT91C_PA23_TXD2; */
 
 	/* memory and cpu-speed are setup before relocation */
 	/* so we do _nothing_ here */
 
-	/* arch number of CMC_PU2-Board */
+	/* PIOB and PIOC clock enabling */
+	*AT91C_PMC_PCER = 1 << AT91C_ID_PIOB;
+	*AT91C_PMC_PCER = 1 << AT91C_ID_PIOC;
+
+	/*
+	 * configure PC0-PC3 as input without pull ups, so RS485 driver enable
+	 * (CMC-PU2) and digital outputs (CMC-BASIC) are deactivated.
+	 */
+	pioc->PIO_ODR = AT91C_PIO_PC0 | AT91C_PIO_PC1 |
+			AT91C_PIO_PC2 | AT91C_PIO_PC3;
+	pioc->PIO_PPUDR = AT91C_PIO_PC0 | AT91C_PIO_PC1 |
+			AT91C_PIO_PC2 | AT91C_PIO_PC3;
+	pioc->PIO_PER = AT91C_PIO_PC0 | AT91C_PIO_PC1 |
+	        	AT91C_PIO_PC2 | AT91C_PIO_PC3;
+
+	/*
+	 * On CMC-PU2 board configure PB3-PB6 to input without pull ups to
+	 * clear the duo LEDs (the external pull downs assure a proper
+	 * signal). On CMC-BASIC set PB3-PB6 to output and drive it
+	 * high, to configure current meassurement on AINx.
+	 */
+	if (hw_detect() & CMC_PU2) {
+		piob->PIO_ODR = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
+				AT91C_PIO_PB5 | AT91C_PIO_PB6;
+	}
+	else if (hw_detect() & CMC_BASIC) {
+		piob->PIO_SODR = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
+				AT91C_PIO_PB5 | AT91C_PIO_PB6;
+		piob->PIO_OER = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
+				AT91C_PIO_PB5 | AT91C_PIO_PB6;
+	}
+	piob->PIO_PPUDR = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
+			AT91C_PIO_PB5 | AT91C_PIO_PB6;
+	piob->PIO_PER = AT91C_PIO_PB3 | AT91C_PIO_PB4 |
+			AT91C_PIO_PB5 | AT91C_PIO_PB6;
+
+	/*
+	 * arch number of CMC_PU2-Board. MACH_TYPE_CMC_PU2 is not supported in
+	 * the linuxarm kernel, yet.
+	 */
 	/* gd->bd->bi_arch_number = MACH_TYPE_CMC_PU2; */
 	gd->bd->bi_arch_number = 251;
 	/* adress of boot parameters */
@@ -65,3 +112,30 @@ int dram_init (void)
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 	return 0;
 }
+
+int checkboard (void)
+{
+	if (hw_detect() & CMC_PU2)
+		puts ("Board: CMC-PU2 (Rittal GmbH)\n");
+	else if (hw_detect() & CMC_BASIC)
+		puts ("Board: CMC-BASIC (Rittal GmbH)\n");
+	else
+		puts ("Board: unknown\n");
+	return 0;
+}
+
+int hw_detect (void)
+{
+	AT91PS_PIO pio = AT91C_BASE_PIOB;
+
+	/* PIOB clock enabling */
+	*AT91C_PMC_PCER = 1 << AT91C_ID_PIOB;
+
+	/* configure PB12 as input without pull up */
+	pio->PIO_ODR = AT91C_PIO_PB12;
+	pio->PIO_PPUDR = AT91C_PIO_PB12;
+	pio->PIO_PER = AT91C_PIO_PB12;
+
+	/* read board identification pin */
+	return ((pio->PIO_PDSR & AT91C_PIO_PB12) ? CMC_PU2 : CMC_BASIC);
+}

board/cmc_pu2/u-boot.lds

@@ -32,7 +32,7 @@ SECTIONS
 	. = ALIGN(4);
 	.text      :
 	{
-	  cpu/at91rm9200/start.o	(.text)
+	  cpu/arm920t/start.o	(.text)
 	  *(.text)
 	}
 

board/cobra5272/Makefile

@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/cobra5272/bdm/cobra5272_uboot.gdb

@@ -0,0 +1,169 @@
+#
+# GDB Init script for the Coldfire 5272 processor.
+#
+# The main purpose of this script is to configure the 
+# DRAM controller so code can be loaded.
+#
+# This file was changed to suite the senTec COBRA5272 board.
+# 
+
+define addresses
+
+set $mbar  = 0x10000001
+set $scr   = $mbar - 1 + 0x004
+set $spr   = $mbar - 1 + 0x006
+set $pmr   = $mbar - 1 + 0x008
+set $apmr  = $mbar - 1 + 0x00e
+set $dir   = $mbar - 1 + 0x010
+set $icr1  = $mbar - 1 + 0x020
+set $icr2  = $mbar - 1 + 0x024
+set $icr3  = $mbar - 1 + 0x028
+set $icr4  = $mbar - 1 + 0x02c
+set $isr   = $mbar - 1 + 0x030
+set $pitr  = $mbar - 1 + 0x034
+set $piwr  = $mbar - 1 + 0x038
+set $pivr  = $mbar - 1 + 0x03f
+set $csbr0 = $mbar - 1 + 0x040
+set $csor0 = $mbar - 1 + 0x044
+set $csbr1 = $mbar - 1 + 0x048
+set $csor1 = $mbar - 1 + 0x04c
+set $csbr2 = $mbar - 1 + 0x050
+set $csor2 = $mbar - 1 + 0x054
+set $csbr3 = $mbar - 1 + 0x058
+set $csor3 = $mbar - 1 + 0x05c
+set $csbr4 = $mbar - 1 + 0x060
+set $csor4 = $mbar - 1 + 0x064
+set $csbr5 = $mbar - 1 + 0x068
+set $csor5 = $mbar - 1 + 0x06c
+set $csbr6 = $mbar - 1 + 0x070
+set $csor6 = $mbar - 1 + 0x074
+set $csbr7 = $mbar - 1 + 0x078
+set $csor7 = $mbar - 1 + 0x07c
+set $pacnt = $mbar - 1 + 0x080
+set $paddr = $mbar - 1 + 0x084
+set $padat = $mbar - 1 + 0x086
+set $pbcnt = $mbar - 1 + 0x088
+set $pbddr = $mbar - 1 + 0x08c
+set $pbdat = $mbar - 1 + 0x08e
+set $pcddr = $mbar - 1 + 0x094
+set $pcdat = $mbar - 1 + 0x096
+set $pdcnt = $mbar - 1 + 0x098
+set $sdcr  = $mbar - 1 + 0x180
+set $sdtr  = $mbar - 1 + 0x184
+set $wrrr  = $mbar - 1 + 0x280
+set $wirr  = $mbar - 1 + 0x283
+set $wcr   = $mbar - 1 + 0x288
+set $wer   = $mbar - 1 + 0x28c
+
+end
+
+
+#
+# Setup system configuration
+#
+define setup-sys
+set *((unsigned short *) $scr) = 0x0003
+set *((unsigned short *) $spr) = 0xffff
+set *((unsigned char *) $pivr) = 0x4f
+end
+
+
+#
+# Setup Chip Selects (as per Motorola M5272C3 board)
+#
+define setup-cs
+
+# CS0 -- FLASH
+set *((unsigned long *) $csbr0) = 0xffe00201
+set *((unsigned long *) $csor0) = 0xffe00014
+
+# CS1 -- external bus test
+set *((unsigned long *) $csbr1) = 0x0
+set *((unsigned long *) $csor1) = 0x0
+
+# CS2 -- Optional FSRAM
+set *((unsigned long *) $csbr2) = 0x30000001
+set *((unsigned long *) $csor2) = 0xfff80000
+
+# CS3 -- not used
+set *((unsigned long *) $csbr3) = 0x0
+set *((unsigned long *) $csor3) = 0x0
+
+# CS4 --  not used
+set *((unsigned long *) $csbr4) = 0x0
+set *((unsigned long *) $csor4) = 0x0
+
+# CS5 -- PLI socket0
+set *((unsigned long *) $csbr5) = 0x0
+set *((unsigned long *) $csor5) = 0x0
+
+# CS6 -- PLI socket1
+set *((unsigned long *) $csbr6) = 0x0
+set *((unsigned long *) $csor6) = 0x0
+
+# CS7 -- SDRAM
+set *((unsigned long *) $csbr7) = 0x00000701
+set *((unsigned long *) $csor7) = 0xff00007c
+
+end
+
+
+#
+# Setup the DRAM controller.
+#
+
+define setup-dram
+set *((unsigned long *) $sdtr) = 0x0000f539
+set *((unsigned long *) $sdcr) = 0x00004211
+
+# Dummy write to start SDRAM
+set *((unsigned long *) 0) = 0
+end
+
+
+#
+# Setup for GPIO pins
+#
+define setup-ppio
+
+# PORT A -- the LED's
+set *((unsigned long *) $pacnt) = 0x00000000
+# lower 8 bits for output:
+set *((unsigned short *) $paddr) = 0xff
+# LED's off:
+set *((unsigned short *) $padat) = 0xff
+
+# PORT B
+set *((unsigned long *) $pbcnt) = 0x55554155
+set *((unsigned short *) $pbddr) = 0x0000
+set *((unsigned short *) $pbdat) = 0x17ea
+
+# PORT C
+#set *((unsigned short *) $pcddr) = 0x0000
+#set *((unsigned short *) $pcdat) = 0x1898
+
+# PORT D
+set *((unsigned long *) $pdcnt) = 0x00000000
+
+end
+
+
+#
+#	Added for uClinux-coldfire target...
+#
+target bdm /dev/bdm
+
+addresses
+setup-sys
+setup-cs
+setup-dram
+setup-ppio
+set print pretty
+set print asm-demangle
+display/i $pc
+
+
+#
+load u-boot
+set $pc=0x20000
+c

board/cobra5272/bdm/gdbinit.reset

@@ -0,0 +1,2 @@
+target bdm /dev/bdmcf0
+q

board/cobra5272/bdm/load-cobra_uboot

@@ -0,0 +1,2 @@
+m68k-bdm-elf-gdb -n -x board/cobra5272/bdm/cobra5272_uboot.gdb u-boot
+

board/cobra5272/bdm/reset

@@ -0,0 +1,2 @@
+m68k-bdm-elf-gdb -n -x bdm/gdbinit.reset
+

board/cobra5272/cobra5272.c

@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/m5272.h>
+#include <asm/immap_5272.h>
+
+
+int checkboard (void)
+{
+	puts ("Board: ");
+	puts ("senTec COBRA5272 Board\n");
+	return 0;
+};
+
+long int initdram (int board_type)
+{
+	volatile sdramctrl_t *sdp = (sdramctrl_t *) (CFG_MBAR + MCFSIM_SDCR);
+
+	sdp->sdram_sdtr = 0xf539;
+	sdp->sdram_sdcr = 0x4211;
+
+	/* Dummy write to start SDRAM */
+	*((volatile unsigned long *) 0) = 0;
+
+	return CFG_SDRAM_SIZE * 1024 * 1024;
+};
+
+int testdram (void)
+{
+	/* TODO: XXX XXX XXX */
+	printf ("DRAM test not implemented!\n");
+
+	return (0);
+}

board/cobra5272/config.mk

@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xffe00000

board/cobra5272/flash.c

@@ -0,0 +1,378 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#define PHYS_FLASH_1 CFG_FLASH_BASE
+#define FLASH_BANK_SIZE 0x200000
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case (AMD_MANUFACT & FLASH_VENDMASK):
+		printf ("AMD: ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case (AMD_ID_PL160CB & FLASH_TYPEMASK):
+		printf ("AM29PL160CB (16Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		goto Done;
+		break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; i++) {
+		if ((i % 5) == 0) {
+			printf ("\n   ");
+		}
+		printf (" %08lX%s", info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf ("\n");
+
+Done:
+}
+
+
+unsigned long flash_init (void)
+{
+	int i, j;
+	ulong size = 0;
+
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		ulong flashbase = 0;
+
+		flash_info[i].flash_id =
+			(AMD_MANUFACT & FLASH_VENDMASK) |
+			(AMD_ID_PL160CB & FLASH_TYPEMASK);
+		flash_info[i].size = FLASH_BANK_SIZE;
+		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		if (i == 0)
+			flashbase = PHYS_FLASH_1;
+		else
+			panic ("configured to many flash banks!\n");
+
+		for (j = 0; j < flash_info[i].sector_count; j++) {
+			if (j == 0) {
+				/* 1st is 16 KiB */
+				flash_info[i].start[j] = flashbase;
+			}
+			if ((j >= 1) && (j <= 2)) {
+				/* 2nd and 3rd are 8 KiB */
+				flash_info[i].start[j] =
+					flashbase + 0x4000 + 0x2000 * (j - 1);
+			}
+			if (j == 3) {
+				/* 4th is 224 KiB */
+				flash_info[i].start[j] = flashbase + 0x8000;
+			}
+			if ((j >= 4) && (j <= 10)) {
+				/* rest is 256 KiB */
+				flash_info[i].start[j] =
+					flashbase + 0x40000 + 0x40000 * (j -
+									 4);
+			}
+		}
+		size += flash_info[i].size;
+	}
+
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_FLASH_BASE,
+		       CFG_FLASH_BASE + 0x3ffff, &flash_info[0]);
+
+	return size;
+}
+
+
+#define CMD_READ_ARRAY		0x00F0
+#define CMD_UNLOCK1		0x00AA
+#define CMD_UNLOCK2		0x0055
+#define CMD_ERASE_SETUP		0x0080
+#define CMD_ERASE_CONFIRM	0x0030
+#define CMD_PROGRAM		0x00A0
+#define CMD_UNLOCK_BYPASS	0x0020
+
+#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1)))
+#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1)))
+
+#define BIT_ERASE_DONE		0x0080
+#define BIT_RDY_MASK		0x0080
+#define BIT_PROGRAM_ERROR	0x0020
+#define BIT_TIMEOUT		0x80000000	/* our flag */
+
+#define READY 1
+#define ERR   2
+#define TMO   4
+
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	ulong result;
+	int iflag, cflag, prot, sect;
+	int rc = ERR_OK;
+	int chip1;
+
+	/* first look for protection bits */
+
+	if (info->flash_id == FLASH_UNKNOWN)
+		return ERR_UNKNOWN_FLASH_TYPE;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		return ERR_INVAL;
+	}
+
+	if ((info->flash_id & FLASH_VENDMASK) !=
+	    (AMD_MANUFACT & FLASH_VENDMASK)) {
+		return ERR_UNKNOWN_FLASH_VENDOR;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+	if (prot)
+		return ERR_PROTECTED;
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	printf ("\n");
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
+		printf ("Erasing sector %2d ... ", sect);
+
+		/* arm simple, non interrupt dependent timer */
+		set_timer (0);
+
+		if (info->protect[sect] == 0) {	/* not protected */
+			volatile u16 *addr =
+				(volatile u16 *) (info->start[sect]);
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
+
+			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+			*addr = CMD_ERASE_CONFIRM;
+
+			/* wait until flash is ready */
+			chip1 = 0;
+
+			do {
+				result = *addr;
+
+				/* check timeout */
+				if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
+					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+					chip1 = TMO;
+					break;
+				}
+
+				if (!chip1
+				    && (result & 0xFFFF) & BIT_ERASE_DONE)
+					chip1 = READY;
+
+			} while (!chip1);
+
+			MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
+
+			if (chip1 == ERR) {
+				rc = ERR_PROG_ERROR;
+				goto outahere;
+			}
+			if (chip1 == TMO) {
+				rc = ERR_TIMOUT;
+				goto outahere;
+			}
+
+			printf ("ok.\n");
+		} else {	/* it was protected */
+
+			printf ("protected!\n");
+		}
+	}
+
+	if (ctrlc ())
+		printf ("User Interrupt!\n");
+
+      outahere:
+	/* allow flash to settle - wait 10 ms */
+	udelay (10000);
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rc;
+}
+
+
+volatile static int write_word (flash_info_t * info, ulong dest, ulong data)
+{
+	volatile u16 *addr = (volatile u16 *) dest;
+	ulong result;
+	int rc = ERR_OK;
+	int cflag, iflag;
+	int chip1;
+
+	/*
+	 * Check if Flash is (sufficiently) erased
+	 */
+	result = *addr;
+	if ((result & data) != data)
+		return ERR_NOT_ERASED;
+
+
+	/*
+	 * Disable interrupts which might cause a timeout
+	 * here. Remember that our exception vectors are
+	 * at address 0 in the flash, and we don't want a
+	 * (ticker) exception to happen while the flash
+	 * chip is in programming mode.
+	 */
+
+	cflag = icache_status ();
+	icache_disable ();
+	iflag = disable_interrupts ();
+
+	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
+	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
+	MEM_FLASH_ADDR1 = CMD_PROGRAM;
+	*addr = data;
+
+	/* arm simple, non interrupt dependent timer */
+	set_timer (0);
+
+	/* wait until flash is ready */
+	chip1 = 0;
+	do {
+		result = *addr;
+
+		/* check timeout */
+		if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
+			chip1 = ERR | TMO;
+			break;
+		}
+		if (!chip1 && ((result & 0x80) == (data & 0x80)))
+			chip1 = READY;
+
+	} while (!chip1);
+
+	*addr = CMD_READ_ARRAY;
+
+	if (chip1 == ERR || *addr != data)
+		rc = ERR_PROG_ERROR;
+
+	if (iflag)
+		enable_interrupts ();
+
+	if (cflag)
+		icache_enable ();
+
+	return rc;
+}
+
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong wp, data;
+	int rc;
+
+	if (addr & 1) {
+		printf ("unaligned destination not supported\n");
+		return ERR_ALIGN;
+	}
+
+#if 0
+	if (cnt & 1) {
+		printf ("odd transfer sizes not supported\n");
+		return ERR_ALIGN;
+	}
+#endif
+
+	wp = addr;
+
+	if (addr & 1) {
+		data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *)
+							  src);
+		if ((rc = write_word (info, wp - 1, data)) != 0) {
+			return (rc);
+		}
+		src += 1;
+		wp += 1;
+		cnt -= 1;
+	}
+
+	while (cnt >= 2) {
+		data = *((volatile u16 *) src);
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 2;
+		wp += 2;
+		cnt -= 2;
+	}
+
+	if (cnt == 1) {
+		data = (*((volatile u8 *) src) << 8) |
+			*((volatile u8 *) (wp + 1));
+		if ((rc = write_word (info, wp, data)) != 0) {
+			return (rc);
+		}
+		src += 1;
+		wp += 1;
+		cnt -= 1;
+	}
+
+	return ERR_OK;
+}

board/cobra5272/u-boot.lds

@@ -0,0 +1,142 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+    cpu/mcf52x2/start.o		(.text)
+    cpu/mcf52x2/cpu_init.o	(.text)
+    lib_m68k/traps.o		(.text)
+    cpu/mcf52x2/interrupts.o	(.text)
+    common/dlmalloc.o		(.text)
+    lib_generic/zlib.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/environment.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/cpu87/Makefile

@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2001-2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/cpu87/config.mk

@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2001-2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# CPU87 board
+#
+
+# This should be equal to the CFG_FLASH_BASE define in configs/cpu87.h
+# for the "final" configuration, with U-Boot in flash, or the address
+# in RAM where U-Boot is loaded at for debugging.
+#
+
+ifeq ($(CONFIG_BOOT_ROM),y)
+	TEXT_BASE := 0xFF800000
+	PLATFORM_CPPFLAGS += -DCONFIG_BOOT_ROM
+else
+	TEXT_BASE := 0xFF000000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)

board/cpu87/cpu87.c

@@ -0,0 +1,333 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include "cpu87.h"
+#include <pci.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+    /* Port A configuration */
+    {	/*	      conf ppar psor pdir podr pdat */
+	/* PA31 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII COL */
+	/* PA30 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII CRS */
+	/* PA29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_ER */
+	/* PA28 */ {   1,   1,   1,   1,   0,   0   }, /* FCC1 MII TX_EN */
+	/* PA27 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_DV */
+	/* PA26 */ {   1,   1,   1,   0,   0,   0   }, /* FCC1 MII RX_ER */
+	/* PA25 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII MDIO */
+	/* PA24 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII MDC */
+	/* PA23 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII MDIO */
+	/* PA22 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII MDC */
+	/* PA21 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[3] */
+	/* PA20 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[2] */
+	/* PA19 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[1] */
+	/* PA18 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 MII TxD[0] */
+	/* PA17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[0] */
+	/* PA16 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[1] */
+	/* PA15 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[2] */
+	/* PA14 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RxD[3] */
+	/* PA13 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII TXSL1 */
+	/* PA12 */ {   1,   0,   0,   1,   0,   1   }, /* FCC2 MII TXSL0 */
+	/* PA11 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII TXSL1 */
+	/* PA10 */ {   1,   0,   0,   1,   0,   1   }, /* FCC1 MII TXSL0 */
+	/* PA9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
+	/* PA8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC2 RXD */
+	/* PA7  */ {   0,   0,   0,   0,   0,   0   }, /* PA7 */
+	/* PA6  */ {   1,   0,   0,   1,   0,   1   }, /* FCC2 MII PAUSE */
+	/* PA5  */ {   1,   0,   0,   1,   0,   1   }, /* FCC1 MII PAUSE */
+	/* PA4  */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MII PWRDN */
+	/* PA3  */ {   1,   0,   0,   1,   0,   0   }, /* FCC1 MII PWRDN */
+	/* PA2  */ {   0,   0,   0,   0,   0,   0   }, /* PA2 */
+	/* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FCC2 MII MDINT */
+	/* PA0  */ {   1,   0,   0,   1,   0,   0   }  /* FCC1 MII MDINT */
+    },
+
+    /* Port B configuration */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+	/* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+	/* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
+	/* PB16 */ {   0,   0,   0,   0,   0,   0   }, /* PB16 */
+	/* PB15 */ {   0,   0,   0,   0,   0,   0   }, /* PB15 */
+	/* PB14 */ {   0,   0,   0,   0,   0,   0   }, /* PB14 */
+	/* PB13 */ {   0,   0,   0,   0,   0,   0   }, /* PB13 */
+	/* PB12 */ {   0,   0,   0,   0,   0,   0   }, /* PB12 */
+	/* PB11 */ {   0,   0,   0,   0,   0,   0   }, /* PB11 */
+	/* PB10 */ {   0,   0,   0,   0,   0,   0   }, /* PB10 */
+	/* PB9  */ {   0,   0,   0,   0,   0,   0   }, /* PB9 */
+	/* PB8  */ {   0,   0,   0,   0,   0,   0   }, /* PB8 */
+	/* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
+	/* PB6  */ {   0,   0,   0,   0,   0,   0   }, /* PB6 */
+	/* PB5  */ {   0,   0,   0,   0,   0,   0   }, /* PB5 */
+	/* PB4  */ {   0,   0,   0,   0,   0,   0   }, /* PB4 */
+	/* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* PB3 */
+	/* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* PB2 */
+	/* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* PB1 */
+	/* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* PB0 */
+    },
+
+    /* Port C */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PC31 */ {   0,   0,   0,   0,   0,   0   }, /* PC31 */
+	/* PC30 */ {   0,   0,   0,   0,   0,   0   }, /* PC30 */
+	/* PC29 */ {   1,   0,   0,   0,   0,   0   }, /* SCC1 CTS */
+	/* PC28 */ {   1,   0,   0,   0,   0,   0   }, /* SCC2 CTS */
+	/* PC27 */ {   0,   0,   0,   0,   0,   0   }, /* PC27 */
+	/* PC26 */ {   0,   0,   0,   0,   0,   0   }, /* PC26 */
+	/* PC25 */ {   0,   0,   0,   0,   0,   0   }, /* PC25 */
+	/* PC24 */ {   0,   0,   0,   0,   0,   0   }, /* PC24 */
+	/* PC23 */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DACFD */
+	/* PC22 */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DNFD */
+	/* PC21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII RX_CLK */
+	/* PC20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 MII TX_CLK */
+	/* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK */
+	/* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII TX_CLK */
+	/* PC17 */ {   0,   0,   0,   0,   0,   0   }, /* PC17 */
+	/* PC16 */ {   0,   0,   0,   0,   0,   0   }, /* PC16 */
+	/* PC15 */ {   0,   0,   0,   0,   0,   0   }, /* PC15 */
+	/* PC14 */ {   0,   0,   0,   0,   0,   0   }, /* PC14 */
+	/* PC13 */ {   0,   0,   0,   0,   0,   0   }, /* PC13 */
+	/* PC12 */ {   0,   0,   0,   0,   0,   0   }, /* PC12 */
+	/* PC11 */ {   0,   0,   0,   0,   0,   0   }, /* PC11 */
+	/* PC10 */ {   0,   0,   0,   0,   0,   0   }, /* PC10 */
+	/* PC9  */ {   0,   0,   0,   0,   0,   0   }, /* FC9 */
+	/* PC8  */ {   0,   0,   0,   0,   0,   0   }, /* PC8 */
+	/* PC7  */ {   0,   0,   0,   0,   0,   0   }, /* PC7 */
+	/* PC6  */ {   0,   0,   0,   0,   0,   0   }, /* PC6 */
+	/* PC5  */ {   0,   0,   0,   0,   0,   0   }, /* PC5 */
+	/* PC4  */ {   0,   0,   0,   0,   0,   0   }, /* PC4 */
+	/* PC3  */ {   0,   0,   0,   0,   0,   0   }, /* PC3 */
+	/* PC2  */ {   0,   0,   0,   0,   0,   0   }, /* PC2 */
+	/* PC1  */ {   0,   0,   0,   0,   0,   0   }, /* PC1 */
+	/* PC0  */ {   0,   0,   0,   0,   0,   0   }, /* FDC37C78 DRQFD */
+    },
+
+    /* Port D */
+    {   /*	      conf ppar psor pdir podr pdat */
+	/* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 RXD */
+	/* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 TXD */
+	/* PD29 */ {   1,   0,   0,   1,   0,   0   }, /* SCC1 RTS */
+	/* PD28 */ {   1,   1,   0,   0,   0,   0   }, /* SCC2 RXD */
+	/* PD27 */ {   1,   1,   0,   1,   0,   0   }, /* SCC2 TXD */
+	/* PD26 */ {   1,   0,   0,   1,   0,   0   }, /* SCC2 RTS */
+	/* PD25 */ {   0,   0,   0,   0,   0,   0   }, /* PD25 */
+	/* PD24 */ {   0,   0,   0,   0,   0,   0   }, /* PD24 */
+	/* PD23 */ {   0,   0,   0,   0,   0,   0   }, /* PD23 */
+	/* PD22 */ {   0,   0,   0,   0,   0,   0   }, /* PD22 */
+	/* PD21 */ {   0,   0,   0,   0,   0,   0   }, /* PD21 */
+	/* PD20 */ {   0,   0,   0,   0,   0,   0   }, /* PD20 */
+	/* PD19 */ {   0,   0,   0,   0,   0,   0   }, /* PD19 */
+	/* PD18 */ {   0,   0,   0,   0,   0,   0   }, /* PD18 */
+	/* PD17 */ {   0,   0,   0,   0,   0,   0   }, /* PD17 */
+	/* PD16 */ {   0,   0,   0,   0,   0,   0   }, /* PD16 */
+#if defined(CONFIG_SOFT_I2C)
+	/* PD15 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SDA */
+	/* PD14 */ {   1,   0,   0,   1,   1,   1   }, /* I2C SCL */
+#else
+#if defined(CONFIG_HARD_I2C)
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#else /* normal I/O port pins */
+	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+#endif
+#endif
+	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
+	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
+	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
+	/* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
+	/* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
+	/* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
+	/* PD7  */ {   0,   0,   0,   0,   0,   0   }, /* PD7 */
+	/* PD6  */ {   0,   0,   0,   0,   0,   0   }, /* PD6 */
+	/* PD5  */ {   0,   0,   0,   0,   0,   0   }, /* PD5 */
+	/* PD4  */ {   0,   0,   0,   0,   0,   0   }, /* PD4 */
+	/* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* PD3 */
+	/* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* PD2 */
+	/* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* PD1 */
+	/* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* PD0 */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/* Check Board Identity:
+ */
+int checkboard (void)
+{
+	printf ("Board: CPU87 (Rev %02x)\n", CPU86_REV);
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
+ *
+ * This routine performs standard 8260 initialization sequence
+ * and calculates the available memory size. It may be called
+ * several times to try different SDRAM configurations on both
+ * 60x and local buses.
+ */
+static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
+			  ulong orx, volatile uchar * base)
+{
+	volatile uchar c = 0xff;
+	volatile uint *sdmr_ptr;
+	volatile uint *orx_ptr;
+	ulong maxsize, size;
+	int i;
+
+	/* We must be able to test a location outsize the maximum legal size
+	 * to find out THAT we are outside; but this address still has to be
+	 * mapped by the controller. That means, that the initial mapping has
+	 * to be (at least) twice as large as the maximum expected size.
+	 */
+	maxsize = (1 + (~orx | 0x7fff)) / 2;
+
+	/* Since CFG_SDRAM_BASE is always 0 (??), we assume that
+	 * we are configuring CS1 if base != 0
+	 */
+	sdmr_ptr = &memctl->memc_psdmr;
+	orx_ptr = &memctl->memc_or2;
+
+	*orx_ptr = orx;
+
+	/*
+	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+	 *
+	 * "At system reset, initialization software must set up the
+	 *  programmable parameters in the memory controller banks registers
+	 *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+	 *  system software should execute the following initialization sequence
+	 *  for each SDRAM device.
+	 *
+	 *  1. Issue a PRECHARGE-ALL-BANKS command
+	 *  2. Issue eight CBR REFRESH commands
+	 *  3. Issue a MODE-SET command to initialize the mode register
+	 *
+	 *  The initial commands are executed by setting P/LSDMR[OP] and
+	 *  accessing the SDRAM with a single-byte transaction."
+	 *
+	 * The appropriate BRx/ORx registers have already been set when we
+	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
+	*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
+	for (i = 0; i < 8; i++)
+		*base = c;
+
+	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
+	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+
+	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+	*base = c;
+
+	size = get_ram_size((long *)base, maxsize);
+
+	*orx_ptr = orx | ~(size - 1);
+
+	return (size);
+}
+
+long int initdram (int board_type)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+
+#ifndef CFG_RAMBOOT
+	ulong size8, size9;
+#endif
+	long psize;
+
+	psize = 32 * 1024 * 1024;
+
+	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_psrt = CFG_PSRT;
+
+#ifndef CFG_RAMBOOT
+	/* 60x SDRAM setup:
+	 */
+	size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
+			  (uchar *) CFG_SDRAM_BASE);
+	size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
+			  (uchar *) CFG_SDRAM_BASE);
+
+	if (size8 < size9) {
+		psize = size9;
+		printf ("(60x:9COL) ");
+	} else {
+		psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
+				  (uchar *) CFG_SDRAM_BASE);
+		printf ("(60x:8COL) ");
+	}
+
+#endif	/* CFG_RAMBOOT */
+
+	icache_enable ();
+
+	return (psize);
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_DOC)
+extern void doc_probe (ulong physadr);
+void doc_init (void)
+{
+	doc_probe (CFG_DOC_BASE);
+}
+#endif
+
+#ifdef	CONFIG_PCI
+struct pci_controller hose;
+
+extern void pci_mpc8250_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc8250_init(&hose);
+}
+#endif

board/cpu87/cpu87.h

@@ -0,0 +1,27 @@
+#ifndef __BOARD_CPU87__
+#define __BOARD_CPU87__
+
+#include <config.h>
+
+#define REG8(x)			(*(volatile unsigned char *)(x))
+
+/* CPU86 register definitions */
+#define CPU86_VME_EAC		REG8(CFG_BCRS_BASE + 0x00)
+#define CPU86_VME_SAC		REG8(CFG_BCRS_BASE + 0x01)
+#define CPU86_VME_MAC		REG8(CFG_BCRS_BASE + 0x02)
+#define CPU86_BCR		REG8(CFG_BCRS_BASE + 0x03)
+#define CPU86_BSR		REG8(CFG_BCRS_BASE + 0x04)
+#define CPU86_WDOG_RPORT	REG8(CFG_BCRS_BASE + 0x05)
+#define CPU86_MBOX_IRQ		REG8(CFG_BCRS_BASE + 0x04)
+#define CPU86_REV		REG8(CFG_BCRS_BASE + 0x07)
+#define CPU86_VME_IRQMASK	REG8(CFG_BCRS_BASE + 0x80)
+#define CPU86_VME_IRQSTATUS	REG8(CFG_BCRS_BASE + 0x81)
+#define CPU86_LOCAL_IRQMASK	REG8(CFG_BCRS_BASE + 0x82)
+#define CPU86_LOCAL_IRQSTATUS	REG8(CFG_BCRS_BASE + 0x83)
+#define CPU86_PMCL_IRQSTATUS	REG8(CFG_BCRS_BASE + 0x84)
+
+/* Board Control Register bits */
+#define CPU86_BCR_FWPT		0x01
+#define CPU86_BCR_FWRE		0x02
+
+#endif /* __BOARD_CPU87__ */

board/cpu87/flash.c

@@ -0,0 +1,624 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Flash Routines for Intel devices
+ *
+ *--------------------------------------------------------------------
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+#include "cpu87.h"
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+/*-----------------------------------------------------------------------
+ */
+ulong flash_int_get_size (volatile unsigned long *baseaddr,
+					  flash_info_t * info)
+{
+	short i;
+	unsigned long flashtest_h, flashtest_l;
+
+	info->sector_count = info->size = 0;
+	info->flash_id = FLASH_UNKNOWN;
+
+	/* Write identify command sequence and test FLASH answer
+	 */
+	baseaddr[0] = 0x00900090;
+	baseaddr[1] = 0x00900090;
+
+	flashtest_h = baseaddr[0];	/* manufacturer ID	*/
+	flashtest_l = baseaddr[1];
+
+	if (flashtest_h != INTEL_MANUFACT || flashtest_l != INTEL_MANUFACT)
+		return (0);		/* no or unknown flash	*/
+
+	flashtest_h = baseaddr[2];	/* device ID	        */
+	flashtest_l = baseaddr[3];
+
+	if (flashtest_h != flashtest_l)
+		return (0);
+
+	switch (flashtest_h) {
+	case INTEL_ID_28F160C3B:
+		info->flash_id = FLASH_28F160C3B;
+		info->sector_count = 39;
+		info->size = 0x00800000;	/* 4 * 2 MB = 8 MB	*/
+		break;
+	case INTEL_ID_28F160F3B:
+		info->flash_id = FLASH_28F160F3B;
+		info->sector_count = 39;
+		info->size = 0x00800000;	/* 4 * 2 MB = 8 MB      */
+		break;
+	case INTEL_ID_28F640C3B:
+		info->flash_id = FLASH_28F640C3B;
+		info->sector_count = 135;
+		info->size = 0x02000000;	/* 16 * 2 MB = 32 MB	*/
+		break;
+	default:
+		return (0);			/* no or unknown flash	*/
+	}
+
+	info->flash_id |= INTEL_MANUFACT << 16; /* set manufacturer offset */
+
+	if (info->flash_id & FLASH_BTYPE) {
+		volatile unsigned long *tmp = baseaddr;
+
+		/* set up sector start adress table (bottom sector type)
+		 * AND unlock the sectors (if our chip is 160C3)
+		 */
+		for (i = 0; i < info->sector_count; i++) {
+			if (((info->flash_id & FLASH_TYPEMASK) == FLASH_28F160C3B) ||
+			    ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F640C3B)) {
+				tmp[0] = 0x00600060;
+				tmp[1] = 0x00600060;
+				tmp[0] = 0x00D000D0;
+				tmp[1] = 0x00D000D0;
+			}
+			info->start[i] = (uint) tmp;
+			tmp += i < 8 ? 0x2000 : 0x10000; /* pointer arith       */
+		}
+	}
+
+	memset (info->protect, 0, info->sector_count);
+
+	baseaddr[0] = 0x00FF00FF;
+	baseaddr[1] = 0x00FF00FF;
+
+	return (info->size);
+}
+
+static ulong flash_amd_get_size (vu_char *addr, flash_info_t *info)
+{
+	short i;
+	uchar vendor, devid;
+	ulong base = (ulong)addr;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0x90;
+
+	udelay(1000);
+
+	vendor = addr[0];
+	devid = addr[1] & 0xff;
+
+	/* only support AMD */
+	if (vendor != 0x01) {
+		return 0;
+	}
+
+	vendor &= 0xf;
+	devid &= 0xff;
+
+	if (devid == AMD_ID_F040B) {
+		info->flash_id     = vendor << 16 | devid;
+		info->sector_count = 8;
+		info->size         = info->sector_count * 0x10000;
+	}
+	else if (devid == AMD_ID_F080B) {
+		info->flash_id     = vendor << 16 | devid;
+		info->sector_count = 16;
+		info->size         = 4 * info->sector_count * 0x10000;
+	}
+	else if (devid == AMD_ID_F016D) {
+		info->flash_id     = vendor << 16 | devid;
+		info->sector_count = 32;
+		info->size         = 4 * info->sector_count * 0x10000;
+	}
+	else {
+		printf ("## Unknown Flash Type: %02x\n", devid);
+		return 0;
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* sector base address */
+		info->start[i] = base + i * (info->size / info->sector_count);
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr = (volatile unsigned char *)(info->start[i]);
+		info->protect[i] = addr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		addr = (vu_char *)info->start[0];
+		addr[0] = 0xF0; /* reset bank */
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+	unsigned long size_b0 = 0;
+	unsigned long size_b1 = 0;
+	int i;
+
+	/* Init: no FLASHes known
+	 */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Disable flash protection */
+	CPU86_BCR |= (CPU86_BCR_FWPT | CPU86_BCR_FWRE);
+
+	/* Static FLASH Bank configuration here (only one bank) */
+
+	size_b0 = flash_int_get_size ((ulong *) CFG_FLASH_BASE, &flash_info[0]);
+	size_b1 = flash_amd_get_size ((uchar *) CFG_BOOTROM_BASE, &flash_info[1]);
+
+	if (size_b0 > 0 || size_b1 > 0) {
+
+		printf("(");
+
+		if (size_b0 > 0) {
+			puts ("Bank#1 - ");
+			print_size (size_b0, (size_b1 > 0) ? ", " : ") ");
+		}
+
+		if (size_b1 > 0) {
+			puts ("Bank#2 - ");
+			print_size (size_b1, ") ");
+		}
+	}
+	else {
+		printf ("## No FLASH found.\n");
+		return 0;
+	}
+	/* protect monitor and environment sectors
+	 */
+
+#if CFG_MONITOR_BASE >= CFG_BOOTROM_BASE
+	if (size_b1) {
+		/* If U-Boot is booted from ROM the CFG_MONITOR_BASE > CFG_FLASH_BASE
+		 * but we shouldn't protect it.
+		 */
+
+		flash_protect  (FLAG_PROTECT_SET,
+				CFG_MONITOR_BASE,
+				CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1]
+		);
+	}
+#else
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_MONITOR_BASE,
+		       CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]
+	);
+#endif
+#endif
+
+#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
+# ifndef  CFG_ENV_SIZE
+#  define CFG_ENV_SIZE	CFG_ENV_SECT_SIZE
+# endif
+# if CFG_ENV_ADDR >= CFG_BOOTROM_BASE
+	if (size_b1) {
+		flash_protect (FLAG_PROTECT_SET,
+				CFG_ENV_ADDR,
+				CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[1]);
+	}
+# else
+	flash_protect (FLAG_PROTECT_SET,
+		       CFG_ENV_ADDR,
+		       CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+# endif
+#endif
+
+	return (size_b0 + size_b1);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch ((info->flash_id >> 16) & 0xff) {
+	case 0x89:
+		printf ("INTEL ");
+		break;
+	case 0x1:
+		printf ("AMD ");
+		break;
+	default:
+		printf ("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F160C3B:
+		printf ("28F160C3B (16 Mbit, bottom sector)\n");
+		break;
+	case FLASH_28F160F3B:
+		printf ("28F160F3B (16 Mbit, bottom sector)\n");
+		break;
+	case FLASH_28F640C3B:
+		printf ("28F640C3B (64 M, bottom sector)\n");
+		break;
+	case AMD_ID_F040B:
+		printf ("AM29F040B (4 Mbit)\n");
+		break;
+	default:
+		printf ("Unknown Chip Type\n");
+		break;
+	}
+
+	if (info->size < 0x100000)
+		printf ("  Size: %ld KB in %d Sectors\n",
+				info->size >> 10, info->sector_count);
+	else
+		printf ("  Size: %ld MB in %d Sectors\n",
+				info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+	vu_char *addr = (vu_char *)(info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n",
+				prot);
+	} else {
+		printf ("\n");
+	}
+
+	/* Check the type of erased flash
+	 */
+	if (info->flash_id >> 16 == 0x1) {
+		/* Erase AMD flash
+		 */
+		l_sect = -1;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr[0x0555] = 0xAA;
+		addr[0x02AA] = 0x55;
+		addr[0x0555] = 0x80;
+		addr[0x0555] = 0xAA;
+		addr[0x02AA] = 0x55;
+
+		/* wait at least 80us - let's wait 1 ms */
+		udelay (1000);
+
+		/* Start erase on unprotected sectors */
+		for (sect = s_first; sect<=s_last; sect++) {
+			if (info->protect[sect] == 0) { /* not protected */
+				addr = (vu_char *)(info->start[sect]);
+				addr[0] = 0x30;
+				l_sect = sect;
+			}
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* wait at least 80us - let's wait 1 ms */
+		udelay (1000);
+
+		/*
+		 * We wait for the last triggered sector
+		 */
+		if (l_sect < 0)
+			goto AMD_DONE;
+
+		start = get_timer (0);
+		last  = start;
+		addr = (vu_char *)(info->start[l_sect]);
+		while ((addr[0] & 0x80) != 0x80) {
+			if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				printf ("Timeout\n");
+				return 1;
+			}
+			/* show that we're waiting */
+			if ((now - last) > 1000) {      /* every second */
+				serial_putc ('.');
+				last = now;
+			}
+		}
+
+AMD_DONE:
+		/* reset to read mode */
+		addr = (volatile unsigned char *)info->start[0];
+		addr[0] = 0xF0;     /* reset bank */
+
+	} else {
+		/* Erase Intel flash
+		 */
+
+		/* Start erase on unprotected sectors
+		 */
+		for (sect = s_first; sect <= s_last; sect++) {
+			volatile ulong *addr =
+				(volatile unsigned long *) info->start[sect];
+
+			start = get_timer (0);
+			last = start;
+			if (info->protect[sect] == 0) {
+			/* Disable interrupts which might cause a timeout here
+			 */
+				flag = disable_interrupts ();
+
+				/* Erase the block
+				 */
+				addr[0] = 0x00200020;
+				addr[1] = 0x00200020;
+				addr[0] = 0x00D000D0;
+				addr[1] = 0x00D000D0;
+
+				/* re-enable interrupts if necessary
+				 */
+				if (flag)
+					enable_interrupts ();
+
+				/* wait at least 80us - let's wait 1 ms
+				 */
+				udelay (1000);
+
+				last = start;
+				while ((addr[0] & 0x00800080) != 0x00800080 ||
+				   (addr[1] & 0x00800080) != 0x00800080) {
+					if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+						printf ("Timeout (erase suspended!)\n");
+						/* Suspend erase
+						 */
+						addr[0] = 0x00B000B0;
+						addr[1] = 0x00B000B0;
+						goto DONE;
+					}
+					/* show that we're waiting
+					 */
+					if ((now - last) > 1000) {	/* every second */
+						serial_putc ('.');
+						last = now;
+					}
+				}
+				if (addr[0] & 0x00220022 || addr[1] & 0x00220022) {
+					printf ("*** ERROR: erase failed!\n");
+					goto DONE;
+				}
+			}
+			/* Clear status register and reset to read mode
+			 */
+			addr[0] = 0x00500050;
+			addr[1] = 0x00500050;
+			addr[0] = 0x00FF00FF;
+			addr[1] = 0x00FF00FF;
+		}
+	}
+
+	printf (" done\n");
+
+DONE:
+	return 0;
+}
+
+static int write_word (flash_info_t *, volatile unsigned long *, ulong);
+static int write_byte (flash_info_t *info, ulong dest, uchar data);
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong v;
+	int i, l, rc, cc = cnt, res = 0;
+
+	if (info->flash_id >> 16 == 0x1) {
+
+		/* Write to AMD 8-bit flash
+		 */
+		while (cnt > 0) {
+			if ((rc = write_byte(info, addr, *src)) != 0) {
+				return (rc);
+			}
+			addr++;
+			src++;
+			cnt--;
+		}
+
+		return (0);
+	} else {
+
+		/* Write to Intel 64-bit flash
+		 */
+		for (v=0; cc > 0; addr += 4, cc -= 4 - l) {
+			l = (addr & 3);
+			addr &= ~3;
+
+			for (i = 0; i < 4; i++) {
+				v = (v << 8) + (i < l || i - l >= cc ?
+					*((unsigned char *) addr + i) : *src++);
+			}
+
+			if ((res = write_word (info, (volatile unsigned long *) addr, v)) != 0)
+				break;
+		}
+	}
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t * info, volatile unsigned long *addr,
+					   ulong data)
+{
+	int flag, res = 0;
+	ulong start;
+
+	/* Check if Flash is (sufficiently) erased
+	 */
+	if ((*addr & data) != data)
+		return (2);
+
+	/* Disable interrupts which might cause a timeout here
+	 */
+	flag = disable_interrupts ();
+
+	*addr = 0x00400040;
+	*addr = data;
+
+	/* re-enable interrupts if necessary
+	 */
+	if (flag)
+		enable_interrupts ();
+
+	start = get_timer (0);
+	while ((*addr & 0x00800080) != 0x00800080) {
+		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			/* Suspend program
+			 */
+			*addr = 0x00B000B0;
+			res = 1;
+			goto OUT;
+		}
+	}
+
+	if (*addr & 0x00220022) {
+		printf ("*** ERROR: program failed!\n");
+		res = 1;
+	}
+
+OUT:
+	/* Clear status register and reset to read mode
+	 */
+	*addr = 0x00500050;
+	*addr = 0x00FF00FF;
+
+	return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a byte to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_byte (flash_info_t *info, ulong dest, uchar data)
+{
+	vu_char *addr = (vu_char *)(info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_char *)dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0xA0;
+
+	*((vu_char *)dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer (0);
+	while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */

board/cpu87/u-boot.lds

@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2001-2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    common/environment.o(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

board/cradle/Makefile

@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	:= cradle.o flash.o
-SOBJS	:= memsetup.o
+SOBJS	:= lowlevel_init.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)

board/cradle/lowlevel_init.S

@@ -43,8 +43,8 @@ DRAM_SIZE:  .long   CFG_DRAM_SIZE
    .endm
 
 
-.globl memsetup
-memsetup:
+.globl lowlevel_init
+lowlevel_init:
 
     mov      r10, lr
 
@@ -512,4 +512,4 @@ mem_init:
 
    mov   pc, r10
 
-@ End memsetup
+@ End lowlevel_init

board/csb226/Makefile

@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	:= csb226.o flash.o
-SOBJS	:= memsetup.o
+SOBJS	:= lowlevel_init.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)

board/csb226/lowlevel_init.S

@@ -3,7 +3,7 @@
  *
  * NOTE: I haven't clean this up considerably, just enough to get it
  * running. See hal_platform_setup.h for the source. See
- * board/cradle/memsetup.S for another PXA250 setup that is
+ * board/cradle/lowlevel_init.S for another PXA250 setup that is
  * much cleaner.
  *
  * See file CREDITS for list of people who contributed to this
@@ -46,8 +46,8 @@ _TEXT_BASE:
  * 	Memory setup
  */
 
-.globl memsetup
-memsetup:
+.globl lowlevel_init
+lowlevel_init:
 
     mov      r10, lr
 
@@ -429,9 +429,9 @@ initclks:
 #endif
 
 	/* ---------------------------------------------------------------- */
-	/* End memsetup                                                     */
+	/* End lowlevel_init                                                     */
 	/* ---------------------------------------------------------------- */
 
-endmemsetup:
+endlowlevel_init:
 
     mov     pc, lr

board/csb472/init.S

@@ -129,7 +129,7 @@ ext_bus_cntlr_init:
 	 *******************************************************************/
 	/*WDCR_EBC(pb3ap, 0x07869200)*/
 	WDCR_EBC(pb3ap, 0x04055200)
-	WDCR_EBC(pb3cr, 0xff01c000)
+	WDCR_EBC(pb3cr, 0xf081c000)
 	/********************************************************************
 	 * Memory Bank 1,2,4-7 (Unused) initialization
 	 *******************************************************************/

board/dave/B2/Makefile

@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	:= B2.o flash.o
-SOBJS	:= memsetup.o
+SOBJS	:= lowlevel_init.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)

board/dave/B2/lowlevel_init.S

@@ -149,8 +149,8 @@ MEMORY_CONFIG:
   .word 0x20      /*MRSR7*/
 
 
-.globl memsetup
-memsetup:
+.globl lowlevel_init
+lowlevel_init:
 
 	/*
 		the next instruction fail due memory relocation...

board/dave/PPChameleonEVB/u-boot.lds

@@ -140,6 +140,7 @@ SECTIONS
    *(COMMON)
   }
 
+  ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
   . = 0xFFFF8000;
   .ppcenv :
   {

board/dbau1x00/Makefile

@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	= $(BOARD).o flash.o
-SOBJS	= memsetup.o
+SOBJS	= lowlevel_init.o
 
 $(LIB):	.depend $(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)

board/dbau1x00/dbau1x00.c

@@ -30,7 +30,7 @@ long int initdram(int board_type)
 {
 	/* Sdram is setup by assembler code */
 	/* If memory could be changed, we should return the true value here */
-	return 64*1024*1024;
+	return MEM_SIZE*1024*1024;
 }
 
 #define BCSR_PCMCIA_PC0DRVEN		0x0010
@@ -41,9 +41,11 @@ void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
 
 int checkboard (void)
 {
+#ifdef CONFIG_IDE_PCMCIA
 	u16 status;
-	volatile u32 *pcmcia_bcsr = (u32*)(DB1000_BCSR_ADDR+0x10);
-	volatile u32 *phy = (u32*)(DB1000_BCSR_ADDR+0xC);
+	volatile u32 *pcmcia_bcsr = (u32*)(DB1XX0_BCSR_ADDR+0x10);
+#endif	/* CONFIG_IDE_PCMCIA */
+	volatile u32 *phy = (u32*)(DB1XX0_BCSR_ADDR+0xC);
 	volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
 	u32 proc_id;
 
@@ -67,6 +69,11 @@ int checkboard (void)
 		printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n",
 			(proc_id >> 8) & 0xFF, proc_id & 0xFF);
 		break;
+	case 3:
+		puts ("Board: DbAu1550\n");
+		printf ("CPU: Au1550, id: 0x%02x, rev: 0x%02x\n",
+			(proc_id >> 8) & 0xFF, proc_id & 0xFF);
+		break;
 	default:
 		printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
 	}

board/dbau1x00/lowlevel_init.S

@@ -9,20 +9,34 @@
 #define AU1500_SYS_ADDR		0xB1900000
 #define sys_endian		0x0038
 #define CP0_Config0		$16
-#define MEM_1MS			((396000000/1000000) * 1000)
+#define CPU_SCALE		((CFG_MHZ) / 12) /* CPU clock is a multiple of 12 MHz */
+#define MEM_1MS			((CFG_MHZ) * 1000)
 
 	.text
 	.set noreorder
 	.set mips32
 
-	.globl	memsetup
-memsetup:
+	.globl	lowlevel_init
+lowlevel_init:
 	/*
 	 * Step 1) Establish CPU endian mode.
 	 * Db1500-specific:
 	 * Switch S1.1 Off(bit7 reads 1) is Little Endian
 	 * Switch S1.1 On (bit7 reads 0) is Big Endian
 	 */
+#ifdef CONFIG_DBAU1550
+	li	t0, MEM_STCFG2
+	li	t1, 0x00000040
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME2
+	li	t1, 0x22080a20
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR2
+	li	t1, 0x10c03f00
+	sw	t1, 0(t0)
+#else
 	li	t0, MEM_STCFG1
 	li	t1, 0x00000080
 	sw	t1, 0(t0)
@@ -34,9 +48,10 @@ memsetup:
 	li	t0, MEM_STADDR1
 	li	t1, 0x10c03f00
 	sw	t1, 0(t0)
+#endif
 
-	li	t0, 0xAE000008
-	lw	t1,0(t0)
+	li	t0, DB1XX0_BCSR_ADDR
+	lw	t1,8(t0)
 	andi	t1,t1,0x80
 	beq	zero,t1,big_endian
 	nop
@@ -98,10 +113,82 @@ big_endian:
 	mtc0	zero, CP0_WIRED
 	nop
 
+#ifdef CONFIG_DBAU1550
+	/* No workaround if running from ram */
+	lui	t0, 0xffc0
+	lui	t3, 0xbfc0
+	and	t1, ra, t0
+	bne	t1, t3, noCacheJump
+	nop
+
+	/*** From AMD YAMON ***/
+	/*
+	 * Step 8) Initialize the caches
+	 */
+	li		t0, (16*1024)
+	li		t1, 32
+	li		t2, 0x80000000
+	addu	t3, t0, t2
+cacheloop:
+	cache	0, 0(t2)
+	cache	1, 0(t2)
+	addu	t2, t1
+	bne		t2, t3, cacheloop
+	nop
+
+	/* Save return address */
+	move		t3, ra
+
+	/* Run from cacheable space now */
+	bal		cachehere
+	nop
+cachehere:
+	li		t1, ~0x20000000 /* convert to KSEG0 */
+	and		t0, ra, t1
+	addi	t0, 5*4			/* 5 insns beyond cachehere */
+	jr		t0
+	nop
+
+	/* Restore return address */
+	move		ra, t3
+
+	/*
+	 * Step 9) Initialize the TLB
+	 */
+	li		t0, 0			# index value
+	li		t1, 0x00000000		# entryhi value
+	li		t2, 32			# 32 entries
+
+tlbloop:
+	/* Probe TLB for matching EntryHi */
+	mtc0	t1, CP0_ENTRYHI
+	tlbp
+	nop
+
+	/* Examine Index[P], 1=no matching entry */
+	mfc0	t3, CP0_INDEX
+	li	t4, 0x80000000
+	and	t3, t4, t3
+	addiu	t1, t1, 1		# increment t1 (asid)
+	beq	zero, t3, tlbloop
+	nop
+
+	/* Initialize the TLB entry */
+	mtc0	t0, CP0_INDEX
+	mtc0	zero, CP0_ENTRYLO0
+	mtc0	zero, CP0_ENTRYLO1
+	mtc0	zero, CP0_PAGEMASK
+	tlbwi
+
+	/* Do it again */
+	addiu	t0, t0, 1
+	bne	t0, t2, tlbloop
+	nop
+
 	/* First setup pll:s to make serial work ok */
 	/* We have a 12 MHz crystal */
 	li	t0, SYS_CPUPLL
-	li	t1, 0x21  /* 396 MHz */
+	li	t1, CPU_SCALE  /* CPU clock */
 	sw	t1, 0(t0)
 	sync
 	nop
@@ -119,19 +206,49 @@ big_endian:
 	sync
 
 	/*  Static memory controller */
+	/* RCE0 - can not change while fetching, do so from icache */
+	move		t2, ra /* Store return address */
+	bal		getAddr
+	nop
+
+getAddr:
+	move		t1, ra
+	move		ra, t2 /* Move return addess back */
+
+	cache	0x14,0(t1)
+	cache	0x14,32(t1)
+	/*** /From YAMON ***/
+
+noCacheJump:
+#endif /* CONFIG_DBAU1550 */
+
+#ifdef CONFIG_DBAU1550
+	li	t0, MEM_STTIME0
+	li	t1, 0x040181D7
+	sw	t1, 0(t0)
+
+	/* RCE0 AMD MirrorBit Flash (?) */
+	li	t0, MEM_STCFG0
+	li	t1, 0x00000003
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR0
+	li	t1, 0x11803E00
+	sw	t1, 0(t0)
+#else /* CONFIG_DBAU1550 */
+	li	t0, MEM_STTIME0
+	li	t1, 0x00014C0F
+	sw	t1, 0(t0)
 
 	/* RCE0 AMD 29LV640M MirrorBit Flash */
 	li	t0, MEM_STCFG0
 	li	t1, 0x00000013
 	sw	t1, 0(t0)
 
-	li	t0, MEM_STTIME0
-	li	t1, 0x040181D7
-	sw	t1, 0(t0)
-
 	li	t0, MEM_STADDR0
 	li	t1, 0x11E03F80
 	sw	t1, 0(t0)
+#endif /* CONFIG_DBAU1550 */
 
 	/* RCE1 CPLD Board Logic */
 	li	t0, MEM_STCFG1
@@ -146,7 +263,20 @@ big_endian:
 	li	t1, 0x10c03f00
 	sw	t1, 0(t0)
 
+#ifdef CONFIG_DBAU1550
 	/* RCE2 CPLD Board Logic */
+	li	t0, MEM_STCFG2
+	li	t1, 0x00000040
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STTIME2
+	li	t1, 0x22080a20
+	sw	t1, 0(t0)
+
+	li	t0, MEM_STADDR2
+	li	t1, 0x10c03f00
+	sw	t1, 0(t0)
+#else
 	li	t0, MEM_STCFG2
 	li	t1, 0x00000000
 	sw	t1, 0(t0)
@@ -158,6 +288,7 @@ big_endian:
 	li	t0, MEM_STADDR2
 	li	t1, 0x00000000
 	sw	t1, 0(t0)
+#endif
 
 	/* RCE3 PCMCIA 250ns */
 	li	t0, MEM_STCFG3
@@ -281,6 +412,99 @@ big_endian:
 	bne	t1, zero, 1b
 	nop
 
+#ifdef CONFIG_DBAU1550
+/* SDCS 0,1,2 DDR SDRAM */
+	li	t0, MEM_SDMODE0
+	li	t1, 0x04276221
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDMODE1
+	li	t1, 0x04276221
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDMODE2
+	li	t1, 0x04276221
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDADDR0
+	li	t1, 0xe21003f0
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDADDR1
+	li	t1, 0xe21043f0
+	sw	t1, 0(t0)
+
+	li	t0, MEM_SDADDR2
+	li	t1, 0xe21083f0
+	sw	t1, 0(t0)
+
+	sync
+
+	li	t0, MEM_SDCONFIGA
+	li	t1, 0x9030060a /* Program refresh - disabled */
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDCONFIGB
+	li	t1, 0x00028000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDPRECMD /* Precharge all */
+	li	t1, 0
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD0
+	li	t1, 0x40000000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD1
+	li	t1, 0x40000000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD2
+	li	t1, 0x40000000
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD0
+	li	t1, 0x00000063
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD1
+	li	t1, 0x00000063
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDWRMD2
+	li	t1, 0x00000063
+	sw	t1, 0(t0)
+	sync
+
+	li	t0, MEM_SDPRECMD /* Precharge all */
+	sw	zero, 0(t0)
+	sync
+
+	/* Issue 2 autoref */
+	li	t0, MEM_SDAUTOREF
+	sw	zero, 0(t0)
+	sync
+
+	li	t0, MEM_SDAUTOREF
+	sw	zero, 0(t0)
+	sync
+
+	/* Enable refresh */
+	li	t0, MEM_SDCONFIGA
+	li	t1, 0x9830060a /* Program refresh - enabled */
+	sw	t1, 0(t0)
+	sync
+
+#else /* CONFIG_DBAU1550 */
 /* SDCS 0,1 SDRAM */
 	li	t0, MEM_SDMODE0
 	li	t1, 0x005522AA
@@ -339,6 +563,7 @@ big_endian:
 	sw	t1, 0(t0)
 	sync
 
+#endif /* CONFIG_DBAU1550 */
 	/* wait 1mS after setup */
 	li	t1, MEM_1MS
 1:	add	t1, -1

board/dnp1110/Makefile

@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	:= dnp1110.o flash.o
-SOBJS	:= memsetup.o
+SOBJS	:= lowlevel_init.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)

board/dnp1110/lowlevel_init.S

@@ -63,8 +63,8 @@ smcnfg:		.long	0x00000000
 
 /* setting up the memory */
 
-.globl memsetup
-memsetup:
+.globl lowlevel_init
+lowlevel_init:
 
 	ldr	r0, MEM_BASE
 

board/ep7312/Makefile

@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	:= ep7312.o flash.o
-SOBJS	:= memsetup.o
+SOBJS	:= lowlevel_init.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)

board/ep7312/lowlevel_init.S

@@ -45,8 +45,8 @@ sdrfpr_val:	.long	0x00000240
 sdconf_val:	.long	0x00000522
 /* setting up the memory */
 
-.globl memsetup
-memsetup:
+.globl lowlevel_init
+lowlevel_init:
 	/*
 	 * SYSCON1-3
 	 */

board/ep8260/ep8260.c

@@ -227,6 +227,10 @@ int checkboard (void)
 		major = 1;
 		minor = 1;
 		break;
+	case 0x06:
+		major = 1;
+		minor = 3;
+		break;
 	default:
 		break;
 	}

board/ep8260/flash.c

@@ -81,15 +81,28 @@ ulong flash_get_size( ulong baseaddr, flash_info_t *info )
 		info->flash_id = FLASH_UNKNOWN;
 		return(0);
 	}
-  if (flashtest_h == AMD_ID_DL323B) {
+
+	switch((int)flashtest_h) {
+	case AMD_ID_DL323B:
 		info->flash_id += FLASH_AMDL323B;
 		info->sector_count = 71;
 		info->size = 0x01000000;	 /* 4 * 4 MB = 16 MB	*/
-  } else {
+		break;
+	case AMD_ID_LV640U:	/* AMDLV640 and AMDLV641 have same ID */
+		info->flash_id += FLASH_AMLV640U;
+		info->sector_count = 128;
+		info->size = 0x02000000; 	/* 4 * 8 MB = 32 MB	*/
+		break;
+	default:
 		info->flash_id = FLASH_UNKNOWN;
 		return(0);  			 	/* no or unknown flash	   */
 	}
 
+	if(flashtest_h == AMD_ID_LV640U) {
+		/* set up sector start adress table (uniform sector type) */
+		for (i = 0; i < info->sector_count; i++)
+			info->start[i] = baseaddr + (i * 0x00040000);
+	} else {
 		/* set up sector start adress table (bottom sector type) */
 		for (i = 0; i < 8; i++) {
 			info->start[i] = baseaddr + (i * 0x00008000);
@@ -97,7 +110,7 @@ ulong flash_get_size( ulong baseaddr, flash_info_t *info )
 		for (i = 8; i < info->sector_count; i++) {
 			info->start[i] = baseaddr + (i * 0x00040000) - 0x001C0000;
 		}
-
+	}
 	/* check for protected sectors */
 	for (i = 0; i < info->sector_count; i++) {
 		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
@@ -176,6 +189,8 @@ void flash_print_info  (flash_info_t *info)
 	switch (info->flash_id & FLASH_TYPEMASK) {
 	case FLASH_AMDL323B:	printf ("29DL323B (32 M, bottom sector)\n");
 				break;
+	case FLASH_AMLV640U:	printf ("29LV640U (64 M, uniform sector)\n");
+				break;
 	default:		printf ("Unknown Chip Type\n");
 				break;
 	}

board/esd/apc405/apc405.c

@@ -63,10 +63,56 @@ unsigned char logo_bmp[] =
  */
 #include "../common/lcd.c"
 
-#include "../common/"CFG_LCD_HEADER_NAME
+#include CFG_LCD_HEADER_NAME
 #endif /* CONFIG_LCD_USED */
 
 
+int board_revision(void)
+{
+	unsigned long cntrl0Reg;
+	unsigned long value;
+
+	/*
+	 * Get version of APC405 board from GPIO's
+	 */
+
+	/*
+	 * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
+	 */
+	cntrl0Reg = mfdcr(cntrl0);
+	mtdcr(cntrl0, cntrl0Reg | 0x03000000);
+	out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000);
+	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000);
+	udelay(1000);                   /* wait some time before reading input */
+	value = in32(GPIO0_IR) & 0x00180000;       /* get config bits */
+
+	/*
+	 * Restore GPIO settings
+	 */
+	mtdcr(cntrl0, cntrl0Reg);
+
+	switch (value) {
+	case 0x00180000:
+		/* CS2==1 && CS3==1 -> version <= 1.2 */
+		return 2;
+	case 0x00080000:
+		/* CS2==0 && CS3==1 -> version 1.3 */
+		return 3;
+#if 0 /* not yet manufactured ! */
+	case 0x00100000:
+		/* CS2==1 && CS3==0 -> version 1.4 */
+		return 4;
+	case 0x00000000:
+		/* CS2==0 && CS3==0 -> version 1.5 */
+		return 5;
+#endif
+	default:
+		/* should not be reached! */
+		return 0;
+	}
+}
+
+
 int board_early_init_f (void)
 {
 	/*
@@ -120,8 +166,12 @@ int misc_init_f (void)
 
 int misc_init_r (void)
 {
+	DECLARE_GLOBAL_DATA_PTR;
+
 	volatile unsigned short *fpga_mode =
 		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+	volatile unsigned short *fpga_ctrl2 =
+		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL2);
 	volatile unsigned char *duart0_mcr =
 		(unsigned char *)((ulong)DUART0_BA + 4);
 	volatile unsigned char *duart1_mcr =
@@ -204,6 +254,11 @@ int misc_init_r (void)
 	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
 	udelay(1000); /* wait 1ms */
 
+	/*
+	 * Write board revision in FPGA
+	 */
+	*fpga_ctrl2 = (*fpga_ctrl2 & 0xfff0) | (gd->board_type & 0x000f);
+
 	/*
 	 * Enable power on PS/2 interface (with reset)
 	 */
@@ -228,8 +283,11 @@ int misc_init_r (void)
 		 logo_bmp, sizeof(logo_bmp));
 
 	/*
-	 * Enable microcontroller and setup backlight PWM controller
+	 * Reset microcontroller and setup backlight PWM controller
 	 */
+	*fpga_mode |= 0x0014;
+	for (i=0;i<10;i++)
+		udelay(1000);
 	*fpga_mode |= 0x001c;
 	*fuji_lcdbl_pwm = 0x00ff;
 
@@ -243,6 +301,8 @@ int misc_init_r (void)
 
 int checkboard (void)
 {
+	DECLARE_GLOBAL_DATA_PTR;
+
 	unsigned char str[64];
 	int i = getenv_r ("serial#", str, sizeof(str));
 
@@ -254,7 +314,8 @@ int checkboard (void)
 		puts(str);
 	}
 
-	putc ('\n');
+	gd->board_type = board_revision();
+	printf(", Rev 1.%ld\n", gd->board_type);
 
 	/*
 	 * Disable sleep mode in LXT971

board/esd/common/auto_update.c

@@ -224,6 +224,25 @@ int au_do_update(int i, long sz)
 		start = au_image[i].start;
 		end = au_image[i].start + au_image[i].size - 1;
 
+		/*
+		 * do not update firmware when image is already in flash.
+		 */
+		if (au_image[i].type == AU_FIRMWARE) {
+			char *orig = (char*)start;
+			char *new  = (char *)((char *)hdr + sizeof(*hdr));
+			nbytes = ntohl(hdr->ih_size);
+
+			while(--nbytes) {
+				if (*orig++ != *new++) {
+					break;
+				}
+			}
+			if (!nbytes) {
+				printf("Skipping firmware update - images are identical\n");
+				break;
+			}
+		}
+
 		/* unprotect the address range */
 		/* this assumes that ONLY the firmware is protected! */
 		if (au_image[i].type == AU_FIRMWARE) {

board/esd/hh405/logo_320_240_4bpp.c

@@ -1,292 +1,227 @@
-  0x1f,0x8b,0x08,0x08,0xaf,0xaf,0x9c,0x41,0x00,0x03,0x65,0x73,0x64,0x5f,0x77,0x65,
-  0x6c,0x6c,0x65,0x5f,0x6d,0x6f,0x6e,0x69,0x74,0x6f,0x72,0x2d,0x62,0x6c,0x61,0x75,
-  0x5f,0x33,0x32,0x30,0x5f,0x32,0x34,0x30,0x5f,0x34,0x62,0x70,0x70,0x2e,0x62,0x6d,
-  0x70,0x00,0xe5,0x9d,0x0f,0x6c,0xa3,0x65,0x1d,0xc7,0x5f,0xfe,0x48,0xf0,0x0f,0xcb,
-  0x4d,0x41,0x18,0x35,0x0e,0x0b,0x92,0xaa,0x0c,0xc1,0xe6,0x82,0xd4,0x9a,0xe2,0x59,
-  0x64,0x58,0x10,0x2e,0xa6,0x21,0x25,0xc3,0x21,0x92,0x9d,0x09,0x6e,0xca,0x8d,0xa3,
-  0xb1,0x0e,0x5f,0x9c,0x23,0xd6,0x68,0x90,0x02,0x13,0xcb,0x81,0xa7,0x16,0x18,0xa9,
-  0x78,0xb2,0xd0,0x44,0x49,0x0d,0x07,0x8e,0x72,0x9c,0x36,0x39,0x9c,0x30,0x13,0xb1,
-  0xb0,0xa0,0x4e,0x24,0x3a,0xbd,0xeb,0xcd,0xf7,0xd6,0xdb,0xf1,0xfa,0xfb,0xf3,0xbc,
-  0x6f,0xdf,0x6e,0xf7,0xde,0xed,0x69,0xdf,0xb7,0x6f,0x8d,0xdf,0x5b,0xef,0x2e,0x77,
-  0x79,0xde,0x7d,0xf6,0xfd,0xfd,0x79,0x9e,0xf7,0xe9,0xfb,0xbe,0xdd,0x74,0xe5,0xad,
-  0xdf,0x57,0x48,0xb7,0xc2,0x2b,0x00,0xaf,0x4b,0x8e,0x53,0x94,0x7f,0xc3,0x9f,0xc7,
-  0x29,0x27,0xf2,0x7f,0xc0,0xff,0x9f,0x7d,0x3e,0xbf,0x36,0xf0,0xbf,0x28,0x89,0x44,
-  0x42,0x79,0xe2,0x89,0x27,0x94,0x74,0x3a,0xad,0xbc,0xf2,0xca,0x2b,0xca,0x83,0x0f,
-  0x3e,0xa8,0xec,0xd9,0xb3,0x47,0xd9,0xba,0x75,0xab,0xb2,0x7f,0xff,0x7e,0xe5,0xee,
-  0xbb,0xef,0x56,0x9e,0x7a,0xea,0x29,0xe5,0x8d,0x37,0xde,0x50,0x1e,0x7d,0xf4,0x51,
-  0xe5,0xc5,0x17,0x5f,0x54,0x6e,0xbb,0xed,0x36,0x65,0xcb,0x96,0x2d,0xca,0xe1,0xc3,
-  0x87,0x15,0xdd,0x39,0x25,0x83,0xa5,0x4c,0x77,0x61,0x93,0x7f,0x68,0x68,0x68,0xe4,
-  0x9f,0xdf,0x18,0x08,0xfe,0xdc,0xc1,0x63,0xb7,0xa8,0xd1,0x92,0x2f,0xda,0x77,0x2e,
-  0x82,0x2d,0xa2,0x5e,0x3b,0xad,0x83,0xd8,0x52,0x1b,0xb7,0x6f,0xea,0xab,0xcc,0xcd,
-  0x01,0xdd,0x02,0x68,0x71,0x71,0xe1,0x0e,0xa6,0xd3,0x34,0x4d,0x57,0xbd,0x65,0xd3,
-  0x53,0xa5,0x53,0xc7,0xfb,0x2a,0x95,0xca,0x30,0x08,0xed,0x1b,0x19,0x59,0x7c,0xed,
-  0x7e,0x82,0xd3,0x55,0x55,0x57,0x01,0x31,0xe9,0x1d,0x9c,0xb6,0xf1,0x5e,0xbf,0xbf,
-  0xaf,0x6f,0x16,0xf8,0xc0,0x3f,0x30,0x70,0x64,0x68,0x61,0xf1,0x8b,0x7b,0x99,0x0e,
-  0x01,0x35,0x35,0xe9,0x1d,0x60,0x6d,0x73,0xff,0x38,0xe0,0xf9,0x67,0x89,0x8f,0xec,
-  0x03,0xc2,0x1b,0x23,0x26,0x9e,0xa6,0xa9,0xaa,0x9a,0x4c,0x7a,0x03,0x58,0xdd,0xbc,
-  0x29,0xed,0xf7,0x23,0x20,0x19,0x38,0xcc,0xfe,0x8d,0xdc,0x00,0xee,0x51,0x60,0xe1,
-  0x77,0x84,0x4b,0xe2,0x2b,0xa9,0xb6,0x9b,0x0e,0xbc,0x4b,0xa7,0xc7,0xc7,0x01,0xcf,
-  0x6f,0xf8,0x47,0x80,0xc3,0xf7,0x21,0x9a,0x26,0x94,0x14,0xfe,0x25,0xdb,0xed,0xe0,
-  0xc5,0xd1,0x34,0x2a,0x10,0xa0,0xf8,0x56,0xfa,0x8c,0xfc,0x1b,0xba,0x8c,0x0b,0x03,
-  0xe1,0x04,0x19,0x6b,0xaa,0x9d,0x74,0xa3,0xf7,0x4e,0x4c,0x4c,0xa4,0xd1,0xbf,0x00,
-  0x04,0x78,0xb6,0xcf,0x5f,0xe1,0x04,0x1c,0x1e,0x7a,0xc9,0x80,0x13,0x78,0xaa,0x81,
-  0x97,0x6c,0x5f,0x3f,0xd4,0x2e,0x8c,0x46,0xa3,0x13,0xe4,0x1f,0x02,0xfa,0xd1,0x3f,
-  0x68,0x7f,0x15,0xa8,0x8f,0x9b,0x54,0xdd,0x84,0x33,0xd9,0x92,0xc9,0x14,0x4a,0x6d,
-  0x13,0xde,0x98,0x0f,0xf1,0x26,0x26,0xfa,0x31,0xbc,0x88,0x87,0x05,0x82,0xf1,0x85,
-  0x5f,0xd7,0xe8,0x9a,0x51,0x17,0x6a,0x1d,0x2f,0x39,0x45,0x80,0xed,0xc1,0xdb,0x58,
-  0x04,0xbc,0x68,0x7f,0x7f,0x3f,0xfb,0x87,0x05,0x32,0xdb,0x27,0x1a,0xcc,0xd9,0xc8,
-  0x46,0x49,0x67,0xa5,0x23,0xb8,0x54,0x3e,0xdf,0x8e,0x1a,0xd1,0x9e,0x29,0x80,0xc0,
-  0xbf,0x68,0x1a,0xeb,0x37,0x8d,0xf9,0x87,0x80,0x88,0x57,0xb9,0x51,0x25,0x25,0x39,
-  0xbc,0x26,0xde,0x14,0x2a,0x0f,0x84,0xaa,0xfb,0x78,0x9b,0x8b,0x31,0xc4,0x43,0xff,
-  0xfa,0x4d,0xff,0xc4,0x04,0x32,0x7c,0x3a,0xa0,0x59,0xc9,0xc8,0xbb,0x3c,0x79,0x97,
-  0x9f,0xc2,0x97,0xdb,0x78,0xd5,0xed,0xc5,0x58,0x31,0x16,0x65,0x40,0xaa,0x90,0x80,
-  0x9f,0x0a,0x84,0x12,0xf0,0x25,0x61,0x9c,0xa6,0x59,0x43,0x9b,0x04,0xef,0xd0,0x3f,
-  0x94,0xea,0x32,0x5e,0xa6,0x58,0x2c,0xc6,0x62,0x31,0xae,0x0f,0xb6,0xcf,0xe2,0xdf,
-  0x6e,0x04,0x6b,0x28,0x8b,0x3c,0x27,0x1e,0xc3,0xb9,0x6e,0x60,0x75,0xbb,0x0f,0xf8,
-  0x8a,0x85,0x02,0x01,0x72,0x80,0x8d,0x0a,0x06,0xc0,0xf3,0x68,0xba,0xb0,0xc4,0x36,
-  0x4f,0xde,0xe5,0x53,0x26,0x5e,0x28,0xa4,0xba,0x89,0x97,0xf1,0xf9,0x00,0xb0,0x50,
-  0x8c,0x59,0x0a,0x98,0xf0,0xfa,0xb0,0xc1,0xcc,0xee,0xb6,0x4e,0x17,0x98,0x78,0xc9,
-  0xa9,0x7c,0xdd,0xbb,0x50,0x2e,0x97,0xcb,0xe7,0x5c,0x34,0xb0,0xc6,0x78,0xe8,0x1f,
-  0x54,0x48,0x3f,0x34,0x68,0x6c,0x80,0xdc,0xa0,0xa1,0x43,0x57,0xfe,0xb4,0x2a,0xef,
-  0xc0,0x3c,0x33,0xef,0x10,0x2f,0x1f,0x02,0xff,0x72,0xae,0xe1,0x69,0x9b,0xbb,0x7d,
-  0x04,0xc8,0xf9,0x67,0x14,0xb0,0xe9,0x5f,0xdf,0xee,0xb5,0x0d,0xcf,0x0c,0x6c,0x8e,
-  0x7e,0x81,0x85,0xa1,0x88,0x5b,0x7c,0xcf,0x74,0xfb,0xba,0xa7,0x7d,0x45,0x9f,0xf0,
-  0xcf,0x08,0xf0,0xb8,0xd1,0xa1,0x5f,0x5a,0x83,0x97,0x6a,0xc0,0x0b,0x61,0x80,0x41,
-  0x2e,0xe1,0x5d,0xdc,0x0d,0xf2,0x4d,0x63,0x7c,0x39,0xff,0xb8,0x80,0xd3,0xbc,0xc0,
-  0x02,0xfb,0xee,0x33,0x6a,0x96,0xa2,0x8a,0x65,0x51,0xaf,0x0a,0x84,0x83,0x57,0x28,
-  0x98,0x0b,0x86,0xdc,0x59,0x26,0x6c,0xcb,0x64,0x80,0x6f,0xda,0x08,0x70,0xcc,0x08,
-  0xf0,0xb8,0xf0,0xcf,0xff,0xb2,0x41,0xc7,0x0d,0xcf,0xa2,0x10,0x27,0x1f,0xe1,0xc1,
-  0xeb,0x22,0x37,0xf0,0xaa,0xd9,0x1e,0xc6,0x63,0xff,0x08,0x4f,0xac,0x60,0x28,0x01,
-  0x67,0x67,0x2f,0x33,0xe8,0x70,0x26,0x83,0xc4,0x13,0x88,0x58,0xb4,0x02,0x2d,0x08,
-  0xee,0xa1,0xdc,0xe0,0xdb,0x9c,0xc9,0x20,0xa0,0x20,0xe4,0x06,0xc8,0x05,0x32,0x9e,
-  0xa6,0x09,0x38,0x70,0x11,0xac,0xf0,0x78,0x96,0x4d,0x59,0x42,0x8b,0x45,0x9b,0x13,
-  0x0a,0x09,0xc2,0x88,0xf3,0x78,0x17,0x67,0x33,0x18,0x5f,0x88,0x2e,0x26,0x60,0xc1,
-  0x48,0x40,0xf2,0xcf,0x4f,0x0d,0xe6,0xec,0x64,0x2a,0x99,0x17,0x55,0x6b,0x49,0x3c,
-  0x08,0x6c,0x10,0x18,0x83,0xb9,0x1c,0xb1,0x91,0x81,0x21,0xc7,0xf1,0xaa,0xd9,0xac,
-  0xe9,0x9f,0xd9,0x00,0x31,0xc0,0x13,0xe6,0x0a,0xe1,0x9a,0xd4,0xda,0x9e,0x92,0x23,
-  0xff,0x30,0xb6,0x39,0x26,0x14,0x52,0x1d,0xc6,0xd3,0x12,0xd9,0x4c,0xd6,0x08,0x2f,
-  0x04,0x98,0xfd,0x13,0x78,0xd0,0xa0,0x21,0xc0,0xef,0x23,0x38,0x2c,0xda,0x54,0x3d,
-  0xef,0xc8,0x37,0x0c,0x6c,0x30,0x14,0xac,0x2b,0xec,0x78,0x80,0x1f,0xce,0xa2,0x7f,
-  0x5c,0xc0,0xd3,0x75,0xff,0xc4,0x0a,0x86,0x26,0xe0,0xcb,0x30,0xf5,0x2c,0x3d,0x25,
-  0xc7,0xf3,0x99,0x80,0x6b,0xc4,0x0b,0x3b,0x1c,0xe0,0x6a,0x22,0x8b,0xfe,0xf5,0x98,
-  0xfd,0xa5,0xd8,0x30,0x81,0x60,0x7c,0x03,0x21,0x6c,0xc7,0x79,0xeb,0x5c,0x66,0xe2,
-  0xe5,0x2c,0x78,0xe1,0x70,0x38,0x38,0x33,0x13,0x76,0x96,0xaf,0x94,0x05,0xc0,0x1e,
-  0x23,0x01,0xa7,0xcd,0x0e,0x33,0x21,0x2a,0x04,0x56,0xd0,0x77,0x08,0x3c,0x9c,0x3b,
-  0x18,0x0f,0x09,0x39,0xef,0x82,0xf5,0xc4,0x0b,0xce,0x10,0xe2,0x4c,0xc4,0x49,0xbc,
-  0x95,0xc9,0x2c,0x8a,0xfd,0x63,0x3c,0x31,0x03,0xd7,0x57,0x80,0x67,0x42,0x64,0xcd,
-  0x1d,0x02,0x4d,0x4b,0xe5,0xb0,0x6c,0x73,0xb9,0xc6,0xd0,0xce,0x80,0x73,0x61,0xf8,
-  0x6d,0xa6,0xec,0x64,0x8b,0xd6,0xe2,0x93,0x93,0x93,0x75,0xff,0x7c,0x6b,0x1a,0x20,
-  0x18,0x78,0x4e,0x7e,0xaa,0x71,0xff,0x02,0x08,0xc1,0xbe,0x50,0x43,0xde,0x85,0x89,
-  0x70,0xa6,0x3c,0x53,0x0e,0xcf,0x38,0xc8,0x37,0x96,0x48,0x24,0x4c,0xff,0x7c,0x46,
-  0xfe,0x59,0x0a,0x78,0x3c,0x10,0x38,0x6f,0xed,0x9c,0xaa,0x8d,0x5a,0x3b,0x0a,0x90,
-  0x05,0xc1,0x3c,0x8c,0x2d,0xe0,0x95,0xcb,0xce,0xcd,0xc1,0x5a,0x3c,0x1e,0xa7,0x00,
-  0xf7,0x70,0x01,0x8b,0x15,0xaa,0x68,0x80,0x69,0x2e,0x90,0x1d,0x47,0x1a,0x99,0x6a,
-  0xf0,0x0e,0x0b,0x03,0x8c,0x43,0x38,0xd0,0x5e,0xc7,0xf8,0xc6,0xe2,0xe0,0xdf,0x64,
-  0xd6,0x68,0xd0,0xd3,0x46,0x83,0xb1,0xcc,0x20,0x81,0x73,0xd4,0x23,0xff,0x68,0xf5,
-  0xbc,0xc3,0x57,0x39,0x4c,0x78,0xf0,0x5b,0xb9,0xfc,0x1b,0xa7,0xf0,0xd0,0x3e,0x0e,
-  0x70,0x4f,0x0f,0xda,0xc7,0x05,0x5c,0xe0,0x73,0xcc,0x09,0x6a,0x80,0x81,0xf4,0x37,
-  0xed,0x06,0xe7,0x44,0xde,0x85,0x59,0x86,0x7b,0x20,0xa7,0xf8,0x56,0xe2,0x54,0x1e,
-  0x93,0xd9,0x1e,0x00,0xec,0xb1,0xf8,0x17,0xb5,0xf8,0xd7,0x6b,0xfb,0xd3,0xe5,0x30,
-  0xf1,0xca,0x02,0x6e,0xa6,0x5c,0x57,0xc4,0x21,0xbe,0x52,0x9c,0x0c,0xe4,0x09,0xa4,
-  0xbb,0x5e,0xc0,0xb1,0xa2,0xe5,0x14,0x4e,0xb5,0x1d,0xae,0x71,0xe2,0x51,0xe6,0x59,
-  0xf1,0x06,0x76,0x3b,0x83,0xb7,0x12,0x07,0xc0,0xac,0x51,0xc0,0x3d,0x66,0x01,0x17,
-  0x0b,0xd1,0x82,0x89,0x77,0xc7,0x51,0x0e,0x50,0x03,0xe7,0xca,0xa2,0x68,0xad,0xfa,
-  0xac,0x33,0x7c,0x1b,0xc9,0xbf,0xc9,0x2c,0xcd,0x70,0xdd,0x19,0xd3,0xbf,0x58,0x4c,
-  0x2c,0xb1,0xb0,0x80,0xaf,0x3a,0xda,0x11,0x52,0x33,0xab,0xe1,0x4a,0xa8,0xb2,0xea,
-  0x04,0x5e,0xad,0x34,0x80,0x78,0x96,0x06,0x68,0xce,0x20,0x96,0x09,0xf8,0xe8,0xcd,
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board/esd/hh405/logo_320_240_8bpp.c

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+  0x1b,0xc5,0x84,0xa5,0x6c,0xdb,0x69,0xee,0x67,0x4b,0xdb,0xce,0x89,0x89,0x13,0x1f,
+  0x8c,0x3f,0x32,0xb3,0xeb,0xc3,0x4f,0x36,0xed,0x7e,0xd0,0xeb,0x1b,0x9a,0x0d,0x3d,
+  0x69,0x07,0x07,0xaa,0xc9,0xc5,0x42,0xd8,0xed,0xdc,0xb1,0xd4,0xe0,0xfa,0x38,0x9f,
+  0x65,0x5f,0x96,0xd5,0xe5,0x94,0xac,0x98,0xcd,0x42,0xd6,0xd6,0xc0,0xb3,0x0f,0xbb,
+  0xfd,0x91,0xac,0xe6,0xd7,0x71,0x3d,0x15,0x2c,0xf8,0x6d,0x59,0xa1,0x36,0x19,0x0b,
+  0x1b,0xf1,0xac,0x06,0x75,0xcd,0xd9,0xda,0x90,0xdf,0x9d,0x15,0xdf,0xe0,0xcd,0x62,
+  0xc4,0xcc,0xa1,0xee,0xc9,0x32,0xdc,0xe5,0xd6,0x9d,0x06,0xcb,0xe6,0x7d,0x2c,0x97,
+  0x2f,0xf2,0x4a,0x26,0x36,0x7c,0x92,0xfd,0x84,0x10,0x67,0x35,0xb1,0x8b,0x67,0x4b,
+  0xad,0x30,0xf9,0xe3,0xc4,0x89,0x13,0xf7,0x36,0x1e,0x78,0xe8,0xda,0x53,0x07,0x1e,
+  0x7a,0xeb,0x9e,0x37,0xae,0xbd,0x36,0x31,0x71,0x1c,0xe2,0x89,0x13,0x13,0x98,0x4e,
+  0x40,0x80,0x23,0xcc,0xc0,0xfe,0x38,0x66,0x27,0x58,0x72,0xe2,0x38,0x30,0xfe,0xc3,
+  0x47,0x66,0x3e,0xbc,0x7e,0xfd,0x57,0xcf,0x6e,0xee,0x3e,0x58,0xf4,0xb8,0x7c,0xda,
+  0x7d,0x0e,0x7b,0x2a,0x05,0x17,0xc1,0x64,0xb0,0xa0,0x19,0x11,0x58,0x2b,0xe8,0x40,
+  0x42,0x4f,0x28,0x0d,0x31,0x57,0xcc,0xe5,0x72,0x69,0x98,0x49,0xe8,0x01,0x9f,0x0b,
+  0xf3,0xb1,0x58,0xcc,0x59,0x38,0xa4,0x85,0xc3,0x79,0xbf,0x3f,0x9f,0x4f,0xe8,0x4e,
+  0xa6,0x84,0xf1,0xd5,0xc5,0x84,0xce,0x02,0xd4,0xe1,0xb2,0x1b,0xac,0x66,0x81,0xc5,
+  0x04,0x33,0x92,0x00,0xab,0x52,0x9f,0x19,0x77,0x69,0x4c,0x45,0x0f,0x8e,0xb0,0x6c,
+  0x6c,0x14,0xaa,0x80,0xb6,0xee,0x66,0xc5,0x36,0x66,0xa0,0x84,0x1e,0x78,0x15,0xeb,
+  0x09,0x53,0x52,0xa8,0x27,0xfc,0x3e,0xb3,0x15,0xfc,0xdc,0xc0,0x33,0xe3,0xe3,0xdb,
+  0xb7,0xdf,0xfd,0xd7,0x03,0xb5,0x07,0xf7,0xd4,0x3e,0xfd,0xfc,0x8f,0x7f,0x3f,0xfe,
+  0x9f,0xf1,0xed,0x2c,0xa0,0x7c,0x9c,0xb3,0x7d,0x9c,0xe7,0x2d,0x61,0x1c,0x7d,0x07,
+  0xce,0x6b,0xaa,0xaa,0xea,0x7f,0xf3,0xec,0xed,0xfc,0xd7,0x17,0x69,0x70,0xe6,0x83,
+  0x49,0xfb,0x4d,0xb8,0x43,0xaa,0x0e,0x65,0xb1,0x90,0x0f,0x67,0x23,0x95,0x91,0xd1,
+  0xd3,0xbd,0x4e,0xe7,0x88,0x58,0x33,0xf9,0xd8,0x3a,0x75,0xc4,0x29,0x72,0xb8,0xec,
+  0x32,0x0a,0x4a,0x00,0x07,0x8e,0xee,0xf6,0xed,0xf0,0xf9,0xca,0xf4,0x2c,0xf5,0x4c,
+  0x09,0x70,0x1a,0x2d,0x58,0xcd,0xf8,0x42,0xa6,0x0e,0x2b,0x30,0xab,0x8c,0x58,0xb4,
+  0x30,0x33,0xc2,0x2a,0x4b,0x03,0x25,0x1d,0x96,0x9c,0x2e,0x09,0xd7,0xf0,0xc0,0x49,
+  0xe4,0xf9,0xda,0x6f,0x7c,0x34,0x33,0x33,0xf3,0xf8,0xb7,0x0e,0x3e,0x3e,0x73,0x52,
+  0x30,0x73,0x72,0x17,0x26,0x10,0x67,0xc4,0x9e,0xb1,0x0b,0xf7,0xbb,0x4e,0xee,0xda,
+  0xf5,0xe1,0x9b,0xe0,0xbc,0xb1,0xb6,0xb1,0xb1,0x73,0xb7,0x19,0xbd,0x48,0xc6,0xb7,
+  0x14,0xf1,0x2f,0x3a,0x60,0x08,0x43,0x1f,0x54,0x61,0x14,0x07,0x0b,0x05,0x7f,0x3e,
+  0xac,0x69,0xf1,0xfb,0xb5,0x78,0x3c,0x1b,0x8f,0xe3,0x18,0x89,0x23,0xb0,0x63,0x41,
+  0x63,0x49,0x56,0x03,0x25,0x5e,0xc8,0x02,0x26,0x71,0xbe,0x69,0x59,0x8c,0x9c,0x38,
+  0xaf,0xcb,0x6a,0x6b,0x62,0xcf,0x07,0x39,0xd3,0x81,0x2d,0xce,0xe5,0x68,0xa2,0x94,
+  0xc3,0x53,0xb3,0xb3,0xf0,0x63,0x8d,0xcb,0x85,0xd4,0x34,0x19,0xe7,0xdf,0xf3,0x67,
+  0x8a,0xbc,0x09,0xdc,0x24,0x6e,0x5f,0x68,0x42,0xaa,0x9a,0x7e,0xba,0xef,0xe9,0xdf,
+  0x7e,0xf9,0x67,0xfb,0xfe,0xf6,0x00,0x1c,0x5b,0xc0,0x4c,0x3f,0xa4,0x18,0x44,0x14,
+  0x0a,0x55,0x55,0x63,0x63,0x6d,0x2d,0x40,0x5b,0xff,0xfc,0xed,0xdd,0x87,0x33,0xe1,
+  0xa5,0x08,0xf4,0xc0,0x17,0xe0,0x7e,0x80,0xa3,0x18,0x5c,0xb8,0xac,0x2c,0x2e,0xe2,
+  0x97,0x4e,0x74,0x19,0xe4,0xce,0x14,0x94,0x95,0x95,0x44,0x96,0x02,0xab,0x8a,0x69,
+  0x44,0x96,0x94,0xb2,0x42,0x8d,0x7f,0x69,0x46,0x2f,0xb3,0x2c,0x4f,0x1c,0x2c,0x55,
+  0xb4,0x9c,0xbb,0xd4,0x9e,0xf2,0x56,0xc9,0xfd,0x7d,0x2d,0x7b,0x31,0xec,0x6d,0x69,
+  0x79,0xf6,0x17,0x0f,0xef,0xfe,0xf8,0xf4,0xb7,0x5b,0x78,0x76,0x2f,0xd0,0x32,0x0f,
+  0xc7,0x2c,0xd3,0x22,0xa5,0x98,0xe5,0x85,0x50,0x3a,0x3f,0x7f,0x06,0xb6,0xb6,0xaa,
+  0xb6,0xad,0xb8,0x0f,0xff,0x36,0x65,0xa9,0x37,0xac,0x2f,0xab,0x2f,0xe0,0x34,0xf7,
+  0x28,0x73,0xa1,0x9a,0x53,0x73,0x39,0x47,0x4e,0xa2,0xb2,0xd4,0xa1,0x62,0x44,0xb1,
+  0x03,0x82,0xa9,0xa0,0x8a,0xd4,0x54,0xe7,0x4a,0x0e,0x2e,0xc2,0x52,0x5e,0x43,0x15,
+  0xaa,0x2a,0x2b,0x74,0x70,0x3d,0x59,0x0b,0x04,0x0e,0x07,0x2f,0xc9,0x99,0x12,0xeb,
+  0x69,0x1d,0xaa,0x45,0xb5,0x74,0x6a,0x69,0xd7,0x61,0x36,0x43,0x18,0x7d,0xbf,0xa6,
+  0x7d,0xae,0x66,0xae,0xa6,0xbd,0x46,0x32,0x27,0xe2,0xfb,0xb8,0x13,0x39,0xa4,0x9d,
+  0xeb,0xb4,0xf3,0x80,0xc7,0xed,0xed,0xed,0x67,0xce,0xcc,0xb7,0x8d,0xb5,0x6c,0xf5,
+  0x2b,0xd0,0x19,0xb8,0x06,0x1a,0xfe,0x20,0x4e,0xa4,0x99,0x07,0x53,0x70,0x3b,0xde,
+  0x9c,0xdb,0x95,0xdf,0x46,0xef,0x16,0xe2,0xad,0x5a,0xdc,0x22,0x67,0xcf,0xde,0x84,
+  0xc0,0x92,0xa3,0x17,0x59,0x6a,0x4a,0xf8,0xc1,0xcd,0x8b,0x67,0x21,0xf0,0x1c,0x66,
+  0x70,0x8f,0xe9,0xc5,0x8b,0x73,0x73,0x73,0x35,0x67,0xf6,0xb6,0x55,0xbd,0xbb,0x45,
+  0xef,0x21,0xf9,0x86,0x50,0x24,0x6c,0x0b,0x2e,0x3b,0xd4,0xff,0xcb,0xab,0xf9,0xac,
+  0xb9,0x69,0x3a,0x8f,0x7b,0x4c,0x64,0xce,0x96,0x49,0x85,0xd2,0xcd,0xb3,0xd6,0x80,
+  0xee,0x43,0xef,0x8d,0x35,0xbd,0x70,0x7b,0xaf,0x59,0xc7,0x70,0x64,0xc9,0x17,0x81,
+  0x39,0x5d,0x50,0x59,0x4e,0xb2,0x41,0xe1,0x60,0x83,0x18,0x70,0xb0,0xc1,0x2c,0xf2,
+  0xa5,0xc0,0x4a,0x73,0xa6,0xd0,0xc4,0xac,0x67,0x26,0x0e,0xa1,0x9a,0x53,0x73,0x52,
+  0xd7,0x61,0x4a,0xf0,0x00,0xab,0x38,0x2c,0xd6,0xb8,0x80,0x1f,0x9a,0x96,0x73,0x66,
+  0x2b,0x54,0x8b,0x75,0xa6,0x21,0x54,0x1d,0x66,0x4b,0xde,0xc7,0x2e,0xc4,0x37,0x33,
+  0xe2,0x60,0x9e,0x9b,0x2b,0x15,0x48,0x6a,0x4a,0x7b,0x8c,0xed,0x35,0x30,0x72,0xdb,
+  0xaa,0x9a,0xe6,0xef,0xf8,0x87,0x5c,0xc9,0xde,0xa5,0x1d,0xce,0xa2,0x96,0xb7,0x15,
+  0x12,0x41,0xcb,0x97,0x20,0xb7,0x8c,0xbe,0xbe,0xd2,0x46,0x46,0xee,0xd0,0xf8,0x1d,
+  0xa9,0xeb,0xf7,0xbd,0x6b,0xde,0x27,0x24,0x2d,0xb7,0x08,0x82,0x79,0x79,0x34,0xcf,
+  0xf4,0xda,0xda,0xda,0xc6,0xaa,0x9a,0xae,0xb7,0x7c,0xf5,0x4e,0xbd,0xc7,0xfa,0x60,
+  0x21,0x12,0x0a,0x8d,0x38,0x2b,0x8b,0x45,0xb7,0x81,0x13,0x01,0x43,0xce,0x06,0x3e,
+  0x2d,0x8c,0x72,0x63,0x9f,0xa6,0x69,0xc1,0xbf,0xff,0xd0,0xdf,0xcf,0x26,0x21,0xfd,
+  0xa5,0xd8,0x6f,0x39,0x6a,0x12,0xbb,0xd2,0x6c,0x45,0x6a,0x0b,0xae,0x7f,0xfd,0xfa,
+  0x58,0xfb,0xff,0xfe,0x23,0xc2,0xd4,0x62,0xc2,0xaf,0xb9,0xc1,0x83,0x88,0xbb,0x28,
+  0x30,0x64,0x14,0x9b,0x9b,0x97,0xb9,0x65,0x21,0x1e,0x72,0x05,0x77,0x49,0xc0,0x0f,
+  0x4c,0x1b,0x5c,0x2c,0x8d,0x18,0x56,0xa9,0xd0,0x75,0x5b,0xaa,0x95,0xb4,0xdc,0xb2,
+  0xcc,0xd2,0x02,0xf7,0x9a,0x16,0x71,0xfd,0xef,0xfd,0xf2,0xc1,0x73,0x4d,0xe7,0x9a,
+  0xca,0x58,0x93,0x5d,0xc7,0x39,0x8c,0xe7,0xb8,0xde,0xb9,0xa6,0xfe,0xb6,0x96,0x33,
+  0x73,0x9f,0xc5,0xdf,0x19,0x13,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,
+  0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,
+  0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,
+  0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,
+  0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,0x10,0x04,0x41,
+  0x10,0x04,0x41,0x10,0x5b,0xe6,0xbf,0x9f,0xe5,0x54,0xe2,0x36,0x30,0x01,0x00,

board/esd/hub405/hub405.c

@@ -30,6 +30,47 @@
 extern void lxt971_no_sleep(void);
 
 
+int board_revision(void)
+{
+	unsigned long osrl_reg;
+	unsigned long isr1l_reg;
+	unsigned long tcr_reg;
+	unsigned long value;
+
+	/*
+	 * Get version of HUB405 board from GPIO's
+	 */
+
+	/*
+	 * Setup GPIO pin(s) (IRQ6/GPIO23)
+	 */
+	osrl_reg = in32(GPIO0_OSRH);
+	isr1l_reg = in32(GPIO0_ISR1H);
+	tcr_reg = in32(GPIO0_TCR);
+	out32(GPIO0_OSRH, osrl_reg & ~0x00030000);     /* output select */
+	out32(GPIO0_ISR1H, isr1l_reg | 0x00030000);    /* input select  */
+	out32(GPIO0_TCR, tcr_reg & ~0x00000100);       /* select input  */
+
+	udelay(1000);            /* wait some time before reading input */
+	value = in32(GPIO0_IR) & 0x00000100;         /* get config bits */
+
+	/*
+	 * Restore GPIO settings
+	 */
+	out32(GPIO0_OSRH, osrl_reg);                   /* output select */
+	out32(GPIO0_ISR1H, isr1l_reg);                 /* input select  */
+	out32(GPIO0_TCR, tcr_reg);  /* enable output driver for outputs */
+
+	if (value & 0x00000100) {
+		/* Revision 1.1 or 1.2 detected */
+		return 1;
+	}
+
+	/* Revision 1.0 */
+	return 0;
+}
+
+
 int board_early_init_f (void)
 {
 	/*
@@ -69,6 +110,8 @@ int misc_init_f (void)
 
 int misc_init_r (void)
 {
+	DECLARE_GLOBAL_DATA_PTR;
+
 	volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
 	volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
 	volatile unsigned char *duart2_mcr = (unsigned char *)((ulong)DUART2_BA + 4);
@@ -77,6 +120,7 @@ int misc_init_r (void)
 	unsigned long val;
 	int delay, flashcnt;
 	char *str;
+	char hw_rev[4];
 
 	/*
 	 * Enable interrupts in exar duart mcr[3]
@@ -121,14 +165,14 @@ int misc_init_r (void)
 	 */
 	str = getenv("bd_type"); /* this is only set on non prototype hardware */
 	if (str != NULL) {
-		if ((strcmp(str, "swch405") == 0) || (strcmp(str, "hub405") == 0)) {
+		if ((strcmp(str, "swch405") == 0) || ((!strcmp(str, "hub405") && (gd->board_type >= 1)))) {
 			unsigned char led_reg_default = 0;
 			str = getenv("ap_pwr");
 			if (!str || (str && (str[0] == '1')))
 				led_reg_default = 0x04 | 0x02 ; /* U2_LED | AP_PWR */
 
 			/*
-			 * Flash LEDs on SWCH405
+			 * Flash LEDs
 			 */
 			for (flashcnt = 0; flashcnt < 3; flashcnt++) {
 				*led_reg = led_reg_default;        /* LED_A..D off */
@@ -150,6 +194,11 @@ int misc_init_r (void)
 	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
 	udelay(1000); /* wait 1ms */
 
+	/*
+	 * Store hardware revision in environment for further processing
+	 */
+	sprintf(hw_rev, "1.%ld", gd->board_type);
+	setenv("hw_rev", hw_rev);
 	return (0);
 }
 
@@ -159,6 +208,8 @@ int misc_init_r (void)
  */
 int checkboard (void)
 {
+	DECLARE_GLOBAL_DATA_PTR;
+
 	unsigned char str[64];
 	int i = getenv_r ("serial#", str, sizeof(str));
 
@@ -170,7 +221,14 @@ int checkboard (void)
 		puts(str);
 	}
 
-	putc ('\n');
+	if (getenv_r("bd_type", str, sizeof(str)) != -1) {
+		printf(" (%s", str);
+	} else {
+		puts(" (Missing bd_type!");
+	}
+
+	gd->board_type = board_revision();
+	printf(", Rev 1.%ld)\n", gd->board_type);
 
 	/*
 	 * Disable sleep mode in LXT971

board/esd/pmc405/fpgadata.c

@@ -6,26 +6,26 @@
   0x00,0x00,0x03,0x09,0x03,0xff,0xfd,0x03,0xff,0xfd,0x04,0x00,0x00,0x00,0x00,0x02,
   0x08,0xea,0x08,0x00,0x00,0x00,0x22,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x00,
   0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,
-  0x00,0x04,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x08,0x00,0x01,0x00,
+  0x00,0x04,0x38,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x08,0x00,0x01,0x00,
   0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
   0x00,0x00,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x20,0x00,0x01,
-  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x24,0x38,0x01,0x00,0x00,0x00,0x00,0x01,
   0x09,0x00,0x00,0x28,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x2c,0x00,
   0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x30,0x00,0x01,0x00,0x00,0x00,0x00,
   0x01,0x09,0x00,0x00,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x44,
-  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x48,0x00,0x01,0x00,0x00,0x00,
+  0x14,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x48,0x00,0x01,0x00,0x00,0x00,
   0x00,0x01,0x09,0x00,0x00,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,
   0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x00,0x50,0x00,0x03,0x00,0x00,
   0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x00,0x80,0x00,0x01,0x00,
   0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,
-  0x00,0x00,0x84,0x38,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
   0x09,0x00,0x00,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x8c,0x00,
   0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x90,0x00,0x01,0x00,0x00,0x00,0x00,
   0x01,0x09,0x00,0x00,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xa4,
-  0x38,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xa8,0x00,0x01,0x00,0x00,0x00,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xa8,0x00,0x01,0x00,0x00,0x00,
   0x00,0x01,0x09,0x00,0x00,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,
   0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xc0,0x00,0x01,0x00,0x00,
-  0x00,0x00,0x01,0x09,0x00,0x00,0xc4,0x14,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+  0x00,0x00,0x01,0x09,0x00,0x00,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
   0x00,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xcc,0x00,0x01,0x00,
   0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,
   0x00,0x00,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,
@@ -128,34 +128,34 @@
   0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x04,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,
   0x01,0x09,0x00,0x04,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,
   0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x04,0xd0,0x00,0x03,0x00,0x00,0x00,
-  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x05,0x00,0x80,0x01,0x00,0x00,
+  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x05,0x00,0xc0,0x11,0x00,0x00,
   0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,
-  0x05,0x04,0x40,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,
-  0x00,0x05,0x08,0x00,0x31,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x0c,0x80,0x01,
-  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,
-  0x09,0x00,0x05,0x20,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x24,0x04,
-  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x28,0x00,0x01,0x00,0x00,0x00,0x00,
-  0x01,0x09,0x00,0x05,0x2c,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x30,
-  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x40,0xa0,0x11,0x00,0x00,0x00,
-  0x00,0x01,0x09,0x00,0x05,0x44,0xe8,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,
-  0x48,0x40,0x09,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x4c,0x80,0x11,0x00,0x00,
+  0x05,0x04,0xc0,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,
+  0x00,0x05,0x08,0x40,0x31,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x0c,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x10,0x80,0x01,0x00,0x00,0x00,0x00,0x01,
+  0x09,0x00,0x05,0x20,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x24,0x00,
+  0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x28,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x05,0x2c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x30,
+  0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x40,0x20,0x19,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x05,0x44,0x20,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,
+  0x48,0x48,0x09,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x4c,0x00,0x01,0x00,0x00,
   0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,
-  0x05,0x50,0x80,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,
-  0x00,0x05,0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,
-  0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x05,0x84,0x04,0x31,0x00,0x00,0x00,0x00,0x00,
-  0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x05,0x88,0xc0,0x01,0x00,0x00,0x00,0x00,
-  0x01,0x09,0x00,0x05,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x90,
+  0x05,0x50,0x00,0x13,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,
+  0x00,0x05,0x80,0x00,0x21,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x05,0x84,0x00,0x11,0x00,0x00,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x05,0x88,0x80,0x01,0x00,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x05,0x8c,0x80,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0x90,
   0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0xa0,0x04,0x01,0x00,0x00,0x00,
   0x00,0x01,0x09,0x00,0x05,0xa4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,
-  0xa8,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0xac,0x00,0x01,0x00,0x00,
+  0xa8,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0xac,0x00,0x11,0x00,0x00,
   0x00,0x00,0x01,0x09,0x00,0x05,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
-  0x05,0xc0,0x08,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0xc4,0x00,0x09,0x00,
-  0x00,0x00,0x00,0x01,0x09,0x00,0x05,0xc8,0x80,0x11,0x00,0x00,0x00,0x00,0x01,0x09,
-  0x00,0x05,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,
+  0x05,0xc0,0xc8,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x05,0xc4,0x08,0x09,0x00,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x05,0xc8,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x00,0x05,0xcc,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,
   0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x05,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,
   0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x06,0x03,0x02,0x01,0x00,0x00,0x00,0x00,
   0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x06,0x07,
-  0x02,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x06,
+  0x42,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x06,
   0x0b,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0x0f,0x02,0x01,0x00,0x00,
   0x00,0x00,0x01,0x09,0x00,0x06,0x13,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
   0x06,0x23,0x03,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0x27,0x03,0x01,0x00,
@@ -165,8 +165,8 @@
   0x09,0x00,0x06,0x44,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0x48,0x00,
   0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,
   0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x06,0x50,
-  0x80,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x06,
-  0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,
+  0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x06,
+  0x80,0x04,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,
   0x00,0x00,0x00,0x09,0x00,0x06,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
   0x00,0x00,0x00,0x00,0x09,0x00,0x06,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
   0x00,0x06,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0x90,0x00,0x01,
@@ -175,10 +175,10 @@
   0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0xac,0x00,0x01,0x00,0x00,0x00,0x00,
   0x01,0x09,0x00,0x06,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0xc0,
   0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,0xc4,0x00,0x01,0x00,0x00,0x00,
-  0x00,0x01,0x09,0x00,0x06,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,
-  0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x06,0xc8,0x40,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x06,
+  0xcc,0x80,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,
   0x00,0x00,0x00,0x09,0x00,0x06,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
-  0x00,0x00,0x00,0x03,0x09,0x00,0x07,0x03,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x01,
+  0x00,0x00,0x00,0x03,0x09,0x00,0x07,0x02,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x01,
   0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x07,0x07,0x02,0x01,
   0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x07,0x0b,0x02,
   0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x07,0x0f,0x02,0x01,0x00,0x00,0x00,0x00,
@@ -207,7 +207,7 @@
   0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x08,0x04,0x00,0x01,0x00,0x00,
   0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x08,0x08,0x00,0x01,0x00,
   0x00,0x00,0x00,0x01,0x09,0x00,0x08,0x0e,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
-  0x00,0x08,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x08,0x22,0x01,0x01,
+  0x00,0x08,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x08,0x23,0x01,0x01,
   0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x08,0x26,0x01,0x01,0x00,0x00,0x00,0x00,0x01,
   0x09,0x00,0x08,0x28,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x08,0x2e,0x01,
   0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x08,0x30,0x00,0x01,0x00,0x00,0x00,0x00,
@@ -258,8 +258,8 @@
   0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0a,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,
   0x09,0x00,0x0a,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0x10,0x00,
   0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0x20,0x00,0x01,0x00,0x00,0x00,0x00,
-  0x01,0x09,0x00,0x0a,0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0x28,
-  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0x2e,0x00,0x01,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x0a,0x26,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0x28,
+  0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0x2c,0x01,0x01,0x00,0x00,0x00,
   0x00,0x01,0x09,0x00,0x0a,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,
   0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0x44,0x00,0x01,0x00,0x00,
   0x00,0x00,0x01,0x09,0x00,0x0a,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
@@ -278,13 +278,13 @@
   0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0a,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,
   0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0a,0xd0,0x00,
   0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x0b,0x00,
-  0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,
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   0x0b,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x10,0x00,0x01,0x00,
-  0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x20,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x22,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
   0x00,0x0b,0x26,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x28,0x01,0x01,
-  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x2c,0x01,0x01,0x00,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x2e,0x01,0x01,0x00,0x00,0x00,0x00,0x01,
   0x09,0x00,0x0b,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x40,0x00,
   0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x44,0x00,0x01,0x00,0x00,0x00,0x00,
   0x01,0x09,0x00,0x0b,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0b,0x4c,
@@ -327,12 +327,12 @@
   0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0c,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,
   0x01,0x09,0x00,0x0c,0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,
   0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0c,0xd0,0x00,0x03,0x00,0x00,0x00,
-  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x0d,0x03,0x46,0x01,0x00,0x00,
+  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x0d,0x03,0x02,0x01,0x00,0x00,
   0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,
   0x0d,0x07,0x02,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,
   0x00,0x0d,0x0b,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x0f,0x02,0x01,
   0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x13,0x02,0x01,0x00,0x00,0x00,0x00,0x01,
-  0x09,0x00,0x0d,0x23,0x03,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x27,0x03,
+  0x09,0x00,0x0d,0x23,0x03,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x27,0x07,
   0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x2b,0x03,0x01,0x00,0x00,0x00,0x00,
   0x01,0x09,0x00,0x0d,0x2f,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x30,
   0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x40,0x00,0x01,0x00,0x00,0x00,
@@ -340,7 +340,7 @@
   0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x4c,0x00,0x01,0x00,0x00,
   0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,
   0x0d,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,
-  0x00,0x0d,0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,
+  0x00,0x0d,0x80,0x04,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,
   0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x0d,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
   0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0d,0x88,0x00,0x01,0x00,0x00,0x00,0x00,
   0x01,0x09,0x00,0x0d,0x8c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0d,0x90,
@@ -354,27 +354,27 @@
   0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0d,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,
   0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x0e,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
   0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x0e,0x04,
-  0x40,0x11,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0e,
-  0x08,0x80,0x31,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x0c,0x80,0x01,0x00,0x00,
+  0xc0,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x0e,
+  0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x0c,0x80,0x01,0x00,0x00,
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-  0x0e,0x20,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x24,0x04,0x01,0x00,
-  0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x28,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x0e,0x20,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x24,0x00,0x11,0x00,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x28,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
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-  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x40,0x48,0x01,0x00,0x00,0x00,0x00,0x01,
-  0x09,0x00,0x0e,0x44,0x20,0x09,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x48,0x80,
-  0x19,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x4c,0x80,0x11,0x00,0x00,0x00,0x00,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x40,0x60,0x01,0x00,0x00,0x00,0x00,0x01,
+  0x09,0x00,0x0e,0x44,0x48,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x48,0xc0,
+  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0x4c,0x80,0x11,0x00,0x00,0x00,0x00,
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-  0x80,0x80,0x31,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,
-  0x00,0x00,0x00,0x09,0x00,0x0e,0x84,0x84,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
-  0x00,0x00,0x00,0x00,0x09,0x00,0x0e,0x88,0x40,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,
+  0x00,0x00,0x00,0x09,0x00,0x0e,0x84,0x00,0x21,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
+  0x00,0x00,0x00,0x00,0x09,0x00,0x0e,0x88,0x40,0x11,0x00,0x00,0x00,0x00,0x01,0x09,
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-  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0xa0,0x04,0x11,0x00,0x00,0x00,0x00,0x01,
-  0x09,0x00,0x0e,0xa4,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0xa8,0x00,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,
+  0x09,0x00,0x0e,0xa4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0xa8,0x00,
   0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0xac,0x00,0x01,0x00,0x00,0x00,0x00,
   0x01,0x09,0x00,0x0e,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0xc0,
-  0xa0,0x19,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0xc4,0xc8,0x11,0x00,0x00,0x00,
-  0x00,0x01,0x09,0x00,0x0e,0xc8,0x40,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,0xc4,0xa0,0x01,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x0e,0xc8,0x08,0x09,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x0e,
   0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,
   0x00,0x00,0x00,0x09,0x00,0x0e,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
   0x00,0x00,0x00,0x03,0x09,0x00,0x0f,0x00,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x01,
@@ -403,17 +403,17 @@
   0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,
   0x00,0x09,0x00,0x0f,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
   0x00,0x03,0x09,0x00,0x10,0x01,0x82,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,
-  0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x10,0x04,0x82,0x01,0x00,0x00,
+  0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x10,0x05,0x82,0x01,0x00,0x00,
   0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x10,0x0a,0x82,0x01,0x00,
-  0x00,0x00,0x00,0x01,0x09,0x00,0x10,0x0e,0x82,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
-  0x00,0x10,0x12,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x10,0x20,0x03,0x11,
+  0x00,0x00,0x00,0x01,0x09,0x00,0x10,0x0c,0x82,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
+  0x00,0x10,0x12,0x82,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x10,0x20,0x03,0x11,
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-  0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x10,0x30,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x10,0x30,0x00,0x11,0x00,0x00,0x00,0x00,
   0x01,0x09,0x00,0x10,0x40,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x10,0x44,
   0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x10,0x48,0x00,0x11,0x00,0x00,0x00,
   0x00,0x01,0x09,0x00,0x10,0x4c,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,
-  0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x10,0x50,0x00,0x03,0x00,0x00,
+  0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x10,0x50,0x00,0x13,0x00,0x00,
   0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x10,0x80,0x00,0x01,0x00,
   0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,
   0x00,0x10,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
@@ -427,31 +427,31 @@
   0x10,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x10,0xcc,0x00,0x01,0x00,
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   0x00,0x10,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,
-  0x09,0x00,0x11,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,
-  0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x11,0x04,0x04,0x01,0x00,0x00,0x00,0x00,
-  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x11,0x08,0x00,0x11,0x00,0x00,0x00,
+  0x09,0x00,0x11,0x00,0xc0,0x11,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,
+  0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x11,0x04,0x00,0x11,0x00,0x00,0x00,0x00,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x11,0x08,0x80,0x21,0x00,0x00,0x00,
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-  0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0x20,0x00,0x01,0x00,0x00,
-  0x00,0x00,0x01,0x09,0x00,0x11,0x24,0x04,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
-  0x11,0x28,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0x2c,0x00,0x01,0x00,
+  0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0x20,0x00,0x11,0x00,0x00,
+  0x00,0x00,0x01,0x09,0x00,0x11,0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+  0x11,0x28,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x11,0x2c,0x00,0x01,0x00,
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@@ -493,7 +493,7 @@
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@@ -503,8 +503,8 @@
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@@ -528,55 +528,55 @@
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   0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0xaf,0x01,0x01,0x00,0x00,0x00,0x00,
   0x01,0x09,0x00,0x16,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0xc0,
-  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0xc4,0x80,0x01,0x00,0x00,0x00,
-  0x00,0x01,0x09,0x00,0x16,0xc8,0x40,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,0xc4,0x00,0x01,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x16,0xc8,0x08,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x16,
   0xcc,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,
   0x00,0x00,0x00,0x09,0x00,0x16,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
-  0x00,0x00,0x00,0x03,0x09,0x00,0x17,0x03,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x01,
+  0x00,0x00,0x00,0x03,0x09,0x00,0x17,0x02,0x02,0x01,0x00,0x00,0x00,0x00,0x01,0x01,
   0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x17,0x07,0x02,0x01,
   0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x17,0x0b,0x02,
   0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x17,0x0f,0x02,0x01,0x00,0x00,0x00,0x00,
@@ -593,7 +593,7 @@
   0x00,0x09,0x00,0x17,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
   0x00,0x00,0x09,0x00,0x17,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x17,
   0x8e,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x17,0x90,0x00,0x01,0x00,0x00,
-  0x00,0x00,0x01,0x09,0x00,0x17,0xa2,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+  0x00,0x00,0x01,0x09,0x00,0x17,0xa3,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
   0x17,0xa6,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x17,0xa8,0x01,0x01,0x00,
   0x00,0x00,0x00,0x01,0x09,0x00,0x17,0xae,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
   0x00,0x17,0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x17,0xc0,0x00,0x01,
@@ -618,9 +618,9 @@
   0x00,0x18,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
   0x09,0x00,0x18,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,0x8c,0x00,
   0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,0x90,0x00,0x01,0x00,0x00,0x00,0x00,
-  0x01,0x09,0x00,0x18,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,0xa4,
-  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,0xa8,0x00,0x01,0x00,0x00,0x00,
-  0x00,0x01,0x09,0x00,0x18,0xae,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,
+  0x01,0x09,0x00,0x18,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,0xa6,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,0xa8,0x01,0x01,0x00,0x00,0x00,
+  0x00,0x01,0x09,0x00,0x18,0xac,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,
   0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,0xc0,0x00,0x01,0x00,0x00,
   0x00,0x00,0x01,0x09,0x00,0x18,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
   0x18,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x18,0xcc,0x00,0x01,0x00,
@@ -658,16 +658,16 @@
   0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,0x20,0x00,0x11,0x00,0x00,0x00,0x00,
   0x01,0x09,0x00,0x1a,0x24,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,0x28,
   0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,0x2c,0x00,0x11,0x00,0x00,0x00,
-  0x00,0x01,0x09,0x00,0x1a,0x30,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,
+  0x00,0x01,0x09,0x00,0x1a,0x30,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,
   0x40,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,0x44,0x00,0x11,0x00,0x00,
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   0x1a,0x4c,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,
-  0x00,0x00,0x00,0x00,0x09,0x00,0x1a,0x50,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x09,0x00,0x1a,0x50,0x00,0x13,0x00,0x00,0x00,0x00,0x00,0x01,
   0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x1a,0x82,0x81,0x01,0x00,0x00,0x00,0x00,0x01,
   0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x1a,0x84,0x80,
   0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x1a,0x88,
   0x80,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,0x8c,0x80,0x01,0x00,0x00,0x00,
-  0x00,0x01,0x09,0x00,0x1a,0x90,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,
+  0x00,0x01,0x09,0x00,0x1a,0x90,0x80,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,
   0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,0xa4,0x00,0x01,0x00,0x00,
   0x00,0x00,0x01,0x09,0x00,0x1a,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
   0x1a,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x1a,0xb0,0x00,0x01,0x00,
@@ -1006,7 +1006,7 @@
   0x00,0x28,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x20,0x00,0x11,
   0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x24,0x00,0x11,0x00,0x00,0x00,0x00,0x01,
   0x09,0x00,0x28,0x28,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x2c,0x00,
-  0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x30,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x30,0x00,0x11,0x00,0x00,0x00,0x00,
   0x01,0x09,0x00,0x28,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x44,
   0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x48,0x00,0x01,0x00,0x00,0x00,
   0x00,0x01,0x09,0x00,0x28,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,
@@ -1015,7 +1015,7 @@
   0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,
   0x00,0x28,0x84,0x80,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
   0x09,0x00,0x28,0x88,0x80,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x8c,0x80,
-  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x90,0x00,0x01,0x00,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0x90,0x80,0x01,0x00,0x00,0x00,0x00,
   0x01,0x09,0x00,0x28,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0xa4,
   0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,0xa8,0x00,0x01,0x00,0x00,0x00,
   0x00,0x01,0x09,0x00,0x28,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x28,
@@ -1023,30 +1023,30 @@
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   0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,
-  0x00,0x28,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,
-  0x09,0x00,0x29,0x00,0x80,0x31,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,
-  0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x29,0x04,0x84,0x31,0x00,0x00,0x00,0x00,
-  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x29,0x08,0xc0,0x01,0x00,0x00,0x00,
+  0x00,0x28,0xd0,0x00,0x13,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,
+  0x09,0x00,0x29,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,
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+  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x29,0x08,0x00,0x01,0x00,0x00,0x00,
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-  0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0x20,0x04,0x11,0x00,0x00,
-  0x00,0x00,0x01,0x09,0x00,0x29,0x24,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
-  0x29,0x28,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0x2c,0x00,0x01,0x00,
+  0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0x20,0x00,0x01,0x00,0x00,
+  0x00,0x00,0x01,0x09,0x00,0x29,0x24,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
+  0x29,0x28,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0x2c,0x00,0x01,0x00,
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-  0x00,0x29,0x40,0xe8,0x19,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0x44,0xe8,0x19,
-  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0x48,0xc0,0x11,0x00,0x00,0x00,0x00,0x01,
+  0x00,0x29,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0x44,0x00,0x01,
+  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0x48,0x00,0x01,0x00,0x00,0x00,0x00,0x01,
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-  0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x29,0x50,0x80,0x03,0x00,0x00,0x00,0x00,
+  0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x29,0x50,0x00,0x03,0x00,0x00,0x00,0x00,
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-  0x84,0x40,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,
-  0x29,0x88,0x00,0x31,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0x8c,0x80,0x01,0x00,
+  0x84,0x00,0xc1,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,
+  0x29,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0x8c,0x00,0x01,0x00,
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-  0x00,0x29,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0xa4,0x04,0x01,
+  0x00,0x29,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0xa4,0x80,0xe1,
   0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0xa8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,
-  0x09,0x00,0x29,0xac,0x00,0x11,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0xb0,0x00,
+  0x09,0x00,0x29,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0xb0,0x00,
   0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0xc0,0x00,0x01,0x00,0x00,0x00,0x00,
-  0x01,0x09,0x00,0x29,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0xc8,
-  0x00,0x09,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0xcc,0x80,0x11,0x00,0x00,0x00,
+  0x01,0x09,0x00,0x29,0xc4,0x00,0x61,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0xc8,
+  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x29,0xcc,0x00,0x01,0x00,0x00,0x00,
   0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x29,
   0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,
   0x2a,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,
@@ -1351,25 +1351,25 @@
   0x01,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xe8,0x08,0x00,0x00,0x00,0x06,0x01,0x00,
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@@ -1454,30 +1454,30 @@
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@@ -1485,8 +1485,8 @@
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@@ -1494,10 +1494,10 @@
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@@ -1520,8 +1520,8 @@
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   0x09,0x00,0x08,0x2e,0x01,0x03,0x00,0x08,0x28,0x01,0x01,0x09,0x00,0x08,0x30,0x00,
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@@ -1562,9 +1562,9 @@
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@@ -1578,14 +1578,14 @@
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@@ -1619,19 +1619,19 @@
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@@ -1641,26 +1641,26 @@
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@@ -1682,17 +1682,17 @@
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@@ -1757,17 +1757,17 @@
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@@ -1785,49 +1785,49 @@
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@@ -1839,8 +1839,8 @@
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@@ -1861,9 +1861,9 @@
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@@ -1894,15 +1894,15 @@
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@@ -2183,41 +2183,41 @@
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+  0x28,0x8c,0x80,0x03,0x00,0x28,0x88,0x80,0x01,0x09,0x00,0x28,0x90,0x80,0x03,0x00,
+  0x28,0x8c,0x80,0x01,0x09,0x00,0x28,0xa0,0x00,0x03,0x00,0x28,0x90,0x80,0x01,0x09,
   0x00,0x28,0xa4,0x00,0x03,0x00,0x28,0xa0,0x00,0x01,0x09,0x00,0x28,0xa8,0x00,0x03,
   0x00,0x28,0xa4,0x00,0x01,0x09,0x00,0x28,0xac,0x00,0x03,0x00,0x28,0xa8,0x00,0x01,
   0x09,0x00,0x28,0xb0,0x00,0x03,0x00,0x28,0xac,0x00,0x01,0x09,0x00,0x28,0xc0,0x00,
   0x13,0x00,0x28,0xb0,0x00,0x01,0x09,0x00,0x28,0xc4,0x00,0x13,0x00,0x28,0xc0,0x00,
   0x11,0x09,0x00,0x28,0xc8,0x00,0x13,0x00,0x28,0xc4,0x00,0x11,0x09,0x00,0x28,0xcc,
-  0x00,0x13,0x00,0x28,0xc8,0x00,0x11,0x09,0x00,0x28,0xd0,0x00,0x03,0x00,0x28,0xcc,
-  0x00,0x11,0x09,0x00,0x29,0x00,0x80,0x33,0x00,0x28,0xd0,0x00,0x01,0x09,0x00,0x29,
-  0x04,0x84,0x33,0x00,0x29,0x00,0x80,0x31,0x09,0x00,0x29,0x08,0xc0,0x03,0x00,0x29,
-  0x04,0x84,0x31,0x09,0x00,0x29,0x0c,0x00,0x03,0x00,0x29,0x08,0xc0,0x01,0x09,0x00,
-  0x29,0x10,0x00,0x03,0x00,0x29,0x0c,0x00,0x01,0x09,0x00,0x29,0x20,0x04,0x13,0x00,
-  0x29,0x10,0x00,0x01,0x09,0x00,0x29,0x24,0x00,0x13,0x00,0x29,0x20,0x04,0x11,0x09,
-  0x00,0x29,0x28,0x00,0x13,0x00,0x29,0x24,0x00,0x11,0x09,0x00,0x29,0x2c,0x00,0x03,
-  0x00,0x29,0x28,0x00,0x11,0x09,0x00,0x29,0x30,0x00,0x03,0x00,0x29,0x2c,0x00,0x01,
-  0x09,0x00,0x29,0x40,0xe8,0x1b,0x00,0x29,0x30,0x00,0x01,0x09,0x00,0x29,0x44,0xe8,
-  0x1b,0x00,0x29,0x40,0xe8,0x19,0x09,0x00,0x29,0x48,0xc0,0x13,0x00,0x29,0x44,0xe8,
-  0x19,0x09,0x00,0x29,0x4c,0x00,0x03,0x00,0x29,0x48,0xc0,0x11,0x09,0x00,0x29,0x50,
-  0x80,0x03,0x00,0x29,0x4c,0x00,0x01,0x09,0x00,0x29,0x80,0x00,0x03,0x00,0x29,0x50,
-  0x80,0x01,0x09,0x00,0x29,0x84,0x40,0x03,0x00,0x29,0x80,0x00,0x01,0x09,0x00,0x29,
-  0x88,0x00,0x33,0x00,0x29,0x84,0x40,0x01,0x09,0x00,0x29,0x8c,0x80,0x03,0x00,0x29,
-  0x88,0x00,0x31,0x09,0x00,0x29,0x90,0x00,0x03,0x00,0x29,0x8c,0x80,0x01,0x09,0x00,
-  0x29,0xa0,0x00,0x03,0x00,0x29,0x90,0x00,0x01,0x09,0x00,0x29,0xa4,0x04,0x03,0x00,
-  0x29,0xa0,0x00,0x01,0x09,0x00,0x29,0xa8,0x00,0x03,0x00,0x29,0xa4,0x04,0x01,0x09,
-  0x00,0x29,0xac,0x00,0x13,0x00,0x29,0xa8,0x00,0x01,0x09,0x00,0x29,0xb0,0x00,0x03,
-  0x00,0x29,0xac,0x00,0x11,0x09,0x00,0x29,0xc0,0x00,0x03,0x00,0x29,0xb0,0x00,0x01,
-  0x09,0x00,0x29,0xc4,0x00,0x03,0x00,0x29,0xc0,0x00,0x01,0x09,0x00,0x29,0xc8,0x00,
-  0x0b,0x00,0x29,0xc4,0x00,0x01,0x09,0x00,0x29,0xcc,0x80,0x13,0x00,0x29,0xc8,0x00,
-  0x09,0x09,0x00,0x29,0xd0,0x00,0x03,0x00,0x29,0xcc,0x80,0x11,0x09,0x00,0x2a,0x00,
+  0x00,0x13,0x00,0x28,0xc8,0x00,0x11,0x09,0x00,0x28,0xd0,0x00,0x13,0x00,0x28,0xcc,
+  0x00,0x11,0x09,0x00,0x29,0x00,0x00,0x03,0x00,0x28,0xd0,0x00,0x11,0x09,0x00,0x29,
+  0x04,0x00,0x03,0x00,0x29,0x00,0x00,0x01,0x09,0x00,0x29,0x08,0x00,0x03,0x00,0x29,
+  0x04,0x00,0x01,0x09,0x00,0x29,0x0c,0x00,0x03,0x00,0x29,0x08,0x00,0x01,0x09,0x00,
+  0x29,0x10,0x00,0x03,0x00,0x29,0x0c,0x00,0x01,0x09,0x00,0x29,0x20,0x00,0x03,0x00,
+  0x29,0x10,0x00,0x01,0x09,0x00,0x29,0x24,0x00,0x03,0x00,0x29,0x20,0x00,0x01,0x09,
+  0x00,0x29,0x28,0x00,0x03,0x00,0x29,0x24,0x00,0x01,0x09,0x00,0x29,0x2c,0x00,0x03,
+  0x00,0x29,0x28,0x00,0x01,0x09,0x00,0x29,0x30,0x00,0x03,0x00,0x29,0x2c,0x00,0x01,
+  0x09,0x00,0x29,0x40,0x00,0x03,0x00,0x29,0x30,0x00,0x01,0x09,0x00,0x29,0x44,0x00,
+  0x03,0x00,0x29,0x40,0x00,0x01,0x09,0x00,0x29,0x48,0x00,0x03,0x00,0x29,0x44,0x00,
+  0x01,0x09,0x00,0x29,0x4c,0x00,0x03,0x00,0x29,0x48,0x00,0x01,0x09,0x00,0x29,0x50,
+  0x00,0x03,0x00,0x29,0x4c,0x00,0x01,0x09,0x00,0x29,0x80,0x00,0x03,0x00,0x29,0x50,
+  0x00,0x01,0x09,0x00,0x29,0x84,0x00,0xc3,0x00,0x29,0x80,0x00,0x01,0x09,0x00,0x29,
+  0x88,0x00,0x03,0x00,0x29,0x84,0x00,0xc1,0x09,0x00,0x29,0x8c,0x00,0x03,0x00,0x29,
+  0x88,0x00,0x01,0x09,0x00,0x29,0x90,0x00,0x03,0x00,0x29,0x8c,0x00,0x01,0x09,0x00,
+  0x29,0xa0,0x00,0x03,0x00,0x29,0x90,0x00,0x01,0x09,0x00,0x29,0xa4,0x80,0xe3,0x00,
+  0x29,0xa0,0x00,0x01,0x09,0x00,0x29,0xa8,0x00,0x03,0x00,0x29,0xa4,0x80,0xe1,0x09,
+  0x00,0x29,0xac,0x00,0x03,0x00,0x29,0xa8,0x00,0x01,0x09,0x00,0x29,0xb0,0x00,0x03,
+  0x00,0x29,0xac,0x00,0x01,0x09,0x00,0x29,0xc0,0x00,0x03,0x00,0x29,0xb0,0x00,0x01,
+  0x09,0x00,0x29,0xc4,0x00,0x63,0x00,0x29,0xc0,0x00,0x01,0x09,0x00,0x29,0xc8,0x00,
+  0x03,0x00,0x29,0xc4,0x00,0x61,0x09,0x00,0x29,0xcc,0x00,0x03,0x00,0x29,0xc8,0x00,
+  0x01,0x09,0x00,0x29,0xd0,0x00,0x03,0x00,0x29,0xcc,0x00,0x01,0x09,0x00,0x2a,0x00,
   0x00,0x03,0x00,0x29,0xd0,0x00,0x01,0x09,0x00,0x2a,0x04,0x00,0x03,0x00,0x2a,0x00,
   0x00,0x01,0x09,0x00,0x2a,0x08,0x00,0x03,0x00,0x2a,0x04,0x00,0x01,0x09,0x00,0x2a,
   0x0c,0x00,0x03,0x00,0x2a,0x08,0x00,0x01,0x09,0x00,0x2a,0x10,0x00,0x03,0x00,0x2a,

board/evb4510/Makefile

@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	:= evb4510.o flash.o
-SOBJS	:= memsetup.o
+SOBJS	:= lowlevel_init.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $^

board/evb4510/lowlevel_init.S

@@ -31,7 +31,7 @@
  *
  * This memory map allows us to relocate from FLASH to SRAM.  After
  * power-on reset the CPU only knows about the FLASH memory at address
- * 0x00000000.	After memsetup completes the memory map will be:
+ * 0x00000000.	After lowlevel_init completes the memory map will be:
  *
  * Memory Addr
  * 0x00000000
@@ -54,8 +54,8 @@
  *
  ***********************************************************************/
 
-.globl memsetup
-memsetup:
+.globl lowlevel_init
+lowlevel_init:
 
 	/* preserve the temp register (r12 AKA ip) and remap it. */
 	ldr r1, =SRAM_BASE+0xC

board/evb64260/pci.c

@@ -629,6 +629,7 @@ static void gt_setup_ide (struct pci_controller *hose,
 	}
 }
 
+#ifndef CONFIG_P3G4
 static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
 {
 	unsigned char pin, irq;
@@ -642,6 +643,7 @@ static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
 			pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
 	}
 }
+#endif
 
 struct pci_config_table gt_config_table[] = {
 	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
@@ -651,12 +653,16 @@ struct pci_config_table gt_config_table[] = {
 };
 
 struct pci_controller pci0_hose = {
+#ifndef CONFIG_P3G4
 	fixup_irq:gt_fixup_irq,
+#endif
 	config_table:gt_config_table,
 };
 
 struct pci_controller pci1_hose = {
+#ifndef CONFIG_P3G4
 	fixup_irq:gt_fixup_irq,
+#endif
 	config_table:gt_config_table,
 };
 
@@ -692,8 +698,10 @@ void pci_init_board (void)
 
 	pci_register_hose (&pci0_hose);
 
+#ifndef CONFIG_P3G4
 	pciArbiterEnable (PCI_HOST0);
 	pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
+#endif
 
 	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
 	command |= PCI_COMMAND_MASTER;
@@ -735,8 +743,10 @@ void pci_init_board (void)
 
 	pci_register_hose (&pci1_hose);
 
+#ifndef CONFIG_P3G4
 	pciArbiterEnable (PCI_HOST1);
 	pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
+#endif
 
 	command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
 	command |= PCI_COMMAND_MASTER;

board/funkwerk/vovpn-gw/Makefile

@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= $(BOARD).o flash.o m88e6060.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

board/funkwerk/vovpn-gw/config.mk

@@ -0,0 +1,21 @@
+# (C) Copyright 2004
+# Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
+#
+# Support for the Elmeg VoVPN Gateway Module
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+TEXT_BASE = 0xfff00000

board/funkwerk/vovpn-gw/flash.c

@@ -0,0 +1,506 @@
+/*
+ * (C) Copyright 2004
+ * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
+ *
+ * Support for the Elmeg VoVPN Gateway Module
+ * ------------------------------------------
+ * This is a signle bank flashdriver for INTEL 28F320J3, 28F640J3
+ * and 28F128J3A flashs working in 8 Bit mode.
+ *
+ * Most of this code is taken from existing u-boot source code.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+flash_info_t				flash_info[CFG_MAX_FLASH_BANKS];
+
+#define FLASH_CMD_READ_ID		0x90
+#define FLASH_CMD_READ_STATUS		0x70
+#define FLASH_CMD_RESET			0xff
+#define FLASH_CMD_BLOCK_ERASE		0x20
+#define FLASH_CMD_ERASE_CONFIRM		0xd0
+#define FLASH_CMD_CLEAR_STATUS		0x50
+#define FLASH_CMD_SUSPEND_ERASE		0xb0
+#define FLASH_CMD_WRITE			0x40
+#define FLASH_CMD_WRITE_BUFF		0xe8
+#define FLASH_CMD_PROG_RESUME		0xd0
+#define FLASH_CMD_PROTECT		0x60
+#define FLASH_CMD_PROTECT_SET		0x01
+#define FLASH_CMD_PROTECT_CLEAR		0xd0
+#define FLASH_STATUS_DONE		0x80
+
+#define FLASH_WRITE_BUFFER_SIZE		32
+
+#ifdef CFG_FLASH_16BIT
+#define FLASH_WORD_SIZE			unsigned short
+#define FLASH_ID_MASK			0xffff
+#define FLASH_CMD_ADDR_SHIFT		0
+#else
+#define FLASH_WORD_SIZE			unsigned char
+#define FLASH_ID_MASK			0xff
+/* A0 is not used in either 8x or 16x for READ ID */
+#define FLASH_CMD_ADDR_SHIFT		1
+#endif
+
+
+static unsigned long
+flash_get(volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
+{
+	volatile FLASH_WORD_SIZE *p;
+	FLASH_WORD_SIZE value;
+	int i;
+
+	addr[0] = FLASH_CMD_READ_ID;
+
+	/* manufactor */
+	value = addr[0 << FLASH_CMD_ADDR_SHIFT];
+	switch (value) {
+	case (INTEL_MANUFACT & FLASH_ID_MASK):
+		info->flash_id = FLASH_MAN_INTEL;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		*addr = FLASH_CMD_RESET;
+		return (0);
+
+	}
+
+	/* device */
+	value = addr[1 << FLASH_CMD_ADDR_SHIFT];
+	switch (value) {
+	case (INTEL_ID_28F320J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F320J3A;
+		info->sector_count = 32;
+		info->size = 0x00400000;
+		break;
+	case (INTEL_ID_28F640J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F640J3A;
+		info->sector_count = 64;
+		info->size = 0x00800000;
+		break;
+	case (INTEL_ID_28F128J3A & FLASH_ID_MASK):
+		info->flash_id += FLASH_28F128J3A;
+		info->sector_count = 128;
+		info->size = 0x01000000;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		*addr = FLASH_CMD_RESET;
+		return (0);
+	}
+
+	/* setup sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		info->start[i] = (unsigned long)addr + (i * info->size/info->sector_count);
+	}
+
+	/* check protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		p = (volatile FLASH_WORD_SIZE *)(info->start[i]);
+		info->protect[i] = p[2 << FLASH_CMD_ADDR_SHIFT] & 1;
+	}
+
+	/* reset bank */
+	*addr = FLASH_CMD_RESET;
+	return (info->size);
+}
+
+unsigned long
+flash_init(void)
+{
+	unsigned long	size;
+	int		i;
+
+	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+	size = flash_get((volatile FLASH_WORD_SIZE *)CFG_FLASH_BASE, &flash_info[0]);
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf ("## Unknown FLASH Size=0x%08lx\n", size);
+		return (0);
+	}
+
+	/* always protect 1 sector containing the HRCW */
+	flash_protect(FLAG_PROTECT_SET,
+		      flash_info[0].start[0],
+		      flash_info[0].start[1] - 1,
+		      &flash_info[0]);
+
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_MONITOR_FLASH,
+		      CFG_MONITOR_FLASH+CFG_MONITOR_LEN-1,
+		      &flash_info[0]);
+#endif
+#ifdef	CFG_ENV_IS_IN_FLASH
+	flash_protect(FLAG_PROTECT_SET,
+		      CFG_ENV_ADDR,
+		      CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+		      &flash_info[0]);
+#endif
+	return (size);
+}
+
+void
+flash_print_info(flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
+	default:		printf ("Unknown Vendor ");	break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F320J3A:	printf ("28F320JA3 (32 Mbit)\n");
+				break;
+	case FLASH_28F640J3A:	printf ("28F640JA3 (64 Mbit)\n");
+				break;
+	case FLASH_28F128J3A:	printf ("28F128JA3 (128 Mbit)\n");
+				break;
+	default:		printf ("Unknown Chip Type");
+				break;
+	}
+
+	printf ("  Size: %ld MB in %d Sectors\n",
+		info->size >> 20, info->sector_count);
+
+	printf ("  Sector Start Addresses:");
+	for (i=0; i<info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf ("\n   ");
+		printf (" %08lX%s",
+			info->start[i],
+			info->protect[i] ? " (RO)" : "     "
+		);
+	}
+	printf ("\n");
+}
+
+int
+flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	unsigned long start, now, last;
+	int flag, prot, sect;
+	volatile FLASH_WORD_SIZE *addr;
+	FLASH_WORD_SIZE status;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf ("- missing\n");
+		} else {
+			printf ("- no sectors to erase\n");
+		}
+		return (1);
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf ("Cannot erase unknown flash - aborted\n");
+		return (1);
+	}
+
+	prot = 0;
+	for (sect=s_first; sect<=s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf ("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf ("\n");
+	}
+
+	start = get_timer (0);
+	last  = start;
+
+	for (sect = s_first; sect<=s_last; sect++) {
+		if (info->protect[sect]) {
+			continue;
+		}
+
+		addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]);
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+#ifdef DEBUG
+		printf("Erase sector %d at start addr 0x%08X", sect, (unsigned int)info->start[sect]);
+#endif
+
+		*addr = FLASH_CMD_CLEAR_STATUS;
+		*addr = FLASH_CMD_BLOCK_ERASE;
+		*addr = FLASH_CMD_ERASE_CONFIRM;
+
+		/* re-enable interrupts if necessary */
+		if (flag) {
+			enable_interrupts();
+		}
+
+		/* wait at least 80us - let's wait 1 ms */
+		udelay (1000);
+
+		while (((status = *addr) & FLASH_STATUS_DONE) != FLASH_STATUS_DONE) {
+			if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				printf("Flash erase timeout at address %lx\n", info->start[sect]);
+				*addr = FLASH_CMD_SUSPEND_ERASE;
+				*addr = FLASH_CMD_RESET;
+				return (1);
+			}
+
+			/* show that we're waiting */
+			if ((now - last) > 1000) {	/* every second */
+				putc ('.');
+				last = now;
+			}
+		}
+		*addr = FLASH_CMD_RESET;
+	}
+	printf (" done\n");
+	return (0);
+}
+
+static int
+write_buff2( volatile FLASH_WORD_SIZE *dst,
+	     volatile FLASH_WORD_SIZE *src,
+	     unsigned long cnt )
+{
+	unsigned long start;
+	FLASH_WORD_SIZE status;
+	int flag, i;
+
+	start = get_timer (0);
+	while (1) {
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+		dst[0] = FLASH_CMD_WRITE_BUFF;
+		if ((status = *dst) & FLASH_STATUS_DONE) {
+			break;
+		}
+
+		/* re-enable interrupts if necessary */
+		if (flag) {
+			enable_interrupts();
+		}
+
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (-1);
+		}
+	}
+	dst[0] = (FLASH_WORD_SIZE)(cnt - 1);
+	for (i=0; i<cnt; i++) {
+		dst[i] = src[i];
+	}
+	dst[0] = FLASH_CMD_PROG_RESUME;
+
+	if (flag) {
+		enable_interrupts();
+	}
+
+	return( 0 );
+}
+
+static int
+poll_status( volatile FLASH_WORD_SIZE *addr )
+{
+	unsigned long start;
+
+	start = get_timer (0);
+	/* wait for error or finish */
+	while (1) {
+		if (*addr == FLASH_STATUS_DONE) {
+			if (*addr == FLASH_STATUS_DONE) {
+				break;
+			}
+		}
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			*addr = FLASH_CMD_RESET;
+			return (-1);
+		}
+	}
+	*addr = FLASH_CMD_RESET;
+	return (0);
+}
+
+/*
+ * write_buff return values:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - Flash not identified
+ */
+int
+write_buff(flash_info_t *info, uchar *src, ulong udst, ulong cnt)
+{
+	volatile FLASH_WORD_SIZE *addr, *dst;
+	unsigned long bcnt;
+	int flag, i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		return (4);
+	}
+
+	addr = (volatile FLASH_WORD_SIZE *)(info->start[0]);
+	dst = (volatile FLASH_WORD_SIZE *) udst;
+
+#ifdef CFG_FLASH_16BIT
+#error NYI
+#else
+	while (cnt > 0) {
+		/* Check if buffer write is possible */
+		if (cnt > 1 && (((unsigned long)dst & (FLASH_WRITE_BUFFER_SIZE - 1)) == 0)) {
+			bcnt = cnt > FLASH_WRITE_BUFFER_SIZE ? FLASH_WRITE_BUFFER_SIZE : cnt;
+			/* Check if Flash is (sufficiently) erased */
+			for (i=0; i<bcnt; i++) {
+				if ((dst[i] & src[i]) != src[i]) {
+					return (2);
+				}
+			}
+			if (write_buff2( dst,src,bcnt ) != 0) {
+				addr[0] = FLASH_CMD_READ_STATUS;
+			}
+			if (poll_status( dst ) != 0) {
+				return (1);
+			}
+			cnt -= bcnt;
+			dst += bcnt;
+			src += bcnt;
+			continue;
+		}
+
+		/* Check if Flash is (sufficiently) erased */
+		if ((*dst & *src) != *src) {
+			return (2);
+		}
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+		addr[0] = FLASH_CMD_ERASE_CONFIRM;
+		addr[0] = FLASH_CMD_WRITE;
+		*dst++ = *src++;
+		/* re-enable interrupts if necessary */
+		if (flag) {
+			enable_interrupts();
+		}
+
+		if (poll_status( dst ) != 0) {
+			return (1);
+		}
+		cnt --;
+	}
+#endif
+	return (0);
+}
+
+int
+flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+	volatile FLASH_WORD_SIZE *addr;
+	unsigned long start;
+
+	addr = (volatile FLASH_WORD_SIZE *)(info->start[sector]);
+	*addr = FLASH_CMD_CLEAR_STATUS;
+	*addr = FLASH_CMD_PROTECT;
+
+	if(prot) {
+		*addr = FLASH_CMD_PROTECT_SET;
+	} else {
+		*addr = FLASH_CMD_PROTECT_CLEAR;
+	}
+
+	/* wait for error or finish */
+	start = get_timer (0);
+	while(!(addr[0] & FLASH_STATUS_DONE)){
+		if (get_timer(start) > CFG_FLASH_ERASE_TOUT) {
+			printf("Flash protect timeout at address %lx\n",  info->start[sector]);
+			addr[0] = FLASH_CMD_RESET;
+			return (1);
+		}
+	}
+
+	/* Set software protect flag */
+	info->protect[sector] = prot;
+	*addr = FLASH_CMD_RESET;
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Support for flash file system (JFFS2)
+ *
+ * We use custom partition info function because we have to fit the
+ * file system image between first sector (containing hard reset
+ * configuration word) and the sector containing U-Boot image. Standard
+ * partition info function does not allow for last sector specification
+ * and assumes that the file system occupies flash bank up to and
+ * including bank's last sector.
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CFG_JFFS_CUSTOM_PART)
+#error TODO
+
+#ifndef CFG_JFFS2_FIRST_SECTOR
+#define CFG_JFFS2_FIRST_SECTOR 0
+#endif
+#ifndef CFG_JFFS2_FIRST_BANK
+#define CFG_JFFS2_FIRST_BANK 0
+#endif
+#ifndef CFG_JFFS2_NUM_BANKS
+#define CFG_JFFS2_NUM_BANKS 1
+#endif
+#define CFG_JFFS2_LAST_BANK (CFG_JFFS2_FIRST_BANK + CFG_JFFS2_NUM_BANKS - 1)
+
+#include <jffs2/jffs2.h>
+
+static struct part_info partition;
+
+struct part_info *jffs2_part_info(int part_num)
+{
+	int i;
+
+	if (part_num == 0) {
+		if (partition.usr_priv == 0) {
+			partition.offset =
+				(unsigned char *) flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR];
+			for (i = CFG_JFFS2_FIRST_BANK; i <= CFG_JFFS2_LAST_BANK; i++)
+				partition.size += flash_info[i].size;
+			partition.size -=
+				flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR] -
+				flash_info[CFG_JFFS2_FIRST_BANK].start[0];
+#ifdef CFG_JFFS2_LAST_SECTOR
+			i = flash_info[CFG_JFFS2_LAST_BANK].sector_count - 1;
+			partition.size -=
+				flash_info[CFG_JFFS2_LAST_BANK].start[i] -
+				flash_info[CFG_JFFS2_LAST_BANK].start[CFG_JFFS2_LAST_SECTOR];
+#endif
+
+			partition.usr_priv = (void *)1;
+		}
+		return &partition;
+	}
+	return 0;
+}
+
+#endif /* JFFS2 */

board/funkwerk/vovpn-gw/m88e6060.c

@@ -0,0 +1,262 @@
+/*
+ * (C) Copyright 2004
+ * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
+ *
+ * Support for the Elmeg VoVPN Gateway Module
+ * ------------------------------------------
+ * Initialize Marvell M88E6060 Switch
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <asm/m8260_pci.h>
+#include <net.h>
+#include <miiphy.h>
+
+#include "m88e6060.h"
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+static int		prtTab[M88X_PRT_CNT] = { 8, 9, 10, 11, 12, 13 };
+static int		phyTab[M88X_PHY_CNT] = { 0, 1, 2, 3, 4 };
+
+static m88x_regCfg_t	prtCfg0[] = {
+	{  4, 0x3e7c, 0x8000 },
+	{  4, 0x3e7c, 0x8003 },
+	{  6, 0x0fc0, 0x001e },
+	{ -1, 0xffff, 0x0000 }
+};
+
+static m88x_regCfg_t	prtCfg1[] = {
+	{  4, 0x3e7c, 0x8000 },
+	{  4, 0x3e7c, 0x8003 },
+	{  6, 0x0fc0, 0x001d },
+	{ -1, 0xffff, 0x0000 }
+};
+
+static m88x_regCfg_t	prtCfg2[] = {
+	{  4, 0x3e7c, 0x8000 },
+	{  4, 0x3e7c, 0x8003 },
+	{  6, 0x0fc0, 0x001b },
+	{ -1, 0xffff, 0x0000 }
+};
+
+static m88x_regCfg_t	prtCfg3[] = {
+	{  4, 0x3e7c, 0x8000 },
+	{  4, 0x3e7c, 0x8003 },
+	{  6, 0x0fc0, 0x0017 },
+	{ -1, 0xffff, 0x0000 }
+};
+
+static m88x_regCfg_t	prtCfg4[] = {
+	{  4, 0x3e7c, 0x8000 },
+	{  4, 0x3e7c, 0x8003 },
+	{  6, 0x0fc0, 0x000f },
+	{ -1, 0xffff, 0x0000 }
+};
+
+static m88x_regCfg_t	*prtCfg[M88X_PRT_CNT] = {
+	prtCfg0,prtCfg1,prtCfg2,prtCfg3,prtCfg4,NULL
+};
+
+static m88x_regCfg_t	phyCfgX[] = {
+	{  4, 0xfa1f, 0x01e0 },
+	{  0, 0x213f, 0x1200 },
+	{ 24, 0x81ff, 0x1200 },
+	{ -1, 0xffff, 0x0000 }
+};
+
+static m88x_regCfg_t	*phyCfg[M88X_PHY_CNT] = {
+	phyCfgX,phyCfgX,phyCfgX,phyCfgX,NULL
+};
+
+#if 0
+static void
+m88e6060_dump( int devAddr )
+{
+	int		i, j;
+	unsigned short	val[6];
+
+	printf( "M88E6060 Register Dump\n" );
+	printf( "====================================\n" );
+	printf( "PortNo    0    1    2    3    4    5\n" );
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_STAT,&val[i] );
+	printf( "STAT   %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_ID,&val[i] );
+	printf( "ID     %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_CNTL,&val[i] );
+	printf( "CNTL   %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_VLAN,&val[i] );
+	printf( "VLAN   %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_PAV,&val[i] );
+	printf( "PAV    %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_RX,&val[i] );
+	printf( "RX     %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	for (i=0; i<6; i++)
+		miiphy_read( devAddr+prtTab[i],M88X_PRT_TX,&val[i] );
+	printf( "TX     %04hx %04hx %04hx %04hx %04hx %04hx\n",
+		val[0],val[1],val[2],val[3],val[4],val[5] );
+
+	printf( "------------------------------------\n" );
+	printf( "PhyNo     0    1    2    3    4\n" );
+	for (i=0; i<9; i++) {
+		for (j=0; j<5; j++) {
+			miiphy_read( devAddr+phyTab[j],i,&val[j] );
+		}
+		printf( "0x%02x   %04hx %04hx %04hx %04hx %04hx\n",
+			i,val[0],val[1],val[2],val[3],val[4] );
+	}
+	for (i=0x10; i<0x1d; i++) {
+		for (j=0; j<5; j++) {
+			miiphy_read( devAddr+phyTab[j],i,&val[j] );
+		}
+		printf( "0x%02x   %04hx %04hx %04hx %04hx %04hx\n",
+			i,val[0],val[1],val[2],val[3],val[4] );
+	}
+}
+#endif
+
+int
+m88e6060_initialize( int devAddr )
+{
+	static char	*_f = "m88e6060_initialize:";
+	m88x_regCfg_t	*p;
+	int		err;
+	int		i;
+	unsigned short	val;
+
+	/*** reset all phys into powerdown ************************************/
+	for (i=0, err=0; i<M88X_PHY_CNT; i++) {
+		err += miiphy_read( devAddr+phyTab[i],M88X_PHY_CNTL,&val );
+		/* keep SpeedLSB, Duplex */
+		val &= 0x2100;
+		/* set SWReset, AnegEn, PwrDwn, RestartAneg */
+		val |= 0x9a00;
+		err += miiphy_write( devAddr+phyTab[i],M88X_PHY_CNTL,val );
+	}
+	if (err) {
+		printf( "%s [ERR] reset phys\n",_f );
+		return( -1 );
+	}
+
+	/*** disable all ports ************************************************/
+	for (i=0, err=0; i<M88X_PRT_CNT; i++) {
+		err += miiphy_read( devAddr+prtTab[i],M88X_PRT_CNTL,&val );
+		val &= 0xfffc;
+		err += miiphy_write( devAddr+prtTab[i],M88X_PRT_CNTL,val );
+	}
+	if (err) {
+		printf( "%s [ERR] disable ports\n",_f );
+		return( -1 );
+	}
+
+	/*** initialize switch ************************************************/
+	/* set switch mac addr */
+#define ea eth_get_dev()->enetaddr
+	val = (ea[4] <<  8) | ea[5];
+	err = miiphy_write( devAddr+15,M88X_GLB_MAC45,val );
+	val = (ea[2] <<  8) | ea[3];
+	err += miiphy_write( devAddr+15,M88X_GLB_MAC23,val );
+	val = (ea[0] <<  8) | ea[1];
+#undef ea
+	val &= 0xfeff;		/* clear DiffAddr */
+	err += miiphy_write( devAddr+15,M88X_GLB_MAC01,val );
+	if (err) {
+		printf( "%s [ERR] switch mac address register\n",_f );
+		return( -1 );
+	}
+
+	/* !DiscardExcessive, MaxFrameSize, CtrMode */
+	err = miiphy_read( devAddr+15,M88X_GLB_CNTL,&val );
+	val &= 0xd870;
+	val |= 0x0500;
+	err += miiphy_write( devAddr+15,M88X_GLB_CNTL,val );
+	if (err) {
+		printf( "%s [ERR] switch global control register\n",_f );
+		return( -1 );
+	}
+
+	/* LernDis off, ATUSize 1024, AgeTime 5min */
+	err = miiphy_read( devAddr+15,M88X_ATU_CNTL,&val );
+	val &= 0x000f;
+	val |= 0x2130;
+	err += miiphy_write( devAddr+15,M88X_ATU_CNTL,val );
+	if (err) {
+		printf( "%s [ERR] atu control register\n",_f );
+		return( -1 );
+	}
+
+	/*** initialize ports *************************************************/
+	for (i=0; i<M88X_PRT_CNT; i++) {
+		if ((p = prtCfg[i]) == NULL) {
+			continue;
+		}
+		while (p->reg != -1) {
+			err = 0;
+			err += miiphy_read( devAddr+prtTab[i],p->reg,&val );
+			val &= p->msk;
+			val |= p->val;
+			err += miiphy_write( devAddr+prtTab[i],p->reg,val );
+			if (err) {
+				printf( "%s [ERR] config port %d register %d\n",_f,i,p->reg );
+				/* XXX what todo */
+			}
+			p++;
+		}
+	}
+
+	/*** initialize phys **************************************************/
+	for (i=0; i<M88X_PHY_CNT; i++) {
+		if ((p = phyCfg[i]) == NULL) {
+			continue;
+		}
+		while (p->reg != -1) {
+			err = 0;
+			err += miiphy_read( devAddr+phyTab[i],p->reg,&val );
+			val &= p->msk;
+			val |= p->val;
+			err += miiphy_write( devAddr+phyTab[i],p->reg,val );
+			if (err) {
+				printf( "%s [ERR] config phy %d register %d\n",_f,i,p->reg );
+				/* XXX what todo */
+			}
+			p++;
+		}
+	}
+	udelay(100000);
+	return( 0 );
+}
+#endif

board/funkwerk/vovpn-gw/m88e6060.h

@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2004
+ * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
+ *
+ * Support for the Elmeg VoVPN Gateway Module
+ * ------------------------------------------
+ * Initialize Marvell M88E6060 Switch
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _INC_m88e6060_h_
+#define _INC_m88e6060_h_
+
+/* ************************************************************************** */
+/* *** DEFINES ************************************************************** */
+
+/* switch hw */
+#define M88X_PRT_CNT			6
+#define M88X_PHY_CNT			5
+
+/* phy register offsets */
+#define M88X_PHY_CNTL			0x00
+#define M88X_PHY_STAT			0x00
+#define M88X_PHY_ID0			0x02
+#define M88X_PHY_ID1			0x03
+#define M88X_PHY_ANEG_ADV		0x04
+#define M88X_PHY_LPA			0x05
+#define M88X_PHY_ANEG_EXP		0x06
+#define M88X_PHY_NPT			0x07
+#define M88X_PHY_LPNP			0x08
+
+/* port register offsets */
+#define M88X_PRT_STAT			0x00
+#define M88X_PRT_ID			0x03
+#define M88X_PRT_CNTL			0x04
+#define M88X_PRT_VLAN			0x06
+#define M88X_PRT_PAV			0x0b
+#define M88X_PRT_RX			0x10
+#define M88X_PRT_TX			0x11
+
+/* global/atu register offsets */
+#define M88X_GLB_STAT			0x00
+#define M88X_GLB_MAC01			0x01
+#define M88X_GLB_MAC23			0x02
+#define M88X_GLB_MAC45			0x03
+#define M88X_GLB_CNTL			0x04
+#define M88X_ATU_CNTL			0x0a
+#define M88X_ATU_OP			0x0b
+
+/* id0 register - 0x02 */
+#define M88X_PHY_ID0_VALUE		0x0141
+
+/* id1 register - 0x03 */
+#define M88X_PHY_ID1_VALUE		0x0c80		/* without revision ! */
+
+
+/* misc */
+#define M88E6060_ID		((M88X_PHY_ID0_VALUE<<16) | M88X_PHY_ID1_VALUE)
+
+/* ************************************************************************** */
+/* *** TYPEDEFS ************************************************************* */
+
+typedef struct {
+	int		reg;
+	unsigned short	msk;
+	unsigned short	val;
+} m88x_regCfg_t;
+
+/* ************************************************************************** */
+/* *** PROTOTYPES *********************************************************** */
+
+extern int		m88e6060_initialize( int );
+
+#endif	/* _INC_m88e6060_h_ */

board/funkwerk/vovpn-gw/u-boot.lds

@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2001-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Modified by Yuli Barcohen <yuli@arabellasw.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)

board/funkwerk/vovpn-gw/vovpn-gw.c

@@ -0,0 +1,375 @@
+/*
+ * (C) Copyright 2004
+ * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
+ *
+ * Support for the Elmeg VoVPN Gateway Module
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ioports.h>
+#include <mpc8260.h>
+#include <asm/m8260_pci.h>
+#include <miiphy.h>
+
+#include "m88e6060.h"
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+    /* Port A configuration */
+    {	/*	     conf ppar psor pdir podr pdat */
+	/* PA31 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1252           */
+	/* PA30 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    BP_RES           */
+	/* PA29 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1253           */
+	/* PA28 */ { 1,   1,   1,   1,   0,   0 }, /* FCC1   RMII TX_EN       */
+	/* PA27 */ { 1,   1,   1,   0,   0,   0 }, /* FCC1   RMII CRS_DV      */
+	/* PA26 */ { 1,   1,   1,   0,   0,   0 }, /* FCC1   RMII RX_ERR      */
+	/* PA25 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    HWID             */
+	/* PA24 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    HWID             */
+	/* PA23 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    HWID             */
+	/* PA22 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    HWID             */
+	/* PA21 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    HWID             */
+	/* PA20 */ { 1,   0,   0,   1,   0,   1 }, /* GPO    LED STATUS       */
+	/* PA19 */ { 1,   1,   0,   1,   0,   0 }, /* FCC1   RMII TxD[1]      */
+	/* PA18 */ { 1,   1,   0,   1,   0,   0 }, /* FCC1   RMII TxD[0]      */
+	/* PA17 */ { 1,   1,   0,   0,   0,   0 }, /* FCC1   RMII RxD[0]      */
+	/* PA16 */ { 1,   1,   0,   0,   0,   0 }, /* FCC1   RMII RxD[1]      */
+	/* PA15 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1255           */
+	/* PA14 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP????           */
+	/* PA13 */ { 1,   0,   0,   1,   0,   1 }, /* GPO    EN_BCTL1 XXX jse */
+	/* PA12 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    SWITCH RESET     */
+	/* PA11 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    DSP SL1 RESET    */
+	/* PA10 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    DSP SL2 RESET    */
+	/* PA9  */ { 1,   1,   0,   1,   0,   0 }, /* SMC2   TXD              */
+	/* PA8  */ { 1,   1,   0,   0,   0,   0 }, /* SMC2   RXD              */
+	/* PA7  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA6  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA5  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA4  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA3  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA2  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA1  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exit       */
+	/* PA0  */ { 0,   0,   0,   0,   0,   0 }  /* pin does not exit       */
+    },
+
+    /* Port B configuration */
+    {   /*	     conf ppar psor pdir podr pdat */
+	/* PB31 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1257           */
+	/* PB30 */ { 1,   1,   0,   0,   0,   0 }, /* FCC2   RMII CRS_DV      */
+	/* PB29 */ { 1,   1,   1,   1,   0,   0 }, /* FCC2   RMII TX_EN       */
+	/* PB28 */ { 1,   1,   0,   0,   0,   0 }, /* FCC2   RMII RX_ERR      */
+	/* PB27 */ { 1,   1,   1,   0,   1,   0 }, /* TDM_B2 L1TXD XXX val=0  */
+	/* PB26 */ { 1,   1,   1,   0,   1,   0 }, /* TDM_B2 L1RXD XXX val,dr */
+	/* PB25 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1259           */
+	/* PB24 */ { 1,   1,   1,   0,   0,   0 }, /* TDM_B2 L1RSYNC          */
+	/* PB23 */ { 1,   1,   0,   1,   0,   0 }, /* FCC2   RMII TxD[1]      */
+	/* PB22 */ { 1,   1,   0,   1,   0,   0 }, /* FCC2   RMII TxD[0]      */
+	/* PB21 */ { 1,   1,   0,   0,   0,   0 }, /* FCC2   RMII RxD[0]      */
+	/* PB20 */ { 1,   1,   0,   0,   0,   0 }, /* FCC2   RMII RxD[1]      */
+	/* PB19 */ { 1,   0,   0,   1,   0,   1 }, /* GPO    PHY MDC          */
+	/* PB18 */ { 1,   0,   0,   0,   0,   0 }, /* GPIO   PHY MDIO         */
+	/* PB17 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB16 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB15 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB14 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB13 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB12 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB11 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB10 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB9  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB8  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB7  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB6  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB5  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB4  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB3  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB2  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB1  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PB0  */ { 0,   0,   0,   0,   0,   0 }  /* pin does not exist      */
+    },
+
+    /* Port C */
+    {   /*	     conf ppar psor pdir podr pdat */
+	/* PC31 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PC30 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PC29 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1183           */
+	/* PC28 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1184           */
+	/* PC27 */ { 1,   1,   0,   0,   0,   0 }, /* CLK5   TDM_A1 RX        */
+	/* PC26 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1185           */
+	/* PC25 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1178           */
+	/* PC24 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1186           */
+	/* PC23 */ { 1,   1,   0,   0,   0,   0 }, /* CLK9   TDM_B2 RX        */
+	/* PC22 */ { 1,   1,   0,   0,   0,   0 }, /* CLK10  FCC1 RMII REFCLK */
+	/* PC21 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1187           */
+	/* PC20 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1182           */
+	/* PC19 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1188           */
+	/* PC18 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    HW RESET         */
+	/* PC17 */ { 1,   1,   0,   1,   0,   0 }, /* BRG8   SWITCH CLKIN     */
+	/* PC16 */ { 1,   1,   0,   0,   0,   0 }, /* CLK16  FCC2 RMII REFCLK */
+	/* PC15 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL1_MTYPE_3      */
+	/* PC14 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL1_MTYPE_2      */
+	/* PC13 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL1_MTYPE_1      */
+	/* PC12 */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL1_MTYPE_0      */
+	/* PC11 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1176           */
+	/* PC10 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1177           */
+	/* PC9  */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL2_MTYPE_3      */
+	/* PC8  */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL2_MTYPE_2      */
+	/* PC7  */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL2_MTYPE_1      */
+	/* PC6  */ { 1,   0,   0,   0,   0,   0 }, /* GPI    SL2_MTYPE_0      */
+	/* PC5  */ { 1,   1,   0,   1,   0,   0 }, /* SMC1   TXD              */
+	/* PC4  */ { 1,   1,   0,   0,   0,   0 }, /* SMC1   RXD              */
+	/* PC3  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PC2  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PC1  */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1192           */
+	/* PC0  */ { 1,   0,   0,   0,   0,   0 }, /* GPI    RACK             */
+    },
+
+    /* Port D */
+    {   /*	     conf ppar psor pdir podr pdat */
+	/* PD31 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1193           */
+	/* PD30 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1194           */
+	/* PD29 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1195           */
+	/* PD28 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD27 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD26 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD25 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1179           */
+	/* PD24 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1180           */
+	/* PD23 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1181           */
+	/* PD22 */ { 1,   1,   1,   0,   1,   0 }, /* TDM_A2 L1TXD            */
+	/* PD21 */ { 1,   1,   1,   0,   1,   0 }, /* TDM_A2 L1RXD            */
+	/* PD20 */ { 1,   1,   1,   0,   0,   0 }, /* TDM_A2 L1RSYNC          */
+	/* PD19 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1196           */
+	/* PD18 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1197           */
+	/* PD17 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1198           */
+	/* PD16 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1199           */
+	/* PD15 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1250           */
+	/* PD14 */ { 1,   0,   0,   1,   0,   0 }, /* GPO    TP1251           */
+	/* PD13 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD12 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD11 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD10 */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD9  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD8  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD7  */ { 0,   0,   0,   1,   0,   0 }, /* GPO    FL_BYTE          */
+	/* PD6  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD5  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD4  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD3  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD2  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD1  */ { 0,   0,   0,   0,   0,   0 }, /* pin does not exist      */
+	/* PD0  */ { 0,   0,   0,   0,   0,   0 }  /* pin does not exist      */
+    }
+};
+
+void reset_phy (void)
+{
+	volatile ioport_t *iop;
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+	int i;
+	unsigned short val;
+#endif
+
+	iop = ioport_addr((immap_t *)CFG_IMMR, 0);
+
+	/* Reset the PHY */
+	iop->pdat &= 0xfff7ffff;	/* PA12 = |SWITCH_RESET */
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+	udelay(20000);
+	iop->pdat |= 0x00080000;
+	for (i=0; i<100; i++) {
+		udelay(20000);
+		if (miiphy_read( CFG_PHY_ADDR,2,&val ) == 0) {
+			break;
+		}
+	}
+	/* initialize switch */
+	m88e6060_initialize( CFG_PHY_ADDR );
+#endif
+}
+
+static unsigned long UPMATable[] = {
+	0x8fffec00,  0x0ffcfc00,  0x0ffcfc00,  0x0ffcfc00, //Words 0 to 3
+	0x0ffcfc04,  0x3ffdfc00,  0xfffffc01,  0xfffffc01, //Words 4 to 7
+	0xfffffc00,  0xfffffc04,  0xfffffc01,  0xfffffc00, //Words 8 to 11
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, //Words 12 to 15
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, //Words 16 to 19
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01, //Words 20 to 23
+	0x8fffec00,  0x00fffc00,  0x00fffc00,  0x00fffc00, //Words 24 to 27
+	0x0ffffc04,  0xfffffc01,  0xfffffc01,  0xfffffc01, //Words 28 to 31
+	0xfffffc00,  0xfffffc01,  0xfffffc01,  0xfffffc00, //Words 32 to 35
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, //Words 36 to 39
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, //Words 40 to 43
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01, //Words 44 to 47
+	0xfffffc00,  0xfffffc04,  0xfffffc01,  0xfffffc00, //Words 48 to 51
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc00, //Words 52 to 55
+	0xfffffc00,  0xfffffc00,  0xfffffc00,  0xfffffc01, //Words 56 to 59
+	0xffffec00,  0xffffec04,  0xffffec00,  0xfffffc01  //Words 60 to 63
+};
+
+int board_early_init_f (void)
+{
+	volatile immap_t *immap;
+	volatile memctl8260_t *memctl;
+	volatile unsigned char *dummy;
+	int i;
+
+	immap = (immap_t *) CFG_IMMR;
+	memctl = &immap->im_memctl;
+
+#if 0
+	/* CS2-5 - DSP via UPMA */
+	dummy = (volatile unsigned char *) (memctl->memc_br2 & BRx_BA_MSK);
+	memctl->memc_mar = 0;
+	memctl->memc_mamr = MxMR_OP_WARR;
+	for (i = 0; i < 64; i++) {
+		memctl->memc_mdr = UPMATable[i];
+		*dummy = 0;
+	}
+	memctl->memc_mamr = 0x00044440;
+#else
+	/* CS7 - DPRAM via UPMA */
+	dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK);
+	memctl->memc_mar = 0;
+	memctl->memc_mamr = MxMR_OP_WARR;
+	for (i = 0; i < 64; i++) {
+		memctl->memc_mdr = UPMATable[i];
+		*dummy = 0;
+	}
+	memctl->memc_mamr = 0x00044440;
+#endif
+	return 0;
+}
+
+int misc_init_r (void)
+{
+	volatile ioport_t *iop;
+	unsigned char temp;
+#if 0
+	/* DUMP UPMA RAM */
+	volatile immap_t *immap;
+	volatile memctl8260_t *memctl;
+	volatile unsigned char *dummy;
+	unsigned char c;
+	int i;
+
+	immap = (immap_t *) CFG_IMMR;
+	memctl = &immap->im_memctl;
+
+
+	dummy = (volatile unsigned char *) (memctl->memc_br7 & BRx_BA_MSK);
+	memctl->memc_mar = 0;
+	memctl->memc_mamr = MxMR_OP_RARR;
+	for (i = 0; i < 64; i++) {
+		c = *dummy;
+		printf( "UPMA[%02d]: 0x%08lx,0x%08lx: 0x%08lx\n",i,
+		        memctl->memc_mamr,
+		        memctl->memc_mar,
+		        memctl->memc_mdr );
+	}
+	memctl->memc_mamr = 0x00044440;
+#endif
+	/* enable buffers (DSP, DPRAM) */
+	iop = ioport_addr((immap_t *)CFG_IMMR, 0);
+	iop->pdat &= 0xfffbffff;	/* PA13 = |EN_M_BCTL1 */
+
+	/* destroy DPRAM magic */
+	*(volatile unsigned char *)0xf0500000 = 0x00;
+
+	/* clear any pending DPRAM irq */
+	temp = *(volatile unsigned char *)0xf05003ff;
+
+	/* write module-id into DPRAM */
+	*(volatile unsigned char *)0xf0500201 = 0x50;
+
+	return 0;
+}
+
+#if defined(CONFIG_HAVE_OWN_RESET)
+int
+do_reset (void *cmdtp, int flag, int argc, char *argv[])
+{
+	volatile ioport_t *iop;
+
+	iop = ioport_addr((immap_t *)CFG_IMMR, 2);
+	iop->pdat |= 0x00002000;	/* PC18 = HW_RESET */
+	return 1;
+}
+#endif	/* CONFIG_HAVE_OWN_RESET */
+
+#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
+
+long int initdram (int board_type)
+{
+#ifndef CFG_RAMBOOT
+	volatile immap_t *immap;
+	volatile memctl8260_t *memctl;
+	volatile uchar *ramaddr;
+	int i;
+	uchar c;
+
+	immap = (immap_t *) CFG_IMMR;
+	memctl = &immap->im_memctl;
+	ramaddr = (uchar *) CFG_SDRAM_BASE;
+	c = 0xff;
+
+	immap->im_siu_conf.sc_ppc_acr  = 0x02;
+	immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
+	immap->im_siu_conf.sc_ppc_alrl = 0x89abcdef;
+	immap->im_siu_conf.sc_tescr1   = 0x00000000;
+	immap->im_siu_conf.sc_tescr2   = 0x00000000;
+
+	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_or1 = CFG_OR1_PRELIM;
+	memctl->memc_br1 = CFG_SDRAM_BASE | CFG_BR1_PRELIM;
+
+	/* Precharge all banks */
+	memctl->memc_psdmr = CFG_PSDMR | 0x28000000;
+	*ramaddr = c;
+
+	/* CBR refresh */
+	memctl->memc_psdmr = CFG_PSDMR | 0x08000000;
+	for (i = 0; i < 8; i++)
+		*ramaddr = c;
+
+	/* Mode Register write */
+	memctl->memc_psdmr = CFG_PSDMR | 0x18000000;
+	*ramaddr = c;
+
+	/* Refresh enable */
+	memctl->memc_psdmr = CFG_PSDMR | 0x40000000;
+	*ramaddr = c;
+#endif /* CFG_RAMBOOT */
+
+	return (CFG_SDRAM_SIZE);
+}
+
+int checkboard (void)
+{
+#ifdef CONFIG_CLKIN_66MHz
+	puts ("Board: Elmeg VoVPN Gateway Module (66MHz)\n");
+#else
+	puts ("Board: Elmeg VoVPN Gateway Module (100MHz)\n");
+#endif
+	return 0;
+}

board/gcplus/Makefile

@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(BOARD).a
 
 OBJS	:= gcplus.o flash.o
-SOBJS	:= memsetup.o
+SOBJS	:= lowlevel_init.o
 
 $(LIB):	$(OBJS) $(SOBJS)
 	$(AR) crv $@ $(OBJS) $(SOBJS)

board/gcplus/lowlevel_init.S

@@ -29,11 +29,11 @@
 #include "version.h"
 
 
-	.globl	memsetup
-memsetup:
+	.globl	lowlevel_init
+lowlevel_init:
 	/* The ADS GC+ for Linux Boot Rom Ver. 1.73 does memory init for us.
 	 * However the darn thing leaves the MMU enabled before handing control
-	 * over to us. So we need to disable the MMU and we use memsetup
+	 * over to us. So we need to disable the MMU and we use lowlevel_init
 	 * to do it.
 	 */
 

board/hidden_dragon/Makefile

@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2000-2005
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS =  $(BOARD).o flash.o
+
+$(LIB):	.depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend:	Makefile $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################

board/hidden_dragon/README

@@ -0,0 +1,60 @@
+U-Boot for Hidden Dragon board
+------------------------------
+
+Hidden Dragon is a MPC824x-based board by Motorola. For the most
+part it is similar to Sandpoint8245 board. So unless otherwise
+mentioned, the codes in this directory are adapted from ../sandpoint
+directory.
+
+Apparently there are very few of this board out there. Even Motorola
+website does not have any info on it.
+
+RAM:
+  start = 0x0000 0000
+  size	= 0x0200 0000 (32 MB)
+
+Flash:
+  BANK ONE:
+    start = 0xFFE0 0000
+    size  = 0x0020 0000 (2 MB)
+    flash chip = 29LV160TE (1x16 Mbits or 2x8 Mbits)
+    flash sectors = 16K, 2x8K, 32K, 31x64K
+
+  BANK TWO:
+    NONE
+
+The processor interrupt vectors reside on the first 256 bytes
+starting from address 0xFFF00000. The "reset vector" (first
+instruction executed after reset) is located on 0xFFF0 0100.
+
+U-Boot is configured to reside in flash starting at the address of
+0xFFF00000. The environment space is located in flash separately from
+U-Boot, at the second sector of the first flash bank, starting from
+0xFFE04000 until 0xFFE06000 (8KB).
+
+Network:
+  - RTL8139 chip on the base board	  (SUPPORTED)
+  - RTL8129 chip on the processor board	  (NOT SUPPORTED)
+
+Serial:
+  - Two NS16550 compatible UART on the processor board	(SUPPORTED)
+  - One NS16550 compatible UART on the base board	(UNTESTED)
+
+Misc:
+  VIA686A PCI SuperIO peripheral controller
+  - 2 USB ports		    (UNTESTED)
+  - 2 PS2 ports		    (UNTESTED)
+  - Parallel port	    (UNTESTED)
+  - IDE & floppy interface  (UNTESTED)
+
+  S3 Savage4 video card	    (UNTESTED)
+
+TODO:
+-----
+- Support for the VIA686A based peripherals
+- The RTL8139 driver frequently gives rx error.
+- Support for RTL8129 network controller. (Why is the support removed from
+  rtl8139.c driver?)
+
+(C) Copyright 2004
+Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com