Display Serial Interface (DSI) host can usefully be modelled
as their own uclass.
DSI defines a serial bus and a communication protocol
between the host and the device (panel, bridge).
Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
If an exception occurs in a loaded image and the relocation offset is
unknown, it is helpful to know the instructions pointed to by the
program counter. This patch adds the missing output.
A possible output is:
Code: 910c4021 aa1303e0 f9400662 d63f0040 (e7f7defb)
The parentheses indicate the instruction causing the exception.
The output can be disassembled using scripts/decodecode:
echo 'Code: 90000360 9100b800 94002782 17ffff8f (e7f7defb)' | \
ARCH=arm64 scripts/decodecode
Code: 90000360 9100b800 94002782 17ffff8f (e7f7defb)
All code
========
0: 90000360 adrp x0, 0x6c000
4: 9100b800 add x0, x0, #0x2e
8: 94002782 bl 0x9e10
c: 17ffff8f b 0xfffffffffffffe48
10:* e7f7defb .inst 0xe7f7defb ; undefined <-- trapping instruction
Code starting with the faulting instruction
===========================================
0: e7f7defb .inst 0xe7f7defb ; undefined
We already have implemented the same for armv7.
For testing command 'exception undefined' can be used.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
readb is unconditionally defined earlier in io.h, so there's no point
checking whether it's undefined.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
No ARM board seems to define __mem_pci - and if it did, one would get tons of
./arch/arm/include/asm/io.h:307:0: warning: "readl" redefined
warnings, because readl and friends are unconditionally defined
earlier in io.h. Moreover, the redefinitions lack the memory barriers
that the first definitions have. So I'm guessing this is practically
dead code.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
If there is any failure during IOdelay recalibration sequence, IOs are
not guaranteed to behave as expected. So hang on any failure during the
sequence.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
When an error is reported in __recalibrate_iodelay_start(), de-isolation
of IO doesn't happen. Because of this, undefined behaviour is observed
on many peripherals without any error. So make sure io is out of isolation
at the end of iodelay recalibration.
Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Main uart0 is used as debug console by both R5SPL and A72 bootloader and
Linux. So mark it as shared device so that power-domain request is
successful by both cores.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
AM335x-ICE boards contain the CDCE913 clock synthesizer, and their
reset crystal capacitance load value of 10pF is wrong leading into
lost packets in certain networking tests. Add DT data for this
device, and probe it from the board file to program the crystal
capacitance load value to 0pF to avoid any problems.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
AM43xx-IDK boards contain the CDCE913 clock synthesizer, and their
reset crystal capacitance load value of 10pF is wrong leading into
lost packets in certain networking tests. Add DT data for this
device, and probe it from the board file to program the crystal
capacitance load value to 0pF to avoid any problems.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
AM57xx-IDK boards contain the CDCE913 clock synthesizer, and their
reset crystal capacitance load value of 10pF is wrong leading into
lost packets in certain networking tests. Add DT data for this
device, and probe it from the board file to program the crystal
capacitance load value to 0pF to avoid any problems.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
- add BOARD_LATE_INIT function calls in board.c
- add swi_status detection in board.c
- mux: add guardian interfaces to single pinmux structure
- am33xx, kconfig: add BOARD_LATE_INIT for GUARDIAN board
Signed-off-by: Moses Christopher <BollavarapuMoses.Christopher@in.bosch.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Before the priming begins, we need to disable RMW (Read Modify Write)
and disable ECC verification for read accesses. By default, the EMIF
tool enables RMW and read accesses in the EMIF_ECC_CTRL_REG.
Signed-off-by: Krunal Bhargav <k-bhargav@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
If ECC is enabled, we need to ensure interleaving is disabled for higher
address space.
Signed-off-by: Krunal Bhargav <k-bhargav@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
ecc_address_range registers contains the start address and end address
of the DDR address space. But the ddr driver is assuming the register
contains the start address and size of the DDR address space. Because
of this the ecc enabling is failing for the 2nd range of ecc addresses.
Fix this calculation.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This follows the linux header rules to avoid conflict bitfields.
Tested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
This adds PCIe and its PHY nodes for MT7623.
Tested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
This commit add a spi-nor device in the bcm96850xref device tree.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Kursad Oney <kursad.oney@broadcom.com>
This commit add a hsspi controller in the bcm6858 device tree.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Kursad Oney <kursad.oney@broadcom.com>
This change adds a spi nor flash device to the bcm963158 board.
Signed-off-by: Kursad Oney <kursad.oney@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
This change adds the hsspi controller to the 63158 dtsi.
Signed-off-by: Kursad Oney <kursad.oney@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
The A72 U-Boot code loads and boots a number of remote processors
including the C71x DSP, both the C66_0 and C66_1 DSPs, and the various
Main R5FSS Cores. In order to view the code loaded by the U-Boot by
remote cores, U-Boot should configure the memory region with right
memory attributes. Right now U-Boot carves out a memory region which
is not sufficient for all the images to be loaded. So, increase this
carve out region by 256MB.
Signed-off-by: Kedar Chitnis <kedarc@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The A53 U-Boot code can load and boot the MCU domain R5F cores (either a
single core in LockStep mode or 2 cores in Split mode) to achieve various
early system functionalities. Change the memory attributes for the DDR
regions used by the remote processors so that the cores can see and
execute the proper code loaded by U-Boot.
These regions are currently limited to 0xa0000000 to 0xa2100000 as per
the DDR carveouts assigned for these R5F cores in the overall DDR memory
map.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The AM65x SoCs has a single dual-core Arm Cortex-R5F processor
subsystem/cluster (MCU_R5FSS0) within the MCU domain. This cluster
can be configured at boot time to be either run in a LockStep mode
or in an Asymmetric Multi Processing (AMP) fashion in Split-mode.
This subsystem has 64 KB each Tightly-Coupled Memory (TCM) internal
memories for each core split between two banks - ATCM and BTCM
(further interleaved into two banks). There are some IP integration
differences from standard Arm R5 clusters such as the absence of
an ACP port, presence of an additional TI-specific Region Address
Translater (RAT) module for translating 32-bit CPU addresses into
larger system bus addresses etc.
Add the DT node for the MCU domain R5F cluster/subsystem, the two
R5 cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in Split-mode by default, with the
ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The J721E SoCs have a single TMS320C71x DSP Subsystem in the MAIN
voltage domain containing the next-generation C711 CPU core. The
subsystem has 32 KB of L1D configurable SRAM/Cache and 512 KB of
L2 configurable SRAM/Cache. This subsystem has a CMMU but is not
used currently. The inter-processor communication between the main
A72 cores and the C711 processor is achieved through shared memory
and a Mailbox. Add the DT node for this DSP processor sub-system
in the common k3-j721e-main.dtsi file.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The J721E SoCs have two TMS320C66x DSP Core Subsystems (C66x CorePacs)
in the MAIN voltage domain, each with a C66x Fixed/Floating-Point DSP
Core, and 32 KB of L1P & L1D configurable SRAMs/Cache and an additional
288 KB of L2 configurable SRAM/Cache. These subsystems do not have
an MMU but contain a Region Address Translator (RAT) sub-module for
translating 32-bit processor addresses into larger bus addresses.
The inter-processor communication between the main A72 cores and
these processors is achieved through shared memory and Mailboxes.
Add the DT nodes for these DSP processor sub-systems in the common
k3-j721e-main.dtsi file.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within
the MCU domain, and the remaining two clusters are present in the
MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be
configured at boot time to be either run in a LockStep mode or in
an Asymmetric Multi Processing (AMP) fashion in Split-mode. These
subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal
memories for each core split between two banks - ATCM and BTCM
(further interleaved into two banks). There are some IP integration
differences from standard Arm R5 clusters such as the absence of
an ACP port, presence of an additional TI-specific Region Address
Translater (RAT) module for translating 32-bit CPU addresses into
larger system bus addresses etc.
Add the DT nodes for these two MAIN domain R5F cluster/subsystems,
the two R5 cores are each added as child nodes to the corresponding
main cluster node. Configure SS0 in split mode an SS1 in lockstep mode,
with the ATCMs enabled to allow the R5 cores to execute code from DDR
with boot-strapping code from ATCM.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The J721E SoCs have 3 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within
the MCU domain, and the remaining two clusters are present in the
MAIN domain (MAIN_R5FSS0 & MAIN_R5FSS1). Each of these can be
configured at boot time to be either run in a LockStep mode or in
an Asymmetric Multi Processing (AMP) fashion in Split-mode. These
subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal
memories for each core split between two banks - ATCM and BTCM
(further interleaved into two banks). There are some IP integration
differences from standard Arm R5 clusters such as the absence of
an ACP port, presence of an additional TI-specific Region Address
Translater (RAT) module for translating 32-bit CPU addresses into
larger system bus addresses etc.
Add the DT node for the MCU domain R5F cluster/subsystem, the two
R5 cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in LockStep mode by default, with the
ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Although we currently use the MAIN_UART0 for R5 SPL console output there
are cases where we require access to the MCU_UART0 as well for example in
case of UART-based Y-Modem boot. To support these scenarios add related
DTS definitions to be able to use that UART early on.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
In order to allow booting TI K3 family SoCs via Y-Modem add support for
loading System Firmware by tapping into the associated SPL core loader
function.
In this context also make sure a console is available and if not go
ahead and activate the early console feature which allows bringing up
an alternate full console before the main console is activated. Such
an alternate console is typically setup in a way that the associated
UART can be fully initialized prior to SYSFW services being available.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Implement an early console functionality in SPL that can be used before
the main console is being brought up. This helps in situations where the
main console is dependent on System Firmware (SYSFW) being up and running,
which is usually not the case during the very early stages of boot. Using
this early console functionality will allow for an alternate serial port
to be used to support things like UART-based boot and early diagnostic
messages until the main console is ready to get activated.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
At present this produces a 16-byte file. It is intended to start 16 bytes
before the end of ROM and pads with zeroes to readh the end.
But binman sometimes wants to add an image-header at the very end of ROM.
Furthermore binman automatically pads the data if it is finishes early.
Drop the padding in resetvec and let binman handle it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
This is not used anywhere now, so drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Since x86 users binman now, we don't need this compile-time define.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Many of the Kconfig options do not apply to FSP2. Update them to use the
FSP_VERSION1 condition instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Move the code to determine the size of a cache record into a function so
we can use it elsewhere in this file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present when these fail to boot there is no message, just a hang. Add a
panic so it is obvious that something when wrong.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
- Rename existing FSP code to fsp1
- Add fsp2 directory in preparation to support FSP 2.0
- Various x86 platform codes update
- Various bug fixes and updates in dm core, sandbox and spl
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Merge tag 'u-boot-atmel-2020.01-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel
First set of u-boot-atmel features and fixes for 2020.01 cycle
The feature set includes support for two new boards from Microchip AT91:
The sama5d27_wlsom1_ek , an evaluation kit which includes the SAMA5D2
SOC packaged in a 256 MB LPDDR2 SIP, on a SOM including wireless, which
is placed on evaluation kit with sd-card, ethernet, LCD, Camera sensor,
QSPI, etc
The sam9x60ek, an evaluation kit for the new SoC based on ARM926j , the
SAM9X60 . The evaluation kit includes NAND flash, QSPI, Ethernet, Audio,
Camera sensor connector, etc.
The full support for sam9x60ek will come at a later time. There are
still missing bits regarding the clock support and power management
controller.
The major corrections in this pull request are:
Fixes for the SetVariable() boot service.
Device path node for NVMe drives.
Disable CONFIG_CMD_NVEDIT by default.
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Merge tag 'efi-2020-01-rc1' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-01-rc1
The major corrections in this pull request are:
Fixes for the SetVariable() boot service.
Device path node for NVMe drives.
Disable CONFIG_CMD_NVEDIT by default.
Apologies to everyone whose board I broke by attempting to return
MMC1 or MMC2. I misunderstood how the MMC indexing worked.
This reverts commit 14d319b185.
Signed-off-by: Adam Ford <aford173@gmail.com>
Since convert dm_video, unused code introduced, so remove this
Signed-off-by: Joris Offouga <offougajoris@gmail.com>
Reviewed-by: Otavio Salvador <otavio@ossystems.com.br>
