Commit Graph

494 Commits

Author SHA1 Message Date
Hans de Goede
0a247554c2 sunxi_nand_spl: Properly config page-size in the nand ctl register
Properly config page-size in the nand ctl register, it seems that things
work fine without doing this, but still lets play it safe and properly
set the page-size.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:42 +02:00
Hans de Goede
022a99d8b2 sunxi_nand_spl: Add support for sun4i and sun5i SoCs
Other then having a few less chip-select lines the nand controller
on sun4i, sun5i and sun7i is identical.

Note this patch also muxes GPC7 to the NAND on sun7i where as before
it was not muxed this way. GPC7 is a standard NAND pin, so it should
always be muxed to the NAND when in use.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:42 +02:00
Hans de Goede
008ac1dfe0 sunxi_nand_spl: Use kernel driver algorithm for determining ecc_mode / _off
Sync the code for figuring out the ecc_mode and ecc_offset with the linux
kernel v4.1. Keeping this in sync seems like a good idea in general, and
it fixes / adds support for ecc strengths of 56, 60 and 64 bits.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:41 +02:00
Hans de Goede
2a43973f64 sunxi_nand_spl: Add proper cache flusing
We are using dma, so we should flush the cache before starting the dma,
and invalidate it once the dma is done.

Things are working without this by mostly luck, but lets not rely on that.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:41 +02:00
Hans de Goede
5d65c67bf1 sunxi_nand_spl: Turn off clocks when we're done with the nand
Turn off the nand and dma clocks when we're done with the nand, this
puts the nand and dma controllers back into a clean state for when the
kernel boots.

Without this the kernel will not boot properly when it is built with
dma-controller support.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:41 +02:00
Hans de Goede
f62bfa56da sunxi_nand_spl: Use SYS_NAND_SELF_INIT and only do nand init when necessary
Use SYS_NAND_SELF_INIT and only setup the pinmux and clocks when we are
actually using the nand.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:41 +02:00
Hans de Goede
9da5fca55c sunxi_nand_spl: Do not bother writing the spare-area reg in syndrome mode
In syndrome mode we set the NFC_SEQ bit in the command register, so the
spare-area register is not used. Also the value currently being written is
actual wrong, the ecc sits at "column + CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE"
not just CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE.

So the current code only serves to confuse the user -> remove it.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:41 +02:00
Hans de Goede
630cf2e762 sunxi_nand_spl: We only need to reset the nand chip once
There is no need to reset the nand chip for every ecc-block read.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:41 +02:00
Hans de Goede
10d069b797 sunxi_nand_spl: Drop unnecessary temp buf
nand_spl_load_image() always gets called with either CONFIG_SYS_TEXT_BASE
or spl_image.load_addr as destination, both of which are properly aligened,
and have plenty of space for "overshooting" up to
CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE bytes, as we read in
CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE bytes chunks.

This saves CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE (typically 1k) in
SPL size, which is a lot on the total 24k we have.

Note this changes the dma destination from SRAM to DRAM, so this patch
updates the DDMA_DST_TYPE bits in the dma controller cfg0 reg accordingly.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:41 +02:00
Masahiro Yamada
2bc1f2b592 mtd: denali_spl: do not allocate page_buffer in .bss section
Since commit 2580a2a7e7 ("mtd: nand: Increase max sizes of OOB and
Page size"), three boards (ph1_ld4, ph1_pro4, ph1_sld8) fail to build
with the following error message:
  arm-linux-gnueabi-ld.bfd: SPL image plus BSS too big

They compile drivers/mtd/nand/denali_spl.c and it has a page_buffer
as static data:

    static uint8_t page_buffer[NAND_MAX_PAGESIZE];

This buffer required 8KB in .bss section before that commit and now
it has been increased to 16KB.  Given limited code/memory size for SPL,
it is not a good idea to allocate a page buffer statically.  In the
first place, the load address 'dst' can be used as a page buffer.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-08-30 22:18:00 +09:00
Marcel Ziswiler
4519668b29 mtd/nand/ubi: assortment of alignment fixes
Various U-Boot adoptions/extensions to MTD/NAND/UBI did not take buffer
alignment into account which led to failures of the following form:

ERROR: v7_dcache_inval_range - start address is not aligned - 0x1f7f0108
ERROR: v7_dcache_inval_range - stop address is not aligned - 0x1f7f1108

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Scott Wood <scottwood@freescale.com>
[trini: Add __UBOOT__ hunk to lib/zlib/zutil.c due to malloc.h in common.h]
Signed-off-by: Tom Rini <trini@konsulko.com>
2015-08-28 12:33:17 -04:00
Peng Fan
ecfb8768b1 mtd: nand: mxs invalidate dcache before DMA read
Follow linux dma flow:
Before DMA read, be sure to invalidate the cache over the address
range of DMA buffer to prevent cache coherency problems.
After DMA read, invalidate dcache again.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
2015-08-25 22:53:59 -05:00
Peng Fan
63b29d8082 mtd: nand: mxs support oobsize bigger than 512
If ecc chunk data size is 512 and oobsize is bigger than 512, there is
a chance that block_mark_bit_offset conflicts with bch ecc area.

The following graph is modified from kernel gpmi-nand.c driver with
each data block 512 bytes. We can see that Block Mark conflicts with
ecc area from bch view. We can enlarge the ecc chunk size to avoid
this problem to those oobsize which is larger than 512.

   |                          P                                        |
   |<----------------------------------------------------------------->|
   |                                                                   |
   |                                                (Block Mark)       |
   |                      P'                             |           | |   |
   |<--------------------------------------------------->|     D     | | O'|
   |                                                     |<--------->| |<->|
   V                                                     V           V V   V
   +---+--------------+-+--------------+-+--------------+-+----------+-+---+
   | M |   data       |E|   data       |E|   data       |E|   data   |E|   |
   +---+--------------+-+--------------+-+--------------+-+----------+-+---+
                                                        ^                  ^
                                                        |         O        |
                                                        |<---------------->|

       P : the page size for BCH module.
       E : The ECC strength.
       G : the length of Galois Field.
       N : The chunk count of per page.
       M : the metasize of per page.
       C : the ecc chunk size, aka the "data" above.
       P': the nand chip's page size.
       O : the nand chip's oob size.
       O': the free oob.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Tested-By: Tim Harvey <tharvey@gateworks.com>
2015-08-25 22:53:58 -05:00
Stefan Roese
873960c89e mtd: nand: Add mvebu (PXA / AXP / A38x) NAND device driver
Cloned from the Linux driver v4.2.0-rc2. Plus some patches from
Antoine Tenart enabling controller initialization and ONFI timing
support:

http://lists.infradead.org/pipermail/linux-mtd/2015-July/060197.html

Please note that this driver needs the Linux NAND subsystem sync to v4.1
from Scott to be applied:

https://www.mail-archive.com/u-boot@lists.denx.de/msg175762.html

Otherwise it will not compile.

Tested on the Marvell Armada XP DB-MV784MP-GP eval board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Antoine Tenart <antoine.tenart@free-electrons.com>
Cc: Ezeguil Garcia <ezequiel.garcia@free-electrons.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Scott Wood <scottwood@freescale.com>
2015-08-25 22:53:58 -05:00
Scott Wood
d3963721d9 nand: Sync with Linux v4.1
Update the NAND code to match Linux v4.1.  The previous sync was
from Linux v3.15 in commit 4e67c57125.

CONFIG_SYS_NAND_RESET_CNT is removed, as the upstream Linux code now
has its own timeout.  Plus, CONFIG_SYS_NAND_RESET_CNT was undocumented
and not selected by any board.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2015-08-25 22:53:57 -05:00
Ezequiel Garcia
86a720aafc mtd: Introduce mtd_block_isreserved()
In addition to mtd_block_isbad(), which checks if a block is bad or
reserved, it's needed to check if a block is reserved only (but not
bad). This commit adds an MTD interface for it, in a similar fashion to
mtd_block_isbad().

While here, fix mtd_block_isbad() so the out-of-bounds checking is done
before the callback check.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
[scottwood: Cherry-picked from Linux 8471bb73ba10ed67]
Signed-off-by: Scott Wood <scottwood@freescale.com>
2015-08-25 22:53:57 -05:00
Scott Wood
273310644f nand: Remove __UBOOT__ ifdefs
I didn't approve the patch that added them.  Get them out of the way
before doing a sync.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2015-08-25 22:53:57 -05:00
Sylvain Lemieux
30cb3bf4a9 nand: lpc32xx: add ECC layout for small page NAND
Incorporate ECC layout for small page NAND from legacy LPCLinux NXP BSP.
The code taken from the legacy patch is:
- lpc32xx SLC NAND driver (ECC layout for small page)

This layout is matching the lpc32xx NAND SLC Linux Kernel driver.

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
2015-08-18 13:45:56 -04:00
Sylvain Lemieux
5f63bf3ec8 nand: lpc32xx: add hardware ECC support
Incorporate NAND SLC hardware ECC support from legacy LPCLinux NXP BSP.
The code taken from the legacy patch is:
- lpc32xx SLC NAND driver (hardware ECC support)
- lpc3250 header file missing SLC NAND registers definition

The legacy driver was updated and clean-up as part of the integration with the existing NAND SLC driver.

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Tested-by: Vladimir Zapolskiy <vz@mleia.com>
2015-08-18 13:45:56 -04:00
Marcel Ziswiler
6eeedc196d tegra: nand: disable subpage writes
Disable subpage writes as we do not provide ecc->hwctl.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-08-13 13:06:03 -07:00
Marcel Ziswiler
adf4800d85 mtd/nand/tegra: alignment workaround
Integrate cache alignment bounce buffer to workaround issues as follows:

Loading file '/boot/zImage' to addr 0x01000000 with size 4499152 (0x0044a6d0)...
ERROR: v7_dcache_inval_range - start address is not aligned - 0x1f7f0108
ERROR: v7_dcache_inval_range - stop address is not aligned - 0x1f7f1108
Done
Kernel image @ 0x1000000 [ 0x000000 - 0x44a6d0 ]

Starting kernel ...

undefined instruction
pc : [<005ff03c>]          lr : [<0000800c>]
sp : 0144b6e8  ip : 01000188     fp : 0144a6c8
r10: 00000000  r9 : 411fc090     r8 : 00000100
r7 : 00000cfb  r6 : 0144a6d0     r5 : 00000000  r4 : 00008000
r3 : 0000000c  r2 : 00000100     r1 : 00000cfb  r0 : 00000000
Flags: nZCv  IRQs off  FIQs off  Mode SVC_32
Resetting CPU ...

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-08-13 13:06:02 -07:00
Marcel Ziswiler
1bc66a57c0 tegra: nand: fix read_byte required for proper onfi detection
Fix PIO read_byte() implementation not only used for the legacy READ ID
but also the PARAM command required for proper ONFI detection.

This fix is inspired by Lucas Stach's Linux Tegra NAND driver of late
(not mainline yet but getting there soon I hope).

I vaguely remember that those commands are special on 16-bit bus NAND
(e.g. always return 8-bit data regardless) and later Linux MTD fixed/
changed the way this is handled which in turn broke once U-Boot pulled
that in. Basically instead of doing PIO read regular DMA block read is
now used which this patch actually fixes.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-08-13 13:06:02 -07:00
Vladimir Zapolskiy
dcfd37e5ef nand: lpc32xx: add SLC NAND controller support
The change adds support of LPC32xx SLC NAND controller.

LPC32xx SoC has two different mutually exclusive NAND controllers to
communicate with single and multiple layer chips.

This simple driver allows to specify NAND chip timings and defines
custom read_buf()/write_buf() operations, because access to 8-bit data
register must be 32-bit aligned.

Support of hardware ECC calculation is not implemented (data
correction is always done by software), since it requires a working
DMA engine.

The driver can be included to an SPL image.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
2015-08-12 20:47:33 -04:00
Vladimir Zapolskiy
8d1809a966 spl: nand: simple: replace readb() with chip specific read_buf()
Some NAND controllers define custom functions to read data out,
respect this in order to correctly support bad block handling in
simple SPL NAND framework.

NAND controller specific read_buf() is used even to read 1 byte in
case of connected 8-bit NAND device, it turns out that read_byte()
may become outdated.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Tom Warren <twarren@nvidia.com>
Acked-by: Scott Wood <scottwood@freescale.com>
2015-08-12 20:47:33 -04:00
Heiko Schocher
c10ac540ea nand, atmel: remove udelay in spl_nand_erase_one()
remove unneeded udelay() in this function, as we use
the dev_ready pin.

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
2015-08-12 20:47:27 -04:00
Piotr Zierhoffer
960caeba8f sunxi: nand: Add board configuration options
When SPL_NAND_SUNXI option is selected in config, set some configuration
options for sunxi NAND.

This commit also introduces the configurable options in Kconfig.

Signed-off-by: Peter Gielda <pgielda@antmicro.com>
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-08-08 16:26:19 +02:00
Piotr Zierhoffer
aeb4b0d3b3 sunxi: nand: Add basic sunxi NAND driver for SPL with DMA support
This driver adds NAND support to SPL.
It was tested on Allwinner A20.

Signed-off-by: Peter Gielda <pgielda@antmicro.com>
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-08-08 16:26:19 +02:00
Ian Campbell
da9971d1b3 Revert "sunxi/nand: Add support to the SPL for loading u-boot from internal NAND memory"
This reverts commit f76eba38b3.

This patch did not have a full and proper copyright/S-o-b chain.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>

Conflicts:
	include/configs/sun6i.h
	include/configs/sun8i.h
2015-06-28 11:46:31 -04:00
Jeroen Hofstee
cb2fc338f8 mtd: OMAP: Enable GPMC prefetch mode for 16 bit access
commit c316f57 "mtd: OMAP: Enable GPMC prefetch mode" only enabled
prefetch mode for 8 bit nand access, this adds 16 bit as well.

Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Daniel Mack <zonque@gmail.com>

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-06-18 11:23:45 -04:00
Jeroen Hofstee
c07361145f omap_gpmc: move prefetch out of CONFIG_NAND_OMAP_ELM
The prefech mode is a feature of the gpmc, not the ELM. An am3517
does not have an elm, but can do prefeches, so move the code out
of the CONFIG_NAND_OMAP_ELM ifdef.

Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Daniel Mack <zonque@gmail.com>

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-06-18 11:23:45 -04:00
Daniel Kochmański
f76eba38b3 sunxi/nand: Add support to the SPL for loading u-boot from internal NAND memory
This commit adds support to the sunxi SPL to load u-boot from the internal
NAND. Note this only adds support to access the boot partitions to load
u-boot, full NAND support to load the kernel, etc. from the nand data
partition will come later.

Signed-off-by: Roy Spliet <r.spliet@ultimaker.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-05-29 13:46:36 +02:00
Stefan Agner
8fca2d8cb8 mtd: vf610_nfc: enable ONFI detection
This changes enable ONFI detection. The Read ID command now allows
one address byte which is needed for ONFI detection. To read the
ONFI parameter page, the NAND_CMD_PARAM need to be supported. The
CMD code enables one command and one address byte along with reading
data from flash using R/B#, as specified by ONFI.

Signed-off-by: Stefan Agner <stefan@agner.ch>
2015-05-24 14:27:46 -05:00
Stefan Agner
080a71e8e9 mtd: vf610_nfc: add 32-error correction option for HW ECC
Add option to choose between current 24-error correction and 32-error
correction through Kconfig. 32-error correction allow to use NAND
chips which require up to 8-bit error correction per 512 byte (when
using 2K pages).

Signed-off-by: Stefan Agner <stefan@agner.ch>
2015-05-24 14:27:46 -05:00
Stefan Agner
5519194d4f mtd: vf610_nfc: add Freescale NFC controller configs to Kconfig
This commit allows users to enable/disable the Freescale NFC
controller found in systems like Vybrid (VF610), MPC5125, MCF54418
or Kinetis K70 via Kconfig with more detailed help docs.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Stefano Babic <sbabic@denx.de>
[scottwood: updated vf610twr_nand_defconfig]
Signed-off-by: Scott Wood <scottwood@freescale.com>
2015-05-24 14:27:28 -05:00
Stefan Agner
84d656a283 mtd: vf610_nfc: use in-band bad block table
Use in-band bad block table (NAND_BBT_NO_OOB) which allows to
use the full OOB for hardare ECC purposes. Since there is no
ECC correction on the OOB it is also safer to use in-band area
to store the bad block table marker.

Signed-off-by: Stefan Agner <stefan@agner.ch>
2015-05-24 14:26:55 -05:00
Stefan Agner
5dec286b82 mtd: vf610_nfc: implement OOB only read
Implement read of OOB area only. When using column and sector size
properties, only parts of the page can be read. However, this works
only when hardware ECC is disabled, otherwise the ECC engine would
ruin the data in the buffer. To allow OOB only reads, three points
had to be addressed:
- Set ECC mode per command.
- Handle NAND_CMD_READOOB seperate. Make sure column and sector
  size is correctly set up, while disabling ECC.
- Now, the OOB data end up at the beginning of the buffer. Remove
  the special handling of OOB (spareonly).

Especially bad block scans benefit from this change. On a 512MiB
SLC NAND device, the bad block scan took 1.5s less than before.

Signed-off-by: Stefan Agner <stefan@agner.ch>
2015-05-24 14:26:55 -05:00
Stefan Agner
d111bf99a8 mtd: vf610_nfc: allow bitflips in an empty page
Allow bit flips in a empty page up to half of the recoverable
bits (strength / 2).

Signed-off-by: Stefan Agner <stefan@agner.ch>
2015-05-24 14:26:54 -05:00
Stefan Agner
6fcfd1e890 mtd: vf610_nfc: remove read on SEQIN
Since we do not support sub-page writes anyway, reading the page
back to the controller on SEQIN command is not required. Remove
the page read on SEQIN.

However, the column/page values relevant to the SEQIN command, hence
set the column/row address on SEQIN command.

Signed-off-by: Stefan Agner <stefan@agner.ch>
2015-05-24 14:26:54 -05:00
Stefan Agner
f55bc296a8 mtd: vf610_nfc: remove caching of page in buffer
To improve performance we remember the current page in the buffer
and avoid reading it twice. This implicit page cache increases
complexity while does not increase performance in real world cases.
This patch removes that feature.

Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
2015-05-24 14:26:54 -05:00
Jörg Krause
1fbdb70610 mtd: nand: mxs: Replace magic number for bits per ECC level with macro
Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
Reviewed-by: Marek Vasut <marex@denx.de>
2015-05-24 14:26:54 -05:00
Peng Fan
bd38da1a55 mtd:mxs:nand calculate ecc strength dynamically
Calculate ecc strength according oobsize, but not hardcoded
which is not aligned with kernel driver

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <b37916@freescale.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
2015-05-24 14:26:54 -05:00
Raghav Dogra
6b8583b0ad nand/elbc: Memory leak fix
Freeing allocated memory to priv before returning
from the function

Signed-off-by: Raghav Dogra <raghav@freescale.com>
[scottwood: removed unnecessary cast]
Signed-off-by: Scott Wood <scottwood@freescale.com>
2015-05-22 15:45:51 -05:00
Stephen Warren
5e856fa8be nand: fix buffer alignment in new verification feature
On systems with caches enabled, NAND I/O may need to flush/invalidate
the cache during read/write operations. For this to work correctly, all
buffers must be cache-aligned. Fix nand_verify*() to allocate aligned
buffers.

This prevents cache alignment warnings from being spewed when using
U-Boot to write an updated version of itself to flash on NVIDIA Tegra
Seaboard (after perturbation of stack/data layout in current
u-boot-dm/next branch).

I have validatd (executed) nand_verify(), but I don't think I've executed
nand_verify_page_oob(); testing of that would be useful.

Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Fixes: 59b5a2ad83 ("nand: Add verification functions")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Scott Wood <scottwood@freescale.com>
2015-05-21 14:24:36 -05:00
Scott Wood
b2d5ac5985 armv8/ls2085aqds: NAND boot support
This adds NAND boot support for LS2085AQDS, using SPL framework.
Details of forming NAND image can be found in README.

Signed-off-by: Scott Wood <scottwood@freescale.com>
[York Sun: Remove +S from defconfig after commit 252ed872]
Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 16:46:50 -07:00
Jaiprakash Singh
39b0bbbb23 driver/ifc: Add 64KB page support
IFC has two register pages.Till IFC version 1.4 each
register page is 4KB each.But IFC ver 2.0 register page
size is 64KB each.IFC regiters structure is break into
two viz FCM and RUNTIME.FCM(Flash control machine) registers
are defined in PAGE0 and controls IFC generic functionality.
RUNTIME registers are defined in PAGE1 and controls NAND and
GPCM funcinality.

FCM and RUNTIME structures defination is common for IFC
version 1.4 and 2.0.

Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 16:46:50 -07:00
Scott Wood
585acc9de6 nand/fsl_ifc: Increase eccstat[] for IFC 2.0
IFC 2.0 doubled the SRAM size, which means double the number of
ECCSTAT registers.  Fix the resulting array overflow.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-23 08:55:53 -07:00
Albert ARIBAUD \(3ADEV\)
c8381bf435 lpc32xx: mtd: nand: add MLC NAND controller
The controller's Reed-Solomon ECC hardware is
used except of course for raw reads and writes.
It covers in- and out-of-band data together.

The SPL framework is supported.

Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
2015-04-10 14:22:56 +02:00
Tom Rini
10697704ca Merge branch 'master' of git://git.denx.de/u-boot-atmel 2015-03-31 19:15:59 -04:00
David Dueck
da78fb5414 ARM: at91: atmel_nand: Support flash based BBT
Add support for on-flash bad block table. This makes U-Boot handle an existing
BBT correctly.

Signed-off-by: David Dueck <davidcdueck@googlemail.com>
Reviewed-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
CC: Boris BREZILLON <boris.brezillon@free-electrons.com>
CC: Josh Wu <josh.wu@atmel.com>
CC: Andreas Bießmann <andreas.devel@googlemail.com>
CC: Scott Wood <scottwood@freescale.com>
Acked-by: Josh Wu <josh.wu@atmel.com>
2015-04-01 01:04:28 +02:00
Stefan Agner
55765b1842 mtd: vf610_nfc: specify transfer size before each transfer
Testing showed, that commands like STATUS made the buffer dirty
when executed with NFC_SECSZ set to the page size. It looks
like the controller transfers bogus data when this register
is configured. When setting it to 0, the buffer does not get
altered while the status command still seems to work flawless.

Signed-off-by: Stefan Agner <stefan@agner.ch>
2015-03-30 23:35:27 -05:00