dma: ti: add driver to K3 UDMA
The UDMA-P is intended to perform similar (but significantly upgraded) functions as the packet-oriented DMA used on previous SoC devices. The UDMA-P module supports the transmission and reception of various packet types. The UDMA-P also supports acting as both a UTC and UDMA-C for its internal channels. Channels in the UDMA-P can be configured to be either Packet-Based or Third-Party channels on a channel by channel basis. The initial driver supports: - MEM_TO_MEM (TR mode) - DEV_TO_MEM (Packet mode) - MEM_TO_DEV (Packet mode) Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com>
This commit is contained in:
Vignesh R
Tom Rini
parent
17ef3c4c28
commit
ffcc66e8fe
@ -57,4 +57,6 @@ config APBH_DMA_BURST8
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endif
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source "drivers/dma/ti/Kconfig"
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endmenu # menu "DMA Support"
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@ -13,3 +13,5 @@ obj-$(CONFIG_SANDBOX_DMA) += sandbox-dma-test.o
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obj-$(CONFIG_TI_KSNAV) += keystone_nav.o keystone_nav_cfg.o
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obj-$(CONFIG_TI_EDMA3) += ti-edma3.o
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obj-$(CONFIG_DMA_LPC32XX) += lpc32xx_dma.o
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obj-y += ti/
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14
drivers/dma/ti/Kconfig
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14
drivers/dma/ti/Kconfig
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@ -0,0 +1,14 @@
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# SPDX-License-Identifier: GPL-2.0+
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if ARCH_K3
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config TI_K3_NAVSS_UDMA
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bool "Texas Instruments UDMA"
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depends on ARCH_K3
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select DMA
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select TI_K3_NAVSS_RINGACC
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select TI_K3_NAVSS_PSILCFG
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default n
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help
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Support for UDMA used in K3 devices.
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endif
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3
drivers/dma/ti/Makefile
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3
drivers/dma/ti/Makefile
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@ -0,0 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0+
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obj-$(CONFIG_TI_K3_NAVSS_UDMA) += k3-udma.o
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184
drivers/dma/ti/k3-udma-hwdef.h
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184
drivers/dma/ti/k3-udma-hwdef.h
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@ -0,0 +1,184 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef K3_NAVSS_UDMA_HWDEF_H_
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#define K3_NAVSS_UDMA_HWDEF_H_
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#define UDMA_PSIL_DST_THREAD_ID_OFFSET 0x8000
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/* Global registers */
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#define UDMA_REV_REG 0x0
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#define UDMA_PERF_CTL_REG 0x4
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#define UDMA_EMU_CTL_REG 0x8
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#define UDMA_PSIL_TO_REG 0x10
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#define UDMA_UTC_CTL_REG 0x1c
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#define UDMA_CAP_REG(i) (0x20 + (i * 4))
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#define UDMA_RX_FLOW_ID_FW_OES_REG 0x80
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#define UDMA_RX_FLOW_ID_FW_STATUS_REG 0x88
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/* RX Flow regs */
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#define UDMA_RFLOW_RFA_REG 0x0
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#define UDMA_RFLOW_RFB_REG 0x4
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#define UDMA_RFLOW_RFC_REG 0x8
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#define UDMA_RFLOW_RFD_REG 0xc
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#define UDMA_RFLOW_RFE_REG 0x10
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#define UDMA_RFLOW_RFF_REG 0x14
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#define UDMA_RFLOW_RFG_REG 0x18
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#define UDMA_RFLOW_RFH_REG 0x1c
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#define UDMA_RFLOW_REG(x) (UDMA_RFLOW_RF##x##_REG)
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/* TX chan regs */
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#define UDMA_TCHAN_TCFG_REG 0x0
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#define UDMA_TCHAN_TCREDIT_REG 0x4
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#define UDMA_TCHAN_TCQ_REG 0x14
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#define UDMA_TCHAN_TOES_REG(i) (0x20 + (i) * 4)
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#define UDMA_TCHAN_TEOES_REG 0x60
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#define UDMA_TCHAN_TPRI_CTRL_REG 0x64
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#define UDMA_TCHAN_THREAD_ID_REG 0x68
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#define UDMA_TCHAN_TFIFO_DEPTH_REG 0x70
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#define UDMA_TCHAN_TST_SCHED_REG 0x80
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/* RX chan regs */
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#define UDMA_RCHAN_RCFG_REG 0x0
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#define UDMA_RCHAN_RCQ_REG 0x14
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#define UDMA_RCHAN_ROES_REG(i) (0x20 + (i) * 4)
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#define UDMA_RCHAN_REOES_REG 0x60
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#define UDMA_RCHAN_RPRI_CTRL_REG 0x64
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#define UDMA_RCHAN_THREAD_ID_REG 0x68
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#define UDMA_RCHAN_RST_SCHED_REG 0x80
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#define UDMA_RCHAN_RFLOW_RNG_REG 0xf0
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/* TX chan RT regs */
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#define UDMA_TCHAN_RT_CTL_REG 0x0
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#define UDMA_TCHAN_RT_SWTRIG_REG 0x8
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#define UDMA_TCHAN_RT_STDATA_REG 0x80
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#define UDMA_TCHAN_RT_PEERn_REG(i) (0x200 + (i * 0x4))
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#define UDMA_TCHAN_RT_PEER_STATIC_TR_XY_REG \
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UDMA_TCHAN_RT_PEERn_REG(0) /* PSI-L: 0x400 */
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#define UDMA_TCHAN_RT_PEER_STATIC_TR_Z_REG \
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UDMA_TCHAN_RT_PEERn_REG(1) /* PSI-L: 0x401 */
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#define UDMA_TCHAN_RT_PEER_BCNT_REG \
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UDMA_TCHAN_RT_PEERn_REG(4) /* PSI-L: 0x404 */
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#define UDMA_TCHAN_RT_PEER_RT_EN_REG \
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UDMA_TCHAN_RT_PEERn_REG(8) /* PSI-L: 0x408 */
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#define UDMA_TCHAN_RT_PCNT_REG 0x400
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#define UDMA_TCHAN_RT_BCNT_REG 0x408
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#define UDMA_TCHAN_RT_SBCNT_REG 0x410
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/* RX chan RT regs */
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#define UDMA_RCHAN_RT_CTL_REG 0x0
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#define UDMA_RCHAN_RT_SWTRIG_REG 0x8
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#define UDMA_RCHAN_RT_STDATA_REG 0x80
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#define UDMA_RCHAN_RT_PEERn_REG(i) (0x200 + (i * 0x4))
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#define UDMA_RCHAN_RT_PEER_STATIC_TR_XY_REG \
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UDMA_RCHAN_RT_PEERn_REG(0) /* PSI-L: 0x400 */
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#define UDMA_RCHAN_RT_PEER_STATIC_TR_Z_REG \
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UDMA_RCHAN_RT_PEERn_REG(1) /* PSI-L: 0x401 */
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#define UDMA_RCHAN_RT_PEER_BCNT_REG \
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UDMA_RCHAN_RT_PEERn_REG(4) /* PSI-L: 0x404 */
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#define UDMA_RCHAN_RT_PEER_RT_EN_REG \
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UDMA_RCHAN_RT_PEERn_REG(8) /* PSI-L: 0x408 */
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#define UDMA_RCHAN_RT_PCNT_REG 0x400
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#define UDMA_RCHAN_RT_BCNT_REG 0x408
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#define UDMA_RCHAN_RT_SBCNT_REG 0x410
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/* UDMA_TCHAN_TCFG_REG/UDMA_RCHAN_RCFG_REG */
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#define UDMA_CHAN_CFG_PAUSE_ON_ERR BIT(31)
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#define UDMA_TCHAN_CFG_FILT_EINFO BIT(30)
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#define UDMA_TCHAN_CFG_FILT_PSWORDS BIT(29)
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#define UDMA_CHAN_CFG_ATYPE_MASK GENMASK(25, 24)
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#define UDMA_CHAN_CFG_ATYPE_SHIFT 24
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#define UDMA_CHAN_CFG_CHAN_TYPE_MASK GENMASK(19, 16)
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#define UDMA_CHAN_CFG_CHAN_TYPE_SHIFT 16
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/*
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* PBVR - using pass by value rings
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* PBRR - using pass by reference rings
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* 3RDP - Third Party DMA
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* BC - Block Copy
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* SB - single buffer packet mode enabled
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*/
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#define UDMA_CHAN_CFG_CHAN_TYPE_PACKET_PBRR \
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(2 << UDMA_CHAN_CFG_CHAN_TYPE_SHIFT)
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#define UDMA_CHAN_CFG_CHAN_TYPE_PACKET_SB_PBRR \
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(3 << UDMA_CHAN_CFG_CHAN_TYPE_SHIFT)
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#define UDMA_CHAN_CFG_CHAN_TYPE_3RDP_PBRR \
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(10 << UDMA_CHAN_CFG_CHAN_TYPE_SHIFT)
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#define UDMA_CHAN_CFG_CHAN_TYPE_3RDP_PBVR \
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(11 << UDMA_CHAN_CFG_CHAN_TYPE_SHIFT)
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#define UDMA_CHAN_CFG_CHAN_TYPE_3RDP_BC_PBRR \
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(12 << UDMA_CHAN_CFG_CHAN_TYPE_SHIFT)
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#define UDMA_RCHAN_CFG_IGNORE_SHORT BIT(15)
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#define UDMA_RCHAN_CFG_IGNORE_LONG BIT(14)
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#define UDMA_TCHAN_CFG_SUPR_TDPKT BIT(8)
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#define UDMA_CHAN_CFG_FETCH_SIZE_MASK GENMASK(6, 0)
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#define UDMA_CHAN_CFG_FETCH_SIZE_SHIFT 0
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/* UDMA_TCHAN_RT_CTL_REG/UDMA_RCHAN_RT_CTL_REG */
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#define UDMA_CHAN_RT_CTL_EN BIT(31)
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#define UDMA_CHAN_RT_CTL_TDOWN BIT(30)
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#define UDMA_CHAN_RT_CTL_PAUSE BIT(29)
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#define UDMA_CHAN_RT_CTL_FTDOWN BIT(28)
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#define UDMA_CHAN_RT_CTL_ERROR BIT(0)
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/* UDMA_TCHAN_RT_PEER_RT_EN_REG/UDMA_RCHAN_RT_PEER_RT_EN_REG (PSI-L: 0x408) */
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#define UDMA_PEER_RT_EN_ENABLE BIT(31)
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#define UDMA_PEER_RT_EN_TEARDOWN BIT(30)
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#define UDMA_PEER_RT_EN_PAUSE BIT(29)
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#define UDMA_PEER_RT_EN_FLUSH BIT(28)
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#define UDMA_PEER_RT_EN_IDLE BIT(1)
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/* RX Flow reg RFA */
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#define UDMA_RFLOW_RFA_EINFO BIT(30)
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#define UDMA_RFLOW_RFA_PSINFO BIT(29)
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#define UDMA_RFLOW_RFA_ERR_HANDLING BIT(28)
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#define UDMA_RFLOW_RFA_DESC_TYPE_MASK GENMASK(27, 26)
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#define UDMA_RFLOW_RFA_DESC_TYPE_SHIFT 26
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#define UDMA_RFLOW_RFA_PS_LOC BIT(25)
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#define UDMA_RFLOW_RFA_SOP_OFF_MASK GENMASK(24, 16)
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#define UDMA_RFLOW_RFA_SOP_OFF_SHIFT 16
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#define UDMA_RFLOW_RFA_DEST_QNUM_MASK GENMASK(15, 0)
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#define UDMA_RFLOW_RFA_DEST_QNUM_SHIFT 0
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/* RX Flow reg RFC */
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#define UDMA_RFLOW_RFC_SRC_TAG_HI_SEL_SHIFT 28
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#define UDMA_RFLOW_RFC_SRC_TAG_LO_SEL_SHIFT 24
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#define UDMA_RFLOW_RFC_DST_TAG_HI_SEL_SHIFT 20
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#define UDMA_RFLOW_RFC_DST_TAG_LO_SE_SHIFT 16
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/*
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* UDMA_TCHAN_RT_PEER_STATIC_TR_XY_REG /
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* UDMA_RCHAN_RT_PEER_STATIC_TR_XY_REG
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*/
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#define PDMA_STATIC_TR_X_MASK GENMASK(26, 24)
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#define PDMA_STATIC_TR_X_SHIFT (24)
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#define PDMA_STATIC_TR_Y_MASK GENMASK(11, 0)
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#define PDMA_STATIC_TR_Y_SHIFT (0)
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#define PDMA_STATIC_TR_Y(x) \
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(((x) << PDMA_STATIC_TR_Y_SHIFT) & PDMA_STATIC_TR_Y_MASK)
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#define PDMA_STATIC_TR_X(x) \
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(((x) << PDMA_STATIC_TR_X_SHIFT) & PDMA_STATIC_TR_X_MASK)
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/*
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* UDMA_TCHAN_RT_PEER_STATIC_TR_Z_REG /
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* UDMA_RCHAN_RT_PEER_STATIC_TR_Z_REG
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*/
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#define PDMA_STATIC_TR_Z_MASK GENMASK(11, 0)
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#define PDMA_STATIC_TR_Z_SHIFT (0)
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#define PDMA_STATIC_TR_Z(x) \
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(((x) << PDMA_STATIC_TR_Z_SHIFT) & PDMA_STATIC_TR_Z_MASK)
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#endif /* K3_NAVSS_UDMA_HWDEF_H_ */
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1730
drivers/dma/ti/k3-udma.c
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1730
drivers/dma/ti/k3-udma.c
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File diff suppressed because it is too large
Load Diff
31
include/dt-bindings/dma/k3-udma.h
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31
include/dt-bindings/dma/k3-udma.h
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@ -0,0 +1,31 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
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*/
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#ifndef __DT_TI_UDMA_H
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#define __DT_TI_UDMA_H
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#define UDMA_TR_MODE 0
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#define UDMA_PKT_MODE 1
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#define UDMA_DIR_TX 0
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#define UDMA_DIR_RX 1
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#define PSIL_STATIC_TR_NONE 0
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#define PSIL_STATIC_TR_XY 1
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#define PSIL_STATIC_TR_MCAN 2
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#define UDMA_PDMA_TR_XY(id) \
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ti,psil-config##id { \
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linux,udma-mode = <UDMA_TR_MODE>; \
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statictr-type = <PSIL_STATIC_TR_XY>; \
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}
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#define UDMA_PDMA_PKT_XY(id) \
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ti,psil-config##id { \
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linux,udma-mode = <UDMA_PKT_MODE>; \
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statictr-type = <PSIL_STATIC_TR_XY>; \
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}
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#endif /* __DT_TI_UDMA_H */
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24
include/linux/soc/ti/ti-udma.h
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24
include/linux/soc/ti/ti-udma.h
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@ -0,0 +1,24 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
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* Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
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*/
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#ifndef __TI_UDMA_H
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#define __TI_UDMA_H
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/**
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* struct ti_udma_drv_packet_data - TI UDMA transfer specific data
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*
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* @pkt_type: Packet Type - specific for each DMA client HW
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* @dest_tag: Destination tag The source pointer.
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*
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* TI UDMA transfer specific data passed as part of DMA transfer to
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* the DMA client HW in UDMA descriptors.
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*/
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struct ti_udma_drv_packet_data {
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u32 pkt_type;
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u32 dest_tag;
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};
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#endif /* __TI_UDMA_H */
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