ppc: Move mpc512x clocks to arch_global_data
Move ips_clk and csb_clk into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
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@ -68,7 +68,7 @@ int checkcpu (void)
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}
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printf ("at %s MHz, CSB at %s MHz (RSR=0x%04lx)\n",
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strmhz(buf1, clock),
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strmhz(buf2, gd->csb_clk),
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strmhz(buf2, gd->arch.csb_clk),
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gd->reset_status & 0xffff);
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return 0;
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}
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@ -250,7 +250,7 @@ static int mpc_get_fdr (int speed)
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{126, 128}
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};
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ips = gd->ips_clk;
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ips = gd->arch.ips_clk;
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for (i = 7; i >= 0; i--) {
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for (j = 7; j >= 0; j--) {
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scl = 2 * (scltap[j].scl2tap +
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@ -100,7 +100,7 @@ int ide_preinit (void)
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ide_set_reset(0);
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/* Init timings : we use PIO mode 0 timings */
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t = 1000000000 / gd->ips_clk; /* period in ns */
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t = 1000000000 / gd->arch.ips_clk; /* period in ns */
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cfg.bytes.field1 = 3;
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cfg.bytes.field2 = 3;
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cfg.bytes.field3 = (pio_specs.t1 + t) / t;
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@ -140,7 +140,7 @@ void serial_setbrg_dev(unsigned int idx)
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}
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/* calculate divisor for setting PSC CTUR and CTLR registers */
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baseclk = (gd->ips_clk + 8) / 16;
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baseclk = (gd->arch.ips_clk + 8) / 16;
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div = (baseclk + (baudrate / 2)) / baudrate;
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out_8(&psc->ctur, (div >> 8) & 0xff);
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@ -113,9 +113,9 @@ int get_clocks (void)
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pci_clk = 333333;
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}
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gd->ips_clk = ips_clk;
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gd->arch.ips_clk = ips_clk;
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gd->pci_clk = pci_clk;
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gd->csb_clk = csb_clk;
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gd->arch.csb_clk = csb_clk;
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gd->cpu_clk = core_clk;
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gd->bus_clk = csb_clk;
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return 0;
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@ -128,7 +128,7 @@ int get_clocks (void)
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*********************************************/
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ulong get_bus_freq (ulong dummy)
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{
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return gd->csb_clk;
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return gd->arch.csb_clk;
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}
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int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
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@ -137,10 +137,13 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
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printf("Clock configuration:\n");
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printf(" CPU: %-4s MHz\n", strmhz(buf, gd->cpu_clk));
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printf(" Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
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printf(" IPS Bus: %-4s MHz\n", strmhz(buf, gd->ips_clk));
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printf(" Coherent System Bus: %-4s MHz\n",
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strmhz(buf, gd->arch.csb_clk));
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printf(" IPS Bus: %-4s MHz\n",
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strmhz(buf, gd->arch.ips_clk));
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printf(" PCI: %-4s MHz\n", strmhz(buf, gd->pci_clk));
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printf(" DDR: %-4s MHz\n", strmhz(buf, 2*gd->csb_clk));
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printf(" DDR: %-4s MHz\n",
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strmhz(buf, 2 * gd->arch.csb_clk));
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return 0;
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}
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@ -97,6 +97,10 @@ struct arch_global_data {
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#if defined(CONFIG_MPC5xxx)
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unsigned long ipb_clk;
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#endif
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#if defined(CONFIG_MPC512X)
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u32 ips_clk;
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u32 csb_clk;
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#endif /* CONFIG_MPC512X */
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};
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/*
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@ -119,10 +123,6 @@ typedef struct global_data {
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#if defined(CONFIG_FSL_ESDHC)
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u32 sdhc_clk;
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#endif
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#if defined(CONFIG_MPC512X)
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u32 ips_clk;
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u32 csb_clk;
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#endif /* CONFIG_MPC512X */
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#if defined(CONFIG_MPC8220)
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unsigned long bExtUart;
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unsigned long inp_clk;
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@ -586,7 +586,7 @@ void board_init_f(ulong bootflag)
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bd->bi_vco = gd->arch.vco_out;
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#endif /* CONFIG_CPM2 */
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#if defined(CONFIG_MPC512X)
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bd->bi_ipsfreq = gd->ips_clk;
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bd->bi_ipsfreq = gd->arch.ips_clk;
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#endif /* CONFIG_MPC512X */
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#if defined(CONFIG_MPC5xxx)
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bd->bi_ipbfreq = gd->arch.ipb_clk;
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@ -304,7 +304,7 @@ int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis)
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* and do not drop the Preamble.
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*/
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out_be32(&fec->eth->mii_speed,
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(((gd->ips_clk / 1000000) / 5) + 1) << 1);
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(((gd->arch.ips_clk / 1000000) / 5) + 1) << 1);
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/*
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* Reset PHY, then delay 300ns
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