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ARM: imx: Deduplicate i.MX8M SNVS LPGPR unlock

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Pull this LPGPR unlock into common code, since it is used in multiple
systems already.

Signed-off-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Marek Vasut 2022-09-19 21:37:07 +02:00 committed by Stefano Babic
parent 9bf0cbf396
commit fdf6bbb260
5 changed files with 17 additions and 51 deletions
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5
arch/arm/include/asm/arch-imx8m/imx-regs.h
View File

@ -27,6 +27,7 @@
#define IOMUXC_GPR_BASE_ADDR 0x30340000
#define OCOTP_BASE_ADDR 0x30350000
#define ANATOP_BASE_ADDR 0x30360000
#define SNVS_BASE_ADDR 0x30370000
#define CCM_BASE_ADDR 0x30380000
#define SRC_BASE_ADDR 0x30390000
#define GPC_BASE_ADDR 0x303A0000
@ -113,6 +114,10 @@
#define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1)
#define SRC_DDR1_RCR_PRESET_N_MASK BIT(0)
#define SNVS_LPSR 0x4c
#define SNVS_LPLVDR 0x64
#define SNVS_LPPGDR_INIT 0x41736166
struct iomuxc_gpr_base_regs {
u32 gpr[47];
};

12
arch/arm/mach-imx/imx8m/soc.c
View File

@ -544,6 +544,16 @@ static int imx8m_check_clock(void *ctx, struct event *event)
}
EVENT_SPY(EVT_DM_POST_INIT, imx8m_check_clock);
static void imx8m_setup_snvs(void)
{
/* Enable SNVS clock */
clock_enable(CCGR_SNVS, 1);
/* Initialize glitch detect */
writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR);
/* Clear interrupt status */
writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
}
int arch_cpu_init(void)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
@ -594,6 +604,8 @@ int arch_cpu_init(void)
writel(0x200, &ocotp->ctrl_clr);
}
imx8m_setup_snvs();
return 0;
}

17
board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c
View File

@ -34,22 +34,6 @@ int board_phys_sdram_size(phys_size_t *size)
return 0;
}
/* IMX8M SNVS registers needed for the bootcount functionality */
#define SNVS_BASE_ADDR 0x30370000
#define SNVS_LPSR 0x4c
#define SNVS_LPLVDR 0x64
#define SNVS_LPPGDR_INIT 0x41736166
static void setup_snvs(void)
{
/* Enable SNVS clock */
clock_enable(CCGR_SNVS, 1);
/* Initialize glitch detect */
writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR);
/* Clear interrupt status */
writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
}
static void setup_mac_address(void)
{
unsigned char enetaddr[6];
@ -99,7 +83,6 @@ static void setup_boot_device(void)
int board_init(void)
{
setup_snvs();
return 0;
}

17
board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c
View File

@ -37,22 +37,6 @@ int board_phys_sdram_size(phys_size_t *size)
return 0;
}
/* IMX8M SNVS registers needed for the bootcount functionality */
#define SNVS_BASE_ADDR 0x30370000
#define SNVS_LPSR 0x4c
#define SNVS_LPLVDR 0x64
#define SNVS_LPPGDR_INIT 0x41736166
static void setup_snvs(void)
{
/* Enable SNVS clock */
clock_enable(CCGR_SNVS, 1);
/* Initialize glitch detect */
writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR);
/* Clear interrupt status */
writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
}
static void setup_eqos(void)
{
struct iomuxc_gpr_base_regs *gpr =
@ -145,7 +129,6 @@ int board_init(void)
{
setup_eqos();
setup_fec();
setup_snvs();
return 0;
}

17
board/menlo/mx8menlo/mx8menlo.c
View File

@ -12,24 +12,7 @@
#include <asm/mach-imx/iomux-v3.h>
#include <spl.h>
#define SNVS_BASE_ADDR 0x30370000
#define SNVS_LPSR 0x4c
#define SNVS_LPLVDR 0x64
#define SNVS_LPPGDR_INIT 0x41736166
static void setup_snvs(void)
{
/* Enable SNVS clock */
clock_enable(CCGR_SNVS, 1);
/* Initialize glitch detect */
writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR);
/* Clear interrupt status */
writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
}
void board_early_init(void)
{
init_uart_clk(1);
setup_snvs();
}