dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig
Move this option to Kconfig and fix up all users. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
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@ -13,6 +13,7 @@ CONFIG_CMD_GPIO=y
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# CONFIG_CMD_NFS is not set
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CONFIG_NETDEVICES=y
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CONFIG_E1000=y
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CONFIG_PCI_TEGRA=y
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CONFIG_SYS_NS16550=y
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CONFIG_USB=y
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CONFIG_DM_USB=y
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@ -13,7 +13,11 @@ CONFIG_CMD_GPIO=y
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# CONFIG_CMD_SETEXPR is not set
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# CONFIG_CMD_NFS is not set
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CONFIG_SPI_FLASH=y
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<<<<<<< HEAD
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CONFIG_SPI_FLASH_WINBOND=y
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=======
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CONFIG_PCI_TEGRA=y
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>>>>>>> dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig
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CONFIG_SYS_NS16550=y
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CONFIG_TEGRA20_SLINK=y
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CONFIG_USB=y
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@ -13,7 +13,11 @@ CONFIG_CMD_GPIO=y
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# CONFIG_CMD_SETEXPR is not set
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# CONFIG_CMD_NFS is not set
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CONFIG_SPI_FLASH=y
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<<<<<<< HEAD
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CONFIG_SPI_FLASH_WINBOND=y
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=======
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CONFIG_PCI_TEGRA=y
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>>>>>>> dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig
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CONFIG_SYS_NS16550=y
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CONFIG_TEGRA20_SLINK=y
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CONFIG_USB=y
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@ -13,7 +13,11 @@ CONFIG_CMD_GPIO=y
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# CONFIG_CMD_SETEXPR is not set
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# CONFIG_CMD_NFS is not set
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CONFIG_SPI_FLASH=y
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<<<<<<< HEAD
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CONFIG_SPI_FLASH_WINBOND=y
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=======
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CONFIG_PCI_TEGRA=y
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>>>>>>> dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig
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CONFIG_SYS_NS16550=y
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CONFIG_TEGRA114_SPI=y
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CONFIG_USB=y
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@ -15,5 +15,6 @@ CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_WINBOND=y
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CONFIG_SYS_NS16550=y
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CONFIG_TEGRA114_SPI=y
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CONFIG_PCI_TEGRA=y
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CONFIG_USB=y
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CONFIG_DM_USB=y
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@ -13,7 +13,11 @@ CONFIG_CMD_GPIO=y
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# CONFIG_CMD_SETEXPR is not set
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# CONFIG_CMD_NFS is not set
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CONFIG_SPI_FLASH=y
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<<<<<<< HEAD
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CONFIG_SPI_FLASH_WINBOND=y
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=======
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CONFIG_PCI_TEGRA=y
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>>>>>>> dm: tegra: pci: Move CONFIG_PCI_TEGRA to Kconfig
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CONFIG_SYS_NS16550=y
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CONFIG_TEGRA20_SFLASH=y
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CONFIG_USB=y
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@ -19,4 +19,14 @@ config PCI_SANDBOX
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the device tree but the normal PCI scan technique is used to find
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then.
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config PCI_TEGRA
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bool "Tegra PCI support"
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depends on TEGRA
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help
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Enable support for the PCIe controller found on some generations of
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Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has
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3 root ports with a total of 6 lanes and Tegra124 has 2 root ports
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with a total of 5 lanes. Some boards require this for Ethernet
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support to work (e.g. beaver, jetson-tk1).
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endmenu
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@ -49,7 +49,6 @@
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/* PCI host support */
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#define CONFIG_PCI
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#define CONFIG_PCI_TEGRA
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#define CONFIG_PCI_PNP
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PCI_ENUM
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@ -71,7 +71,6 @@
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/* PCI host support */
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#define CONFIG_PCI
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#define CONFIG_PCI_TEGRA
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#define CONFIG_PCI_PNP
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PCI_ENUM
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@ -73,7 +73,6 @@
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/* PCI host support */
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#define CONFIG_PCI
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#define CONFIG_PCI_TEGRA
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#define CONFIG_PCI_PNP
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PCI_ENUM
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@ -58,7 +58,6 @@
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/* PCI host support */
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#define CONFIG_PCI
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#define CONFIG_PCI_TEGRA
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#define CONFIG_PCI_PNP
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PCI_ENUM
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@ -54,7 +54,6 @@
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/* PCI host support */
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#define CONFIG_PCI
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#define CONFIG_PCI_TEGRA
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#define CONFIG_PCI_PNP
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PCI_ENUM
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@ -56,7 +56,6 @@
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/* PCI host support */
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#define CONFIG_PCI
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#define CONFIG_PCI_TEGRA
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#define CONFIG_PCI_PNP
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PCI_ENUM
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