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Merge branch 'rmobile-mx' of git://git.denx.de/u-boot-sh

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This commit is contained in:
Tom Rini 2017-12-13 17:58:27 -05:00
commit fd12455643
37 changed files with 6494 additions and 9 deletions
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4
arch/arm/dts/Makefile
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@ -393,7 +393,9 @@ dtb-$(CONFIG_RCAR_GEN3) += \
r8a7795-h3ulcb.dtb \
r8a7795-salvator-x.dtb \
r8a7796-m3ulcb.dtb \
r8a7796-salvator-x.dtb
r8a7796-salvator-x.dtb \
r8a77970-eagle.dtb \
r8a77995-draak.dtb
dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
keystone-k2l-evm.dtb \

87
arch/arm/dts/r8a77970-eagle.dts Normal file
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@ -0,0 +1,87 @@
/*
* Device Tree Source for the Eagle board
*
* Copyright (C) 2016-2017 Renesas Electronics Corp.
* Copyright (C) 2017 Cogent Embedded, Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/dts-v1/;
#include "r8a77970.dtsi"
/ {
model = "Renesas Eagle board based on r8a77970";
compatible = "renesas,eagle", "renesas,r8a77970";
aliases {
serial0 = &scif0;
ethernet0 = &avb;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_b";
function = "scif_clk";
};
avb_pins: avb {
groups = "avb0_mdc";
function = "avb0";
};
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
status = "okay";
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
status = "okay";
phy0: ethernet-phy@0 {
rxc-skew-ps = <1500>;
reg = <0>;
};
};

392
arch/arm/dts/r8a77970.dtsi Normal file
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@ -0,0 +1,392 @@
/*
* Device Tree Source for the r8a77970 SoC
*
* Copyright (C) 2016-2017 Renesas Electronics Corp.
* Copyright (C) 2017 Cogent Embedded, Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/ {
compatible = "renesas,r8a77970";
#address-cells = <2>;
#size-cells = <2>;
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
a53_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0>;
clocks = <&cpg CPG_CORE 0>;
power-domains = <&sysc 5>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
};
L2_CA53: cache-controller {
compatible = "cache";
power-domains = <&sysc 21>;
cache-unified;
cache-level = <2>;
};
};
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
u-boot,dm-pre-reloc;
};
extalr_clk: extalr {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
u-boot,dm-pre-reloc;
};
/* External SCIF clock - to be overridden by boards that provide it */
scif_clk: scif {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
u-boot,dm-pre-reloc;
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0 0xf1010000 0 0x1000>,
<0 0xf1020000 0 0x20000>,
<0 0xf1040000 0 0x20000>,
<0 0xf1060000 0 0x20000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc 32>;
resets = <&cpg 408>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
IRQ_TYPE_LEVEL_LOW)>;
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a77970-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
clocks = <&extal_clk>, <&extalr_clk>;
clock-names = "extal", "extalr";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
u-boot,dm-pre-reloc;
};
rst: reset-controller@e6160000 {
compatible = "renesas,r8a77970-rst";
reg = <0 0xe6160000 0 0x200>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a77970-sysc";
reg = <0 0xe6180000 0 0x440>;
#power-domain-cells = <1>;
};
pfc: pfc@e6060000 {
compatible = "renesas,pfc-r8a77970";
reg = <0 0xe6060000 0 0x50c>;
};
intc_ex: interrupt-controller@e61c0000 {
compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0 0xe61c0000 0 0x200>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 407>;
power-domains = <&sysc 32>;
resets = <&cpg 407>;
};
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
u-boot,dm-pre-reloc;
};
dmac1: dma-controller@e7300000 {
compatible = "renesas,dmac-r8a77970",
"renesas,rcar-dmac";
reg = <0 0xe7300000 0 0x10000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7";
clocks = <&cpg CPG_MOD 218>;
clock-names = "fck";
power-domains = <&sysc 32>;
resets = <&cpg 218>;
#dma-cells = <1>;
dma-channels = <8>;
};
dmac2: dma-controller@e7310000 {
compatible = "renesas,dmac-r8a77970",
"renesas,rcar-dmac";
reg = <0 0xe7310000 0 0x10000>;
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7";
clocks = <&cpg CPG_MOD 217>;
clock-names = "fck";
power-domains = <&sysc 32>;
resets = <&cpg 217>;
#dma-cells = <1>;
dma-channels = <8>;
};
hscif0: serial@e6540000 {
compatible = "renesas,hscif-r8a77970",
"renesas,rcar-gen3-hscif",
"renesas,hscif";
reg = <0 0xe6540000 0 96>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 520>,
<&cpg CPG_CORE 9>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x31>, <&dmac1 0x30>,
<&dmac2 0x31>, <&dmac2 0x30>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 520>;
status = "disabled";
};
hscif1: serial@e6550000 {
compatible = "renesas,hscif-r8a77970",
"renesas,rcar-gen3-hscif",
"renesas,hscif";
reg = <0 0xe6550000 0 96>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 519>,
<&cpg CPG_CORE 9>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x33>, <&dmac1 0x32>,
<&dmac2 0x33>, <&dmac2 0x32>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 519>;
status = "disabled";
};
hscif2: serial@e6560000 {
compatible = "renesas,hscif-r8a77970",
"renesas,rcar-gen3-hscif",
"renesas,hscif";
reg = <0 0xe6560000 0 96>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 518>,
<&cpg CPG_CORE 9>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x35>, <&dmac1 0x34>,
<&dmac2 0x35>, <&dmac2 0x34>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 518>;
status = "disabled";
};
hscif3: serial@e66a0000 {
compatible = "renesas,hscif-r8a77970",
"renesas,rcar-gen3-hscif", "renesas,hscif";
reg = <0 0xe66a0000 0 96>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 517>,
<&cpg CPG_CORE 9>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x37>, <&dmac1 0x36>,
<&dmac2 0x37>, <&dmac2 0x36>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 517>;
status = "disabled";
};
scif0: serial@e6e60000 {
compatible = "renesas,scif-r8a77970",
"renesas,rcar-gen3-scif",
"renesas,scif";
reg = <0 0xe6e60000 0 64>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 207>,
<&cpg CPG_CORE 9>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x51>, <&dmac1 0x50>,
<&dmac2 0x51>, <&dmac2 0x50>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 207>;
status = "disabled";
};
scif1: serial@e6e68000 {
compatible = "renesas,scif-r8a77970",
"renesas,rcar-gen3-scif",
"renesas,scif";
reg = <0 0xe6e68000 0 64>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 206>,
<&cpg CPG_CORE 9>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x53>, <&dmac1 0x52>,
<&dmac2 0x53>, <&dmac2 0x52>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 206>;
status = "disabled";
};
scif3: serial@e6c50000 {
compatible = "renesas,scif-r8a77970",
"renesas,rcar-gen3-scif",
"renesas,scif";
reg = <0 0xe6c50000 0 64>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 204>,
<&cpg CPG_CORE 9>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x57>, <&dmac1 0x56>,
<&dmac2 0x57>, <&dmac2 0x56>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 204>;
status = "disabled";
};
scif4: serial@e6c40000 {
compatible = "renesas,scif-r8a77970",
"renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xe6c40000 0 64>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 203>,
<&cpg CPG_CORE 9>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x59>, <&dmac1 0x58>,
<&dmac2 0x59>, <&dmac2 0x58>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc 32>;
resets = <&cpg 203>;
status = "disabled";
};
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a77970",
"renesas,etheravb-rcar-gen3";
reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15",
"ch16", "ch17", "ch18", "ch19",
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc 32>;
resets = <&cpg 812>;
phy-mode = "rgmii-id";
#address-cells = <1>;
#size-cells = <0>;
};
};
};

124
arch/arm/dts/r8a77995-draak.dts Normal file
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@ -0,0 +1,124 @@
/*
* Device Tree Source for the Draak board
*
* Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2017 Glider bvba
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/dts-v1/;
#include "r8a77995.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Renesas Draak board based on r8a77995";
compatible = "renesas,draak", "renesas,r8a77995";
aliases {
serial0 = &scif2;
ethernet0 = &avb;
};
chosen {
bootargs = "ignore_loglevel";
stdout-path = "serial0:115200n8";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x18000000>;
};
};
&extal_clk {
clock-frequency = <48000000>;
};
&pfc {
avb0_pins: avb {
mux {
groups = "avb0_link", "avb0_mdc", "avb0_mii";
function = "avb0";
};
};
pwm0_pins: pwm0 {
groups = "pwm0_c";
function = "pwm0";
};
pwm1_pins: pwm1 {
groups = "pwm1_c";
function = "pwm1";
};
scif2_pins: scif2 {
groups = "scif2_data";
function = "scif2";
};
usb0_pins: usb0 {
groups = "usb0";
function = "usb0";
};
};
&ehci0 {
status = "okay";
};
&ohci0 {
status = "okay";
};
&avb {
pinctrl-0 = <&avb0_pins>;
pinctrl-names = "default";
renesas,no-ether-link;
phy-handle = <&phy0>;
status = "okay";
phy0: ethernet-phy@0 {
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio5>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
};
};
&scif2 {
pinctrl-0 = <&scif2_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb2_phy0 {
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";
status = "okay";
};
&pwm0 {
pinctrl-0 = <&pwm0_pins>;
pinctrl-names = "default";
status = "okay";
};
&pwm1 {
pinctrl-0 = <&pwm1_pins>;
pinctrl-names = "default";
status = "okay";
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};

410
arch/arm/dts/r8a77995.dtsi Normal file
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@ -0,0 +1,410 @@
/*
* Device Tree Source for the r8a77995 SoC
*
* Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2017 Glider bvba
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a77995-sysc.h>
/ {
compatible = "renesas,r8a77995";
#address-cells = <2>;
#size-cells = <2>;
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
a53_0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0>;
device_type = "cpu";
power-domains = <&sysc R8A77995_PD_CA53_CPU0>;
next-level-cache = <&L2_CA53>;
enable-method = "psci";
};
L2_CA53: cache-controller-1 {
compatible = "cache";
power-domains = <&sysc R8A77995_PD_CA53_SCU>;
cache-unified;
cache-level = <2>;
};
};
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
u-boot,dm-pre-reloc;
};
scif_clk: scif {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
u-boot,dm-pre-reloc;
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0xf1010000 0 0x1000>,
<0x0 0xf1020000 0 0x20000>,
<0x0 0xf1040000 0 0x20000>,
<0x0 0xf1060000 0 0x20000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 408>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a77995-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 402>;
status = "disabled";
};
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a77995-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
clocks = <&extal_clk>;
clock-names = "extal";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
u-boot,dm-pre-reloc;
};
rst: reset-controller@e6160000 {
compatible = "renesas,r8a77995-rst";
reg = <0 0xe6160000 0 0x0200>;
};
pfc: pin-controller@e6060000 {
compatible = "renesas,pfc-r8a77995";
reg = <0 0xe6060000 0 0x508>;
};
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
u-boot,dm-pre-reloc;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a77995-sysc";
reg = <0 0xe6180000 0 0x0400>;
#power-domain-cells = <1>;
};
intc_ex: interrupt-controller@e61c0000 {
compatible = "renesas,intc-ex-r8a77995", "renesas,irqc";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0 0xe61c0000 0 0x200>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 407>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 407>;
};
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a77995",
"renesas,rcar-gen3-gpio",
"renesas,gpio-rcar";
reg = <0 0xe6050000 0 0x50>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 0 9>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 912>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 912>;
};
gpio1: gpio@e6051000 {
compatible = "renesas,gpio-r8a77995",
"renesas,rcar-gen3-gpio",
"renesas,gpio-rcar";
reg = <0 0xe6051000 0 0x50>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 32 32>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 911>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 911>;
};
gpio2: gpio@e6052000 {
compatible = "renesas,gpio-r8a77995",
"renesas,rcar-gen3-gpio",
"renesas,gpio-rcar";
reg = <0 0xe6052000 0 0x50>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 64 32>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 910>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 910>;
};
gpio3: gpio@e6053000 {
compatible = "renesas,gpio-r8a77995",
"renesas,rcar-gen3-gpio",
"renesas,gpio-rcar";
reg = <0 0xe6053000 0 0x50>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 96 10>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 909>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 909>;
};
gpio4: gpio@e6054000 {
compatible = "renesas,gpio-r8a77995",
"renesas,rcar-gen3-gpio",
"renesas,gpio-rcar";
reg = <0 0xe6054000 0 0x50>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 128 32>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 908>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 908>;
};
gpio5: gpio@e6055000 {
compatible = "renesas,gpio-r8a77995",
"renesas,rcar-gen3-gpio",
"renesas,gpio-rcar";
reg = <0 0xe6055000 0 0x50>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 160 21>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 907>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 907>;
};
gpio6: gpio@e6055400 {
compatible = "renesas,gpio-r8a77995",
"renesas,rcar-gen3-gpio",
"renesas,gpio-rcar";
reg = <0 0xe6055400 0 0x50>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 192 14>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 906>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 906>;
};
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a77995",
"renesas,etheravb-rcar-gen3";
reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15",
"ch16", "ch17", "ch18", "ch19",
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii-txid";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
scif2: serial@e6e88000 {
compatible = "renesas,scif-r8a77995",
"renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xe6e88000 0 64>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 310>,
<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 310>;
status = "disabled";
};
pwm0: pwm@e6e30000 {
compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
reg = <0 0xe6e30000 0 0x8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 523>;
status = "disabled";
};
pwm1: pwm@e6e31000 {
compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
reg = <0 0xe6e31000 0 0x8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 523>;
status = "disabled";
};
pwm2: pwm@e6e32000 {
compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
reg = <0 0xe6e32000 0 0x8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 523>;
status = "disabled";
};
pwm3: pwm@e6e33000 {
compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
reg = <0 0xe6e33000 0 0x8>;
#pwm-cells = <2>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 523>;
status = "disabled";
};
ehci0: usb@ee080100 {
compatible = "generic-ehci";
reg = <0 0xee080100 0 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>;
phys = <&usb2_phy0>;
phy-names = "usb";
companion = <&ohci0>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 703>;
status = "disabled";
};
ohci0: usb@ee080000 {
compatible = "generic-ohci";
reg = <0 0xee080000 0 0x100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>;
phys = <&usb2_phy0>;
phy-names = "usb";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 703>;
status = "disabled";
};
usb2_phy0: usb-phy@ee080200 {
compatible = "renesas,usb2-phy-r8a77995",
"renesas,rcar-gen3-usb2-phy";
reg = <0 0xee080200 0 0x700>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>;
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 703>;
#phy-cells = <0>;
status = "disabled";
};
};
};

18
arch/arm/mach-rmobile/Kconfig.64
View File

@ -9,12 +9,28 @@ config R8A7795
config R8A7796
bool "Renesas SoC R8A7796"
config R8A77970
bool "Renesas SoC R8A77970"
config R8A77995
bool "Renesas SoC R8A77995"
endchoice
choice
prompt "Renesus ARM64 SoCs board select"
optional
config TARGET_DRAAK
bool "Draak board"
help
Support for Renesas R-Car Gen3 Draak platform
config TARGET_EAGLE
bool "Eagle board"
help
Support for Renesas R-Car Gen3 Eagle platform
config TARGET_SALVATOR_X
bool "Salvator-X board"
help
@ -30,6 +46,8 @@ endchoice
config SYS_SOC
default "rmobile"
source "board/renesas/draak/Kconfig"
source "board/renesas/eagle/Kconfig"
source "board/renesas/salvator-x/Kconfig"
source "board/renesas/ulcb/Kconfig"

2
arch/arm/mach-rmobile/cpu_info.c
View File

@ -61,6 +61,8 @@ static const struct {
{ RMOBILE_CPU_TYPE_R8A7794, "R8A7794" },
{ RMOBILE_CPU_TYPE_R8A7795, "R8A7795" },
{ RMOBILE_CPU_TYPE_R8A7796, "R8A7796" },
{ RMOBILE_CPU_TYPE_R8A77970, "R8A77970" },
{ RMOBILE_CPU_TYPE_R8A77995, "R8A77995" },
{ 0x0, "CPU" },
};

2
arch/arm/mach-rmobile/include/mach/rmobile.h
View File

@ -33,6 +33,8 @@
#define RMOBILE_CPU_TYPE_R8A7794 0x4C
#define RMOBILE_CPU_TYPE_R8A7795 0x4F
#define RMOBILE_CPU_TYPE_R8A7796 0x52
#define RMOBILE_CPU_TYPE_R8A77970 0x54
#define RMOBILE_CPU_TYPE_R8A77995 0x58
#ifndef __ASSEMBLY__
u32 rmobile_get_cpu_type(void);

46
arch/arm/mach-rmobile/memmap-gen3.c
View File

@ -49,6 +49,46 @@ static struct mm_region r8a7796_mem_map[] = {
}
};
static struct mm_region r8a77970_mem_map[] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0xe0000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xe0000000UL,
.phys = 0xe0000000UL,
.size = 0xe0000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
static struct mm_region r8a77995_mem_map[] = {
{
.virt = 0x0UL,
.phys = 0x0UL,
.size = 0xe0000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
}, {
.virt = 0xe0000000UL,
.phys = 0xe0000000UL,
.size = 0xe0000000UL,
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN
}, {
/* List terminator */
0,
}
};
struct mm_region *mem_map = r8a7795_mem_map;
void rcar_gen3_memmap_fixup(void)
@ -62,5 +102,11 @@ void rcar_gen3_memmap_fixup(void)
case RMOBILE_CPU_TYPE_R8A7796:
mem_map = r8a7796_mem_map;
break;
case RMOBILE_CPU_TYPE_R8A77970:
mem_map = r8a77970_mem_map;
break;
case RMOBILE_CPU_TYPE_R8A77995:
mem_map = r8a77995_mem_map;
break;
}
}

15
board/renesas/draak/Kconfig Normal file
View File

@ -0,0 +1,15 @@
if TARGET_DRAAK
config SYS_SOC
default "rmobile"
config SYS_BOARD
default "draak"
config SYS_VENDOR
default "renesas"
config SYS_CONFIG_NAME
default "draak"
endif

6
board/renesas/draak/MAINTAINERS Normal file
View File

@ -0,0 +1,6 @@
DRAAK BOARD
M: Marek Vasut <marek.vasut+renesas@gmail.com>
S: Maintained
F: board/renesas/draak/
F: include/configs/draak.h
F: configs/r8a77995_draak_defconfig

9
board/renesas/draak/Makefile Normal file
View File

@ -0,0 +1,9 @@
#
# board/renesas/draak/Makefile
#
# Copyright (C) 2015 Renesas Electronics Corporation
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := draak.o

133
board/renesas/draak/draak.c Normal file
View File

@ -0,0 +1,133 @@
/*
* board/renesas/draak/draak.c
* This file is Draak board support.
*
* Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <malloc.h>
#include <netdev.h>
#include <dm.h>
#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/sh_sdhi.h>
#include <i2c.h>
#include <mmc.h>
DECLARE_GLOBAL_DATA_PTR;
#define CPGWPCR 0xE6150904
#define CPGWPR 0xE615090C
#define CLK2MHZ(clk) (clk / 1000 / 1000)
void s_init(void)
{
struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
/* Watchdog init */
writel(0xA5A5A500, &rwdt->rwtcsra);
writel(0xA5A5A500, &swdt->swtcsra);
writel(0xA5A50000, CPGWPCR);
writel(0xFFFFFFFF, CPGWPR);
}
#define GSX_MSTP112 BIT(12) /* 3DG */
#define TMU0_MSTP125 BIT(25) /* secure */
#define TMU1_MSTP124 BIT(24) /* non-secure */
#define SCIF2_MSTP310 BIT(10) /* SCIF2 */
#define DVFS_MSTP926 BIT(26)
#define HSUSB_MSTP704 BIT(4) /* HSUSB */
int board_early_init_f(void)
{
/* TMU0,1 */ /* which use ? */
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
/* DVFS for reset */
mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926);
#endif
return 0;
}
/* SYSC */
/* R/- 32 Power status register 2(3DG) */
#define SYSC_PWRSR2 0xE6180100
/* -/W 32 Power resume control register 2 (3DG) */
#define SYSC_PWRONCR2 0xE618010C
/* HSUSB block registers */
#define HSUSB_REG_LPSTS 0xE6590102
#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
#define HSUSB_REG_UGCTRL2 0xE6590184
#define HSUSB_REG_UGCTRL2_USB0SEL 0x30
#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
/* USB1 pull-up */
setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);
/* Configure the HSUSB block */
mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);
/* Choice USB0SEL */
clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,
HSUSB_REG_UGCTRL2_USB0SEL_EHCI);
/* low power status */
setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
return 0;
}
int dram_init(void)
{
if (fdtdec_setup_memory_size() != 0)
return -EINVAL;
return 0;
}
int dram_init_banksize(void)
{
fdtdec_setup_memory_banksize();
return 0;
}
#define RST_BASE 0xE6160000
#define RST_CA57RESCNT (RST_BASE + 0x40)
#define RST_CA53RESCNT (RST_BASE + 0x44)
#define RST_RSTOUTCR (RST_BASE + 0x58)
#define RST_CA57_CODE 0xA5A5000F
#define RST_CA53_CODE 0x5A5A000F
void reset_cpu(ulong addr)
{
unsigned long midr, cputype;
asm volatile("mrs %0, midr_el1" : "=r" (midr));
cputype = (midr >> 4) & 0xfff;
if (cputype == 0xd03)
writel(RST_CA53_CODE, RST_CA53RESCNT);
else if (cputype == 0xd07)
writel(RST_CA57_CODE, RST_CA57RESCNT);
else
hang();
}

15
board/renesas/eagle/Kconfig Normal file
View File

@ -0,0 +1,15 @@
if TARGET_EAGLE
config SYS_SOC
default "rmobile"
config SYS_BOARD
default "eagle"
config SYS_VENDOR
default "renesas"
config SYS_CONFIG_NAME
default "eagle"
endif

6
board/renesas/eagle/MAINTAINERS Normal file
View File

@ -0,0 +1,6 @@
EAGLE BOARD
M: Marek Vasut <marek.vasut+renesas@gmail.com>
S: Maintained
F: board/renesas/eagle/
F: include/configs/eagle.h
F: configs/r8a77970_eagle_defconfig

9
board/renesas/eagle/Makefile Normal file
View File

@ -0,0 +1,9 @@
#
# board/renesas/eagle/Makefile
#
# Copyright (C) 2015 Renesas Electronics Corporation
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := eagle.o

110
board/renesas/eagle/eagle.c Normal file
View File

@ -0,0 +1,110 @@
/*
* board/renesas/eagle/eagle.c
* This file is Eagle board support.
*
* Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <malloc.h>
#include <netdev.h>
#include <dm.h>
#include <dm/platform_data/serial_sh.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/rcar-mstp.h>
#include <asm/arch/sh_sdhi.h>
#include <i2c.h>
#include <mmc.h>
DECLARE_GLOBAL_DATA_PTR;
#define CPGWPCR 0xE6150904
#define CPGWPR 0xE615090C
/* PLL */
#define PLL0CR 0xE61500D8
#define PLL0_STC_MASK 0x7F000000
#define PLL0_STC_OFFSET 24
#define CLK2MHZ(clk) (clk / 1000 / 1000)
void s_init(void)
{
struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
u32 stc;
/* Watchdog init */
writel(0xA5A5A500, &rwdt->rwtcsra);
writel(0xA5A5A500, &swdt->swtcsra);
/* CPU frequency setting. Set to 0.8GHz */
stc = ((800 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_OFFSET;
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
}
#define TMU0_MSTP125 BIT(25) /* secure */
int board_early_init_f(void)
{
writel(0xA5A5FFFF, CPGWPCR);
writel(0x5A5A0000, CPGWPR);
/* TMU0 */
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
return 0;
}
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
return 0;
}
int dram_init(void)
{
if (fdtdec_setup_memory_size() != 0)
return -EINVAL;
return 0;
}
int dram_init_banksize(void)
{
fdtdec_setup_memory_banksize();
return 0;
}
#define RST_BASE 0xE6160000
#define RST_CA57RESCNT (RST_BASE + 0x40)
#define RST_CA53RESCNT (RST_BASE + 0x44)
#define RST_RSTOUTCR (RST_BASE + 0x58)
#define RST_CA57_CODE 0xA5A5000F
#define RST_CA53_CODE 0x5A5A000F
void reset_cpu(ulong addr)
{
unsigned long midr, cputype;
asm volatile("mrs %0, midr_el1" : "=r" (midr));
cputype = (midr >> 4) & 0xfff;
if (cputype == 0xd03)
writel(RST_CA53_CODE, RST_CA53RESCNT);
else if (cputype == 0xd07)
writel(RST_CA57_CODE, RST_CA57RESCNT);
else
hang();
}

56
configs/r8a77970_eagle_defconfig Normal file
View File

@ -0,0 +1,56 @@
CONFIG_ARM=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_RCAR_GEN3=y
CONFIG_R8A77970=y
CONFIG_TARGET_EAGLE=y
CONFIG_DEFAULT_DEVICE_TREE="r8a77970-eagle"
CONFIG_SMBIOS_PRODUCT_NAME=""
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_DEFAULT_FDT_FILE="r8a77970-eagle.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DM_GPIO=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_DM_MMC=y
CONFIG_MMC_UNIPHIER=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_PINCTRL_PFC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_SMBIOS_MANUFACTURER=""

61
configs/r8a77995_draak_defconfig Normal file
View File

@ -0,0 +1,61 @@
CONFIG_ARM=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_RCAR_GEN3=y
CONFIG_R8A77995=y
CONFIG_TARGET_DRAAK=y
CONFIG_DEFAULT_DEVICE_TREE="r8a77995-draak"
CONFIG_SMBIOS_PRODUCT_NAME=""
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySC0,115200 rw root=/dev/nfs nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
CONFIG_DEFAULT_FDT_FILE="r8a77995-draak.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
CONFIG_DM_GPIO=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
CONFIG_DM_MMC=y
CONFIG_MMC_UNIPHIER=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_CFI_FLASH=y
CONFIG_RENESAS_RPC_HF=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_RENESAS_RAVB=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
CONFIG_PINCTRL_PFC=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_SMBIOS_MANUFACTURER=""

5
drivers/clk/renesas/Kconfig
View File

@ -5,9 +5,8 @@ config CLK_RENESAS
Enable support for clock present on Renesas RCar SoCs.
config CLK_RCAR_GEN3
bool "Renesas RCar Gen3 R8A7795/R8A7796 clock driver"
bool "Renesas RCar Gen3 clock driver"
def_bool y if RCAR_GEN3
depends on CLK_RENESAS
help
Enable this to support the clocks on Renesas RCar Gen3
R8A7795 and R8A7796 SoC.
Enable this to support the clocks on Renesas RCar Gen3 SoC.

289
drivers/clk/renesas/clk-rcar-gen3.c
View File

@ -1,5 +1,5 @@
/*
* Renesas RCar Gen3 R8A7795/R8A7796 CPG MSSR driver
* Renesas RCar Gen3 CPG MSSR driver
*
* Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
*
@ -20,6 +20,8 @@
#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
#include <dt-bindings/clock/r8a77970-cpg-mssr.h>
#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
#define CPG_RST_MODEMR 0x0060
@ -126,6 +128,10 @@ enum clk_types {
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
#define DEF_GEN3_RPC(_name, _id, _parent, _offset) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset)
#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
_div_clean) \
DEF_BASE(_name, _id, CLK_TYPE_FF, \
(_parent_clean), .div = (_div_clean), 1)
/*
* Definitions of Module Clocks
@ -154,6 +160,8 @@ enum rcar_gen3_clk_types {
CLK_TYPE_GEN3_SD,
CLK_TYPE_GEN3_RPC,
CLK_TYPE_GEN3_R,
CLK_TYPE_GEN3_PE,
CLK_TYPE_GEN3_Z2,
};
struct rcar_gen3_cpg_pll_config {
@ -179,6 +187,11 @@ enum clk_ids {
CLK_PLL4,
CLK_PLL1_DIV2,
CLK_PLL1_DIV4,
CLK_PLL0D2,
CLK_PLL0D3,
CLK_PLL0D5,
CLK_PLL1D2,
CLK_PE,
CLK_S0,
CLK_S1,
CLK_S2,
@ -558,7 +571,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = {
DEF_MOD("can-fd", 914, R8A7796_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A7796_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4),
DEF_MOD("rpc", 917, R8A7795_CLK_RPC),
DEF_MOD("rpc", 917, R8A7796_CLK_RPC),
DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6),
DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP),
@ -595,6 +608,219 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = {
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
};
static const struct cpg_core_clk r8a77970_core_clks[] = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
/* Internal Core Clocks */
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
/* Core Clock Outputs */
DEF_BASE("z2", R8A77970_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL1_DIV4),
DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED("zx", R8A77970_CLK_ZX, CLK_PLL1_DIV2, 3, 1),
DEF_FIXED("s1d1", R8A77970_CLK_S1D1, CLK_S1, 1, 1),
DEF_FIXED("s1d2", R8A77970_CLK_S1D2, CLK_S1, 2, 1),
DEF_FIXED("s1d4", R8A77970_CLK_S1D4, CLK_S1, 4, 1),
DEF_FIXED("s2d1", R8A77970_CLK_S2D1, CLK_S2, 1, 1),
DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_S2, 2, 1),
DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_S2, 4, 1),
DEF_GEN3_SD("sd0", R8A77970_CLK_SD0, CLK_PLL1_DIV4, 0x0074),
DEF_GEN3_RPC("rpc", R8A77970_CLK_RPC, CLK_RPCSRC, 0x238),
DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
/* NOTE: HDMI, CSI, CAN etc. clock are missing */
DEF_BASE("r", R8A77970_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
};
static const struct mssr_mod_clk r8a77970_mod_clks[] = {
DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1),
DEF_MOD("scif4", 203, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
DEF_MOD("scif3", 204, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
DEF_MOD("scif1", 206, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
DEF_MOD("scif0", 207, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
DEF_MOD("msiof3", 208, R8A77970_CLK_MSO),
DEF_MOD("msiof2", 209, R8A77970_CLK_MSO),
DEF_MOD("msiof1", 210, R8A77970_CLK_MSO),
DEF_MOD("msiof0", 211, R8A77970_CLK_MSO),
DEF_MOD("mfis", 213, R8A77970_CLK_S2D2), /* @@ H3=S3D2 */
DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
DEF_MOD("sdif", 314, R8A77970_CLK_SD0),
DEF_MOD("rwdt0", 402, R8A77970_CLK_R),
DEF_MOD("intc-ex", 407, R8A77970_CLK_CP),
DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
DEF_MOD("hscif3", 517, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
DEF_MOD("hscif2", 518, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
DEF_MOD("hscif1", 519, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
DEF_MOD("hscif0", 520, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
DEF_MOD("thermal", 522, R8A77970_CLK_CP),
DEF_MOD("pwm", 523, R8A77970_CLK_S2D4),
DEF_MOD("fcpvd0", 603, R8A77970_CLK_S2D1),
DEF_MOD("vspd0", 623, R8A77970_CLK_S2D1),
DEF_MOD("csi40", 716, R8A77970_CLK_CSI0),
DEF_MOD("du0", 724, R8A77970_CLK_S2D1),
DEF_MOD("lvds", 727, R8A77970_CLK_S2D1),
DEF_MOD("vin3", 808, R8A77970_CLK_S2D1),
DEF_MOD("vin2", 809, R8A77970_CLK_S2D1),
DEF_MOD("vin1", 810, R8A77970_CLK_S2D1),
DEF_MOD("vin0", 811, R8A77970_CLK_S2D1),
DEF_MOD("etheravb", 812, R8A77970_CLK_S2D2),
DEF_MOD("isp", 817, R8A77970_CLK_S2D1),
DEF_MOD("gpio5", 907, R8A77970_CLK_CP),
DEF_MOD("gpio4", 908, R8A77970_CLK_CP),
DEF_MOD("gpio3", 909, R8A77970_CLK_CP),
DEF_MOD("gpio2", 910, R8A77970_CLK_CP),
DEF_MOD("gpio1", 911, R8A77970_CLK_CP),
DEF_MOD("gpio0", 912, R8A77970_CLK_CP),
DEF_MOD("can-fd", 914, R8A77970_CLK_S2D2),
DEF_MOD("rpc", 917, R8A77970_CLK_RPC),
DEF_MOD("i2c4", 927, R8A77970_CLK_S2D2),
DEF_MOD("i2c3", 928, R8A77970_CLK_S2D2),
DEF_MOD("i2c2", 929, R8A77970_CLK_S2D2),
DEF_MOD("i2c1", 930, R8A77970_CLK_S2D2),
DEF_MOD("i2c0", 931, R8A77970_CLK_S2D2),
};
static const struct cpg_core_clk r8a77995_core_clks[] = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
/* Internal Core Clocks */
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 4, 250),
DEF_FIXED(".pll0d2", CLK_PLL0D2, CLK_PLL0, 2, 1),
DEF_FIXED(".pll0d3", CLK_PLL0D3, CLK_PLL0, 3, 1),
DEF_FIXED(".pll0d5", CLK_PLL0D5, CLK_PLL0, 5, 1),
DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
DEF_FIXED(".pe", CLK_PE, CLK_PLL0D3, 4, 1),
DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
/* Core Clock Outputs */
DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1),
DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1),
DEF_FIXED("zx", R8A77995_CLK_ZX, CLK_PLL1, 3, 1),
DEF_FIXED("s0d1", R8A77995_CLK_S0D1, CLK_S0, 1, 1),
DEF_FIXED("s1d1", R8A77995_CLK_S1D1, CLK_S1, 1, 1),
DEF_FIXED("s1d2", R8A77995_CLK_S1D2, CLK_S1, 2, 1),
DEF_FIXED("s1d4", R8A77995_CLK_S1D4, CLK_S1, 4, 1),
DEF_FIXED("s2d1", R8A77995_CLK_S2D1, CLK_S2, 1, 1),
DEF_FIXED("s2d2", R8A77995_CLK_S2D2, CLK_S2, 2, 1),
DEF_FIXED("s2d4", R8A77995_CLK_S2D4, CLK_S2, 4, 1),
DEF_FIXED("s3d1", R8A77995_CLK_S3D1, CLK_S3, 1, 1),
DEF_FIXED("s3d2", R8A77995_CLK_S3D2, CLK_S3, 2, 1),
DEF_FIXED("s3d4", R8A77995_CLK_S3D4, CLK_S3, 4, 1),
DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1),
DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("osc", R8A77995_CLK_OSC, CLK_EXTAL, 384, 1),
DEF_FIXED("r", R8A77995_CLK_R, CLK_EXTAL, 1536, 1),
DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2),
DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, CLK_SDSRC, 0x268),
};
static const struct mssr_mod_clk r8a77995_mod_clks[] = {
DEF_MOD("scif5", 202, R8A77995_CLK_S3D4C),
DEF_MOD("scif4", 203, R8A77995_CLK_S3D4C),
DEF_MOD("scif3", 204, R8A77995_CLK_S3D4C),
DEF_MOD("scif1", 206, R8A77995_CLK_S3D4C),
DEF_MOD("scif0", 207, R8A77995_CLK_S3D4C),
DEF_MOD("msiof3", 208, R8A77995_CLK_MSO),
DEF_MOD("msiof2", 209, R8A77995_CLK_MSO),
DEF_MOD("msiof1", 210, R8A77995_CLK_MSO),
DEF_MOD("msiof0", 211, R8A77995_CLK_MSO),
DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1),
DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1),
DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1),
DEF_MOD("cmt3", 300, R8A77995_CLK_R),
DEF_MOD("cmt2", 301, R8A77995_CLK_R),
DEF_MOD("cmt1", 302, R8A77995_CLK_R),
DEF_MOD("cmt0", 303, R8A77995_CLK_R),
DEF_MOD("scif2", 310, R8A77995_CLK_S3D4C),
DEF_MOD("emmc0", 312, R8A77995_CLK_SD0),
DEF_MOD("usb-dmac0", 330, R8A77995_CLK_S3D1),
DEF_MOD("usb-dmac1", 331, R8A77995_CLK_S3D1),
DEF_MOD("rwdt", 402, R8A77995_CLK_R),
DEF_MOD("intc-ex", 407, R8A77995_CLK_CP),
DEF_MOD("intc-ap", 408, R8A77995_CLK_S3D1),
DEF_MOD("audmac0", 502, R8A77995_CLK_S3D1),
DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C),
DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C),
DEF_MOD("thermal", 522, R8A77995_CLK_CP),
DEF_MOD("pwm", 523, R8A77995_CLK_S3D4C),
DEF_MOD("fcpvd1", 602, R8A77995_CLK_S1D2),
DEF_MOD("fcpvd0", 603, R8A77995_CLK_S1D2),
DEF_MOD("fcpvbs", 607, R8A77995_CLK_S0D1),
DEF_MOD("vspd1", 622, R8A77995_CLK_S1D2),
DEF_MOD("vspd0", 623, R8A77995_CLK_S1D2),
DEF_MOD("vspbs", 627, R8A77995_CLK_S0D1),
DEF_MOD("ehci0", 703, R8A77995_CLK_S3D2),
DEF_MOD("hsusb", 704, R8A77995_CLK_S3D2),
DEF_MOD("du1", 723, R8A77995_CLK_S2D1),
DEF_MOD("du0", 724, R8A77995_CLK_S2D1),
DEF_MOD("lvds", 727, R8A77995_CLK_S2D1),
DEF_MOD("vin7", 804, R8A77995_CLK_S1D2),
DEF_MOD("vin6", 805, R8A77995_CLK_S1D2),
DEF_MOD("vin5", 806, R8A77995_CLK_S1D2),
DEF_MOD("vin4", 807, R8A77995_CLK_S1D2),
DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2),
DEF_MOD("imr0", 823, R8A77995_CLK_S1D2),
DEF_MOD("gpio6", 906, R8A77995_CLK_S3D4),
DEF_MOD("gpio5", 907, R8A77995_CLK_S3D4),
DEF_MOD("gpio4", 908, R8A77995_CLK_S3D4),
DEF_MOD("gpio3", 909, R8A77995_CLK_S3D4),
DEF_MOD("gpio2", 910, R8A77995_CLK_S3D4),
DEF_MOD("gpio1", 911, R8A77995_CLK_S3D4),
DEF_MOD("gpio0", 912, R8A77995_CLK_S3D4),
DEF_MOD("can-fd", 914, R8A77995_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4),
DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2),
DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2),
DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2),
DEF_MOD("i2c0", 931, R8A77995_CLK_S3D2),
DEF_MOD("ssi-all", 1005, R8A77995_CLK_S3D4),
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
DEF_MOD("scu-all", 1017, R8A77995_CLK_S3D4),
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
};
/*
* CPG Clock Data
*/
@ -931,6 +1157,7 @@ static ulong gen3_clk_get_rate(struct clk *clk)
return rate;
case CLK_TYPE_FF:
case CLK_TYPE_GEN3_PE: /* FIXME */
rate = (gen3_clk_get_rate(&parent) * core->mult) / core->div;
debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n",
__func__, __LINE__,
@ -1015,6 +1242,8 @@ static const struct clk_ops gen3_clk_ops = {
enum gen3_clk_model {
CLK_R8A7795,
CLK_R8A7796,
CLK_R8A77970,
CLK_R8A77995,
};
static int gen3_clk_probe(struct udevice *dev)
@ -1050,6 +1279,26 @@ static int gen3_clk_probe(struct udevice *dev)
if (ret < 0)
return ret;
break;
case CLK_R8A77970:
priv->core_clk = r8a77970_core_clks;
priv->core_clk_size = ARRAY_SIZE(r8a77970_core_clks);
priv->mod_clk = r8a77970_mod_clks;
priv->mod_clk_size = ARRAY_SIZE(r8a77970_mod_clks);
ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
"renesas,r8a77970-rst");
if (ret < 0)
return ret;
break;
case CLK_R8A77995:
priv->core_clk = r8a77995_core_clks;
priv->core_clk_size = ARRAY_SIZE(r8a77995_core_clks);
priv->mod_clk = r8a77995_mod_clks;
priv->mod_clk_size = ARRAY_SIZE(r8a77995_mod_clks);
ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
"renesas,r8a77995-rst");
if (ret < 0)
return ret;
break;
default:
return -EINVAL;
}
@ -1068,9 +1317,11 @@ static int gen3_clk_probe(struct udevice *dev)
if (ret < 0)
return ret;
ret = clk_get_by_name(dev, "extalr", &priv->clk_extalr);
if (ret < 0)
return ret;
if (model != CLK_R8A77995) {
ret = clk_get_by_name(dev, "extalr", &priv->clk_extalr);
if (ret < 0)
return ret;
}
return 0;
}
@ -1098,6 +1349,24 @@ static struct mstp_stop_table r8a7796_mstp_table[] = {
{ 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 },
};
static struct mstp_stop_table r8a77970_mstp_table[] = {
{ 0x00230000, 0x0 }, { 0xFFFFFFFF, 0x0 },
{ 0x14062FD8, 0x2040 }, { 0xFFFFFFDF, 0x400 },
{ 0x80000184, 0x180 }, { 0x83FFFFFF, 0x0 },
{ 0xFFFFFFFF, 0x0 }, { 0xFFFFFFFF, 0x0 },
{ 0x7FF3FFF4, 0x0 }, { 0xFBF7FF97, 0x0 },
{ 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 },
};
static struct mstp_stop_table r8a77995_mstp_table[] = {
{ 0x00200000, 0x0 }, { 0xFFFFFFFF, 0x0 },
{ 0x340E2FDC, 0x2040 }, { 0xFFFFFFDF, 0x400 },
{ 0x80000184, 0x180 }, { 0xC3FFFFFF, 0x0 },
{ 0xFFFFFFFF, 0x0 }, { 0xFFFFFFFF, 0x0 },
{ 0x01F1FFF7, 0x0 }, { 0xFFFFFFFE, 0x0 },
{ 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 },
};
#define TSTR0 0x04
#define TSTR0_STR0 BIT(0)
@ -1117,6 +1386,14 @@ static int gen3_clk_remove(struct udevice *dev)
tbl = r8a7796_mstp_table;
tbl_size = ARRAY_SIZE(r8a7796_mstp_table);
break;
case CLK_R8A77970:
tbl = r8a77970_mstp_table;
tbl_size = ARRAY_SIZE(r8a77970_mstp_table);
break;
case CLK_R8A77995:
tbl = r8a77995_mstp_table;
tbl_size = ARRAY_SIZE(r8a77995_mstp_table);
break;
default:
return -EINVAL;
}
@ -1136,6 +1413,8 @@ static int gen3_clk_remove(struct udevice *dev)
static const struct udevice_id gen3_clk_ids[] = {
{ .compatible = "renesas,r8a7795-cpg-mssr", .data = CLK_R8A7795 },
{ .compatible = "renesas,r8a7796-cpg-mssr", .data = CLK_R8A7796 },
{ .compatible = "renesas,r8a77970-cpg-mssr", .data = CLK_R8A77970 },
{ .compatible = "renesas,r8a77995-cpg-mssr", .data = CLK_R8A77995 },
{ }
};

3
drivers/gpio/gpio-rcar.c
View File

@ -174,6 +174,9 @@ static int rcar_gpio_probe(struct udevice *dev)
static const struct udevice_id rcar_gpio_ids[] = {
{ .compatible = "renesas,gpio-r8a7795" },
{ .compatible = "renesas,gpio-r8a7796" },
{ .compatible = "renesas,gpio-r8a77970" },
{ .compatible = "renesas,gpio-r8a77995" },
{ .compatible = "renesas,rcar-gen3-gpio" },
{ /* sentinel */ }
};

2
drivers/mmc/uniphier-sd.c
View File

@ -849,6 +849,8 @@ static int uniphier_sd_probe(struct udevice *dev)
static const struct udevice_id uniphier_sd_match[] = {
{ .compatible = "renesas,sdhi-r8a7795", .data = UNIPHIER_SD_CAP_64BIT },
{ .compatible = "renesas,sdhi-r8a7796", .data = UNIPHIER_SD_CAP_64BIT },
{ .compatible = "renesas,sdhi-r8a77970", .data = UNIPHIER_SD_CAP_64BIT },
{ .compatible = "renesas,sdhi-r8a77995", .data = UNIPHIER_SD_CAP_64BIT },
{ .compatible = "socionext,uniphier-sdhc", .data = 0 },
{ /* sentinel */ }
};

2
drivers/net/ravb.c
View File

@ -652,6 +652,8 @@ int ravb_ofdata_to_platdata(struct udevice *dev)
static const struct udevice_id ravb_ids[] = {
{ .compatible = "renesas,etheravb-r8a7795" },
{ .compatible = "renesas,etheravb-r8a7796" },
{ .compatible = "renesas,etheravb-r8a77970" },
{ .compatible = "renesas,etheravb-r8a77995" },
{ .compatible = "renesas,etheravb-rcar-gen3" },
{ }
};

22
drivers/pinctrl/renesas/Kconfig
View File

@ -28,4 +28,26 @@ config PINCTRL_PFC_R8A7796
the GPIO definitions and pin control functions for each available
multiplex function.
config PINCTRL_PFC_R8A77970
bool "Renesas RCar Gen3 R8A77970 pin control driver"
def_bool y if R8A77970
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RCar Gen3 R8A77970 SoCs.
The driver is controlled by a device tree node which contains both
the GPIO definitions and pin control functions for each available
multiplex function.
config PINCTRL_PFC_R8A77995
bool "Renesas RCar Gen3 R8A77995 pin control driver"
def_bool y if R8A77995
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RCar Gen3 R8A77995 SoCs.
The driver is controlled by a device tree node which contains both
the GPIO definitions and pin control functions for each available
multiplex function.
endif

2
drivers/pinctrl/renesas/Makefile
View File

@ -1,3 +1,5 @@
obj-$(CONFIG_PINCTRL_PFC) += pfc.o
obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o
obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o
obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o

2585
drivers/pinctrl/renesas/pfc-r8a77970.c Normal file
View File

File diff suppressed because it is too large Load Diff

1813
drivers/pinctrl/renesas/pfc-r8a77995.c Normal file
View File

File diff suppressed because it is too large Load Diff

22
drivers/pinctrl/renesas/pfc.c
View File

@ -26,6 +26,8 @@ DECLARE_GLOBAL_DATA_PTR;
enum sh_pfc_model {
SH_PFC_R8A7795 = 0,
SH_PFC_R8A7796,
SH_PFC_R8A77970,
SH_PFC_R8A77995,
};
struct sh_pfc_pin_config {
@ -778,6 +780,14 @@ static int sh_pfc_pinctrl_probe(struct udevice *dev)
if (model == SH_PFC_R8A7796)
priv->pfc.info = &r8a7796_pinmux_info;
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A77970
if (model == SH_PFC_R8A77970)
priv->pfc.info = &r8a77970_pinmux_info;
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A77995
if (model == SH_PFC_R8A77995)
priv->pfc.info = &r8a77995_pinmux_info;
#endif
priv->pmx.pfc = &priv->pfc;
sh_pfc_init_ranges(&priv->pfc);
@ -798,6 +808,18 @@ static const struct udevice_id sh_pfc_pinctrl_ids[] = {
.compatible = "renesas,pfc-r8a7796",
.data = SH_PFC_R8A7796,
},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A77970
{
.compatible = "renesas,pfc-r8a77970",
.data = SH_PFC_R8A77970,
},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A77995
{
.compatible = "renesas,pfc-r8a77995",
.data = SH_PFC_R8A77995,
},
#endif
{ },
};

13
drivers/pinctrl/renesas/sh_pfc.h
View File

@ -247,6 +247,8 @@ int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector);
extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
/* -----------------------------------------------------------------------------
* Helper macros to create pin and port lists
*/
@ -338,6 +340,11 @@ extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
#define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
#define PORT_GP_CFG_6(bank, fn, sfx, cfg) \
PORT_GP_CFG_4(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), PORT_GP_CFG_1(bank, 5, fn, sfx, cfg)
#define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0)
#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
PORT_GP_CFG_4(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
@ -399,6 +406,12 @@ extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
#define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0)
#define PORT_GP_CFG_22(bank, fn, sfx, cfg) \
PORT_GP_CFG_18(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), PORT_GP_CFG_1(bank, 19, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), PORT_GP_CFG_1(bank, 21, fn, sfx, cfg)
#define PORT_GP_22(bank, fn, sfx) PORT_GP_CFG_22(bank, fn, sfx, 0)
#define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
PORT_GP_CFG_21(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \

47
include/configs/draak.h Normal file
View File

@ -0,0 +1,47 @@
/*
* include/configs/draak.h
* This file is Draak board configuration.
*
* Copyright (C) 2015 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DRAAK_H
#define __DRAAK_H
#undef DEBUG
#include "rcar-gen3-common.h"
/* Ethernet RAVB */
#define CONFIG_NET_MULTI
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
/* XTAL_CLK : 33.33MHz */
#define CONFIG_SYS_CLK_FREQ 33333333u
/* Generic Timer Definitions (use in assembler source) */
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_FLASH_CFI_MTD
#define CONFIG_FLASH_SHOW_PROGRESS 45
#define CONFIG_MTD_DEVICE
#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 }
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_SYS_WRITE_SWAPPED_DATA
#define CONFIG_CMD_CACHE
#endif /* __DRAAK_H */

29
include/configs/eagle.h Normal file
View File

@ -0,0 +1,29 @@
/*
* include/configs/eagle.h
* This file is Eagle board configuration.
*
* Copyright (C) 2015 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __EAGLE_H
#define __EAGLE_H
#undef DEBUG
#include "rcar-gen3-common.h"
/* Ethernet RAVB */
#define CONFIG_NET_MULTI
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
/* XTAL_CLK : 33.33MHz */
#define CONFIG_SYS_CLK_FREQ 33333333u
/* Generic Timer Definitions (use in assembler source) */
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
#endif /* __EAGLE_H */

4
include/configs/rcar-gen3-common.h
View File

@ -44,7 +44,11 @@
#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400 }
/* MEMORY */
#if defined(CONFIG_R8A77970)
#define CONFIG_SYS_TEXT_BASE 0x58280000
#else
#define CONFIG_SYS_TEXT_BASE 0x50000000
#endif
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
#define DRAM_RSV_SIZE 0x08000000

48
include/dt-bindings/clock/r8a77970-cpg-mssr.h Normal file
View File

@ -0,0 +1,48 @@
/*
* Copyright (C) 2016 Renesas Electronics Corp.
* Copyright (C) 2017 Cogent Embedded, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a77970 CPG Core Clocks */
#define R8A77970_CLK_Z2 0
#define R8A77970_CLK_ZR 1
#define R8A77970_CLK_ZTR 2
#define R8A77970_CLK_ZTRD2 3
#define R8A77970_CLK_ZT 4
#define R8A77970_CLK_ZX 5
#define R8A77970_CLK_S1D1 6
#define R8A77970_CLK_S1D2 7
#define R8A77970_CLK_S1D4 8
#define R8A77970_CLK_S2D1 9
#define R8A77970_CLK_S2D2 10
#define R8A77970_CLK_S2D4 11
#define R8A77970_CLK_LB 12
#define R8A77970_CLK_CL 13
#define R8A77970_CLK_ZB3 14
#define R8A77970_CLK_ZB3D2 15
#define R8A77970_CLK_DDR 16
#define R8A77970_CLK_CR 17
#define R8A77970_CLK_CRD2 18
#define R8A77970_CLK_SD0H 19
#define R8A77970_CLK_SD0 20
#define R8A77970_CLK_RPC 21
#define R8A77970_CLK_RPCD2 22
#define R8A77970_CLK_MSO 23
#define R8A77970_CLK_CANFD 24
#define R8A77970_CLK_CSI0 25
#define R8A77970_CLK_FRAY 26
#define R8A77970_CLK_CP 27
#define R8A77970_CLK_CPEX 28
#define R8A77970_CLK_R 29
#define R8A77970_CLK_OSC 30
#endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */

57
include/dt-bindings/clock/r8a77995-cpg-mssr.h Normal file
View File

@ -0,0 +1,57 @@
/*
* Copyright (C) 2017 Glider bvba
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a77995 CPG Core Clocks */
#define R8A77995_CLK_Z2 0
#define R8A77995_CLK_ZG 1
#define R8A77995_CLK_ZTR 2
#define R8A77995_CLK_ZT 3
#define R8A77995_CLK_ZX 4
#define R8A77995_CLK_S0D1 5
#define R8A77995_CLK_S1D1 6
#define R8A77995_CLK_S1D2 7
#define R8A77995_CLK_S1D4 8
#define R8A77995_CLK_S2D1 9
#define R8A77995_CLK_S2D2 10
#define R8A77995_CLK_S2D4 11
#define R8A77995_CLK_S3D1 12
#define R8A77995_CLK_S3D2 13
#define R8A77995_CLK_S3D4 14
#define R8A77995_CLK_S1D4C 15
#define R8A77995_CLK_S3D1C 16
#define R8A77995_CLK_S3D2C 17
#define R8A77995_CLK_S3D4C 18
#define R8A77995_CLK_LB 19
#define R8A77995_CLK_CL 20
#define R8A77995_CLK_ZB3 21
#define R8A77995_CLK_ZB3D2 22
#define R8A77995_CLK_CR 23
#define R8A77995_CLK_CRD2 24
#define R8A77995_CLK_SD0H 25
#define R8A77995_CLK_SD0 26
#define R8A77995_CLK_SSP2 27
#define R8A77995_CLK_SSP1 28
#define R8A77995_CLK_RPC 29
#define R8A77995_CLK_RPCD2 30
#define R8A77995_CLK_ZA2 31
#define R8A77995_CLK_ZA8 32
#define R8A77995_CLK_Z2D 33
#define R8A77995_CLK_CANFD 34
#define R8A77995_CLK_MSO 35
#define R8A77995_CLK_R 36
#define R8A77995_CLK_OSC 37
#define R8A77995_CLK_LV0 38
#define R8A77995_CLK_LV1 39
#define R8A77995_CLK_CP 40
#endif /* __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ */

32
include/dt-bindings/power/r8a77970-sysc.h Normal file
View File

@ -0,0 +1,32 @@
/*
* Copyright (C) 2017 Cogent Embedded Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __DT_BINDINGS_POWER_R8A77970_SYSC_H__
#define __DT_BINDINGS_POWER_R8A77970_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A77970_PD_CA53_CPU0 5
#define R8A77970_PD_CA53_CPU1 6
#define R8A77970_PD_CR7 13
#define R8A77970_PD_CA53_SCU 21
#define R8A77970_PD_A2IR0 23
#define R8A77970_PD_A3IR 24
#define R8A77970_PD_A2IR1 27
#define R8A77970_PD_A2IR2 28
#define R8A77970_PD_A2IR3 29
#define R8A77970_PD_A2SC0 30
#define R8A77970_PD_A2SC1 31
/* Always-on power area */
#define R8A77970_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A77970_SYSC_H__ */

23
include/dt-bindings/power/r8a77995-sysc.h Normal file
View File

@ -0,0 +1,23 @@
/*
* Copyright (C) 2017 Glider bvba
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*/
#ifndef __DT_BINDINGS_POWER_R8A77995_SYSC_H__
#define __DT_BINDINGS_POWER_R8A77995_SYSC_H__
/*
* These power domain indices match the numbers of the interrupt bits
* representing the power areas in the various Interrupt Registers
* (e.g. SYSCISR, Interrupt Status Register)
*/
#define R8A77995_PD_CA53_CPU0 5
#define R8A77995_PD_CA53_SCU 21
/* Always-on power area */
#define R8A77995_PD_ALWAYS_ON 32
#endif /* __DT_BINDINGS_POWER_R8A77995_SYSC_H__ */