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ram: rk3399: s/tsel_wr_select_n/tsel_wr_select_dq_n

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Rename tsel_wr_select_n to tsel_wr_select_dq_n based
on the bsp code.

No functionality change.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
This commit is contained in:
Jagan Teki 2019-07-15 23:51:00 +05:30 committed by Kever Yang
parent d4b4bb47c6
commit fa2b015b9c
1 changed files with 6 additions and 6 deletions
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12
drivers/ram/rockchip/sdram_rk3399.c
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@ -161,7 +161,7 @@ static void set_ds_odt(const struct chan_info *chan,
u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
u32 tsel_idle_select_p, tsel_wr_select_p, tsel_rd_select_p;
u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n;
u32 tsel_idle_select_n, tsel_wr_select_n, tsel_rd_select_n;
u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n;
u32 reg_value;
if (params->base.dramtype == LPDDR4) {
@ -171,7 +171,7 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
tsel_rd_select_n = PHY_DRV_ODT_240;
tsel_wr_select_n = PHY_DRV_ODT_40;
tsel_wr_select_dq_n = PHY_DRV_ODT_40;
ca_tsel_wr_select_n = PHY_DRV_ODT_40;
tsel_idle_select_n = PHY_DRV_ODT_240;
} else if (params->base.dramtype == LPDDR3) {
@ -181,7 +181,7 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_idle_select_p = PHY_DRV_ODT_240;
tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
tsel_wr_select_n = PHY_DRV_ODT_34_3;
tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
ca_tsel_wr_select_n = PHY_DRV_ODT_48;
tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
} else {
@ -191,7 +191,7 @@ static void set_ds_odt(const struct chan_info *chan,
tsel_idle_select_p = PHY_DRV_ODT_240;
tsel_rd_select_n = PHY_DRV_ODT_240;
tsel_wr_select_n = PHY_DRV_ODT_34_3;
tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
ca_tsel_wr_select_n = PHY_DRV_ODT_34_3;
tsel_idle_select_n = PHY_DRV_ODT_240;
}
@ -210,7 +210,7 @@ static void set_ds_odt(const struct chan_info *chan,
* for write cycles for DQ/DM
*/
reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
(tsel_wr_select_n << 8) | (tsel_wr_select_p << 12) |
(tsel_wr_select_dq_n << 8) | (tsel_wr_select_p << 12) |
(tsel_idle_select_n << 16) | (tsel_idle_select_p << 20);
clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value);
clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value);
@ -250,7 +250,7 @@ static void set_ds_odt(const struct chan_info *chan,
/* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */
clrsetbits_le32(&denali_phy[924], 0xff,
tsel_wr_select_n | (tsel_wr_select_p << 4));
tsel_wr_select_dq_n | (tsel_wr_select_p << 4));
clrsetbits_le32(&denali_phy[925], 0xff,
tsel_rd_select_n | (tsel_rd_select_p << 4));