Merge branch 'master' of git://git.denx.de/u-boot-sh
- Various rmobile fixes
This commit is contained in:
Tom Rini
commit
f95fdf237d
16
Makefile
16
Makefile
@ -1020,6 +1020,20 @@ quiet_cmd_copy = COPY $@
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ifeq ($(CONFIG_MULTI_DTB_FIT),y)
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ifeq ($(CONFIG_MULTI_DTB_FIT_LZO),y)
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FINAL_DTB_CONTAINER = fit-dtb.blob.lzo
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else ifeq ($(CONFIG_MULTI_DTB_FIT_GZIP),y)
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FINAL_DTB_CONTAINER = fit-dtb.blob.gz
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else
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FINAL_DTB_CONTAINER = fit-dtb.blob
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endif
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fit-dtb.blob.gz: fit-dtb.blob
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@gzip -kf9 $< > $@
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fit-dtb.blob.lzo: fit-dtb.blob
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@lzop -f9 $< > $@
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fit-dtb.blob: dts/dt.dtb FORCE
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$(call if_changed,mkimage)
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@ -1027,7 +1041,7 @@ MKIMAGEFLAGS_fit-dtb.blob = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
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-a 0 -e 0 -E \
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$(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) -d /dev/null
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u-boot-fit-dtb.bin: u-boot-nodtb.bin fit-dtb.blob
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u-boot-fit-dtb.bin: u-boot-nodtb.bin $(FINAL_DTB_CONTAINER)
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$(call if_changed,cat)
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u-boot.bin: u-boot-fit-dtb.bin FORCE
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@ -567,6 +567,7 @@ dtb-$(CONFIG_RCAR_GEN3) += \
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r8a7795-salvator-x-u-boot.dtb \
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r8a7796-m3ulcb-u-boot.dtb \
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r8a7796-salvator-x-u-boot.dtb \
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r8a77965-m3nulcb-u-boot.dtb \
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r8a77965-salvator-x-u-boot.dtb \
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r8a77970-eagle-u-boot.dtb \
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r8a77990-ebisu-u-boot.dtb \
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@ -489,8 +489,6 @@
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};
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&lvds1 {
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status = "okay";
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ports {
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port@1 {
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lvds_connector: endpoint {
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@ -94,9 +94,8 @@
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status = "okay";
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clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>,
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<&cpg CPG_MOD 726>, <&cpg CPG_MOD 725>,
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<&osc1_clk>;
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clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1", "dclkin.0";
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clock-names = "du.0", "du.1", "du.2", "dclkin.0";
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ports {
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port@0 {
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@ -104,11 +103,21 @@
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remote-endpoint = <&adv7511_in>;
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};
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};
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};
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};
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&lvds0 {
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ports {
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port@1 {
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lvds_connector0: endpoint {
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};
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};
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port@2 {
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};
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};
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&lvds1 {
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ports {
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port@1 {
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lvds_connector1: endpoint {
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};
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};
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@ -318,6 +327,10 @@
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interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
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interrupt-controller;
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onkey {
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compatible = "dlg,da9063-onkey";
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};
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rtc {
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compatible = "dlg,da9063-rtc";
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};
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the r8a7790 SoC
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* Device Tree Source for the R-Car H2 (R8A77900) SoC
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*
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* Copyright (C) 2015 Renesas Electronics Corporation
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* Copyright (C) 2013-2014 Renesas Solutions Corp.
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@ -1559,7 +1559,7 @@
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sata0: sata@ee300000 {
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compatible = "renesas,sata-r8a7790",
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"renesas,rcar-gen2-sata";
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reg = <0 0xee300000 0 0x2000>;
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reg = <0 0xee300000 0 0x200000>;
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interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 815>;
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power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
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@ -1570,7 +1570,7 @@
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sata1: sata@ee500000 {
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compatible = "renesas,sata-r8a7790",
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"renesas,rcar-gen2-sata";
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reg = <0 0xee500000 0 0x2000>;
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reg = <0 0xee500000 0 0x200000>;
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interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 814>;
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power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
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@ -479,8 +479,6 @@
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};
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&lvds0 {
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status = "okay";
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ports {
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port@1 {
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lvds_connector: endpoint {
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@ -482,8 +482,6 @@
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};
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&lvds0 {
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status = "okay";
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ports {
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port@1 {
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lvds_connector: endpoint {
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the r8a7791 SoC
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* Device Tree Source for the R-Car M2-W (R8A77910) SoC
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*
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* Copyright (C) 2013-2015 Renesas Electronics Corporation
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* Copyright (C) 2013-2014 Renesas Solutions Corp.
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@ -1543,7 +1543,7 @@
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sata0: sata@ee300000 {
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compatible = "renesas,sata-r8a7791",
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"renesas,rcar-gen2-sata";
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reg = <0 0xee300000 0 0x2000>;
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reg = <0 0xee300000 0 0x200000>;
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interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 815>;
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power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
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@ -1554,7 +1554,7 @@
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sata1: sata@ee500000 {
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compatible = "renesas,sata-r8a7791",
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"renesas,rcar-gen2-sata";
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reg = <0 0xee500000 0 0x2000>;
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reg = <0 0xee500000 0 0x200000>;
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interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 814>;
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power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the r8a7792 SoC
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* Device Tree Source for the R-Car V2H (R8A77920) SoC
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*
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* Copyright (C) 2016 Cogent Embedded Inc.
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*/
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@ -829,7 +829,6 @@
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du: display@feb00000 {
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compatible = "renesas,du-r8a7792";
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reg = <0 0xfeb00000 0 0x40000>;
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reg-names = "du";
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interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 724>,
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@ -596,6 +596,10 @@
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status = "okay";
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};
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&cpu0 {
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cpu0-supply = <&vdd_dvfs>;
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};
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&rwdt {
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timeout-sec = <60>;
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status = "okay";
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@ -725,6 +729,18 @@
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compatible = "dlg,da9063-watchdog";
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};
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};
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vdd_dvfs: regulator@68 {
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compatible = "dlg,da9210";
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reg = <0x68>;
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interrupt-parent = <&irqc0>;
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interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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&i2c4 {
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the r8a7793 SoC
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* Device Tree Source for the R-Car M2-N (R8A77930) SoC
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*
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* Copyright (C) 2014-2015 Renesas Electronics Corporation
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*/
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@ -13,6 +13,30 @@
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clock-frequency = <100000>;
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};
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&pci0 {
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status = "okay";
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pinctrl-0 = <&usb0_pins>;
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pinctrl-names = "default";
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};
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&pci1 {
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status = "okay";
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pinctrl-0 = <&usb1_pins>;
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pinctrl-names = "default";
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};
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&pfc {
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usb0_pins: usb0 {
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groups = "usb0";
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function = "usb0";
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};
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usb1_pins: usb1 {
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groups = "usb1";
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function = "usb1";
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};
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};
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&scif2 {
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u-boot,dm-pre-reloc;
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};
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@ -23,3 +47,7 @@
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spi-rx-bus-width = <1>;
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};
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};
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&usbphy {
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status = "okay";
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};
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@ -405,6 +405,31 @@
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clock-frequency = <400000>;
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};
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&i2c7 {
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status = "okay";
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clock-frequency = <100000>;
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pmic@58 {
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compatible = "dlg,da9063";
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reg = <0x58>;
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interrupt-parent = <&gpio3>;
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interrupts = <31 IRQ_TYPE_LEVEL_LOW>;
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interrupt-controller;
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onkey {
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compatible = "dlg,da9063-onkey";
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};
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rtc {
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compatible = "dlg,da9063-rtc";
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};
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wdt {
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compatible = "dlg,da9063-watchdog";
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};
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};
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};
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&mmcif0 {
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pinctrl-0 = <&mmcif0_pins>;
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pinctrl-names = "default";
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the r8a7794 SoC
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* Device Tree Source for the R-Car E2 (R8A77940) SoC
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*
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* Copyright (C) 2014 Renesas Electronics Corporation
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||||
* Copyright (C) 2014 Ulrich Hecht
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||||
@ -1349,7 +1349,6 @@
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du: display@feb00000 {
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compatible = "renesas,du-r8a7794";
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reg = <0 0xfeb00000 0 0x40000>;
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reg-names = "du";
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||||
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
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||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
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||||
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
|
||||
|
||||
@ -19,19 +19,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
&vcc_sdhi0 {
|
||||
u-boot,off-on-delay-us = <20000>;
|
||||
};
|
||||
|
||||
&sdhi2_pins {
|
||||
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
&sdhi2_pins_uhs {
|
||||
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
|
||||
@ -41,11 +41,10 @@
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 722>,
|
||||
<&cpg CPG_MOD 721>,
|
||||
<&cpg CPG_MOD 727>,
|
||||
<&versaclock5 1>,
|
||||
<&versaclock5 3>,
|
||||
<&versaclock5 4>,
|
||||
<&versaclock5 2>;
|
||||
clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
|
||||
clock-names = "du.0", "du.1", "du.2", "du.3",
|
||||
"dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
|
||||
};
|
||||
|
||||
@ -8,23 +8,6 @@
|
||||
#include "r8a7795-salvator-x.dts"
|
||||
#include "r8a7795-u-boot.dtsi"
|
||||
|
||||
&vcc_sdhi0 {
|
||||
u-boot,off-on-delay-us = <20000>;
|
||||
};
|
||||
|
||||
&vcc_sdhi3 {
|
||||
u-boot,off-on-delay-us = <20000>;
|
||||
};
|
||||
|
||||
&sdhi2_pins {
|
||||
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
&sdhi2_pins_uhs {
|
||||
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
|
||||
@ -40,12 +40,11 @@
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 722>,
|
||||
<&cpg CPG_MOD 721>,
|
||||
<&cpg CPG_MOD 727>,
|
||||
<&versaclock5 1>,
|
||||
<&x21_clk>,
|
||||
<&x22_clk>,
|
||||
<&versaclock5 2>;
|
||||
clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0",
|
||||
clock-names = "du.0", "du.1", "du.2", "du.3",
|
||||
"dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
|
||||
};
|
||||
|
||||
@ -113,6 +112,7 @@
|
||||
ports {
|
||||
/* rsnd_port0 is on salvator-common */
|
||||
rsnd_port1: port@1 {
|
||||
reg = <1>;
|
||||
rsnd_endpoint1: endpoint {
|
||||
remote-endpoint = <&dw_hdmi0_snd_in>;
|
||||
|
||||
@ -124,6 +124,7 @@
|
||||
};
|
||||
};
|
||||
rsnd_port2: port@2 {
|
||||
reg = <2>;
|
||||
rsnd_endpoint2: endpoint {
|
||||
remote-endpoint = <&dw_hdmi1_snd_in>;
|
||||
|
||||
|
||||
@ -11,12 +11,14 @@
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&soc {
|
||||
rpc: rpc@0xee200000 {
|
||||
compatible = "renesas,rpc-r8a7795", "renesas,rpc";
|
||||
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
bank-width = <2>;
|
||||
status = "disabled";
|
||||
/ {
|
||||
soc {
|
||||
rpc: rpc@0xee200000 {
|
||||
compatible = "renesas,rpc-r8a7795", "renesas,rpc";
|
||||
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
bank-width = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the r8a7795 SoC
|
||||
* Device Tree Source for the R-Car H3 (R8A77950) SoC
|
||||
*
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*/
|
||||
@ -116,96 +116,136 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&a57_0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&a57_1>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&a57_2>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&a57_3>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&a53_0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&a53_1>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&a53_2>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&a53_3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
a57_0: cpu@0 {
|
||||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
|
||||
next-level-cache = <&L2_CA57>;
|
||||
enable-method = "psci";
|
||||
clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
|
||||
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
a57_1: cpu@1 {
|
||||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
|
||||
next-level-cache = <&L2_CA57>;
|
||||
enable-method = "psci";
|
||||
clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
|
||||
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
a57_2: cpu@2 {
|
||||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x2>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
|
||||
next-level-cache = <&L2_CA57>;
|
||||
enable-method = "psci";
|
||||
clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
|
||||
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
a57_3: cpu@3 {
|
||||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x3>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
|
||||
next-level-cache = <&L2_CA57>;
|
||||
enable-method = "psci";
|
||||
clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
|
||||
clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
a53_0: cpu@100 {
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x100>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
|
||||
clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
capacity-dmips-mhz = <535>;
|
||||
};
|
||||
|
||||
a53_1: cpu@101 {
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x101>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
|
||||
clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
capacity-dmips-mhz = <535>;
|
||||
};
|
||||
|
||||
a53_2: cpu@102 {
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x102>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
|
||||
clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
capacity-dmips-mhz = <535>;
|
||||
};
|
||||
|
||||
a53_3: cpu@103 {
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x103>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
|
||||
clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
capacity-dmips-mhz = <535>;
|
||||
};
|
||||
|
||||
L2_CA57: cache-controller-0 {
|
||||
@ -455,7 +495,6 @@
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 522>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
intc_ex: interrupt-controller@e61c0000 {
|
||||
@ -525,15 +564,6 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
arm_cc630p: crypto@e6601000 {
|
||||
compatible = "arm,cryptocell-630p-ree";
|
||||
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x0 0xe6601000 0 0x1000>;
|
||||
clocks = <&cpg CPG_MOD 229>;
|
||||
resets = <&cpg 229>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
i2c3: i2c@e66d0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -705,9 +735,9 @@
|
||||
hsusb: usb@e6590000 {
|
||||
compatible = "renesas,usbhs-r8a7795",
|
||||
"renesas,rcar-gen3-usbhs";
|
||||
reg = <0 0xe6590000 0 0x100>;
|
||||
reg = <0 0xe6590000 0 0x200>;
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 704>;
|
||||
clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
|
||||
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
|
||||
<&usb_dmac1 0>, <&usb_dmac1 1>;
|
||||
dma-names = "ch0", "ch1", "ch2", "ch3";
|
||||
@ -715,16 +745,16 @@
|
||||
phys = <&usb2_phy0>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 704>;
|
||||
resets = <&cpg 704>, <&cpg 703>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hsusb3: usb@e659c000 {
|
||||
compatible = "renesas,usbhs-r8a7795",
|
||||
"renesas,rcar-gen3-usbhs";
|
||||
reg = <0 0xe659c000 0 0x100>;
|
||||
reg = <0 0xe659c000 0 0x200>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 705>;
|
||||
clocks = <&cpg CPG_MOD 705>, <&cpg CPG_MOD 700>;
|
||||
dmas = <&usb_dmac2 0>, <&usb_dmac2 1>,
|
||||
<&usb_dmac3 0>, <&usb_dmac3 1>;
|
||||
dma-names = "ch0", "ch1", "ch2", "ch3";
|
||||
@ -732,7 +762,7 @@
|
||||
phys = <&usb2_phy3>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 705>;
|
||||
resets = <&cpg 705>, <&cpg 700>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -805,6 +835,15 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
arm_cc630p: crypto@e6601000 {
|
||||
compatible = "arm,cryptocell-630p-ree";
|
||||
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x0 0xe6601000 0 0x1000>;
|
||||
clocks = <&cpg CPG_MOD 229>;
|
||||
resets = <&cpg 229>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
};
|
||||
|
||||
dmac0: dma-controller@e6700000 {
|
||||
compatible = "renesas,dmac-r8a7795",
|
||||
"renesas,rcar-dmac";
|
||||
@ -1425,11 +1464,11 @@
|
||||
|
||||
vin0csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint= <&csi20vin0>;
|
||||
remote-endpoint = <&csi20vin0>;
|
||||
};
|
||||
vin0csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin0>;
|
||||
remote-endpoint = <&csi40vin0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1457,11 +1496,11 @@
|
||||
|
||||
vin1csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint= <&csi20vin1>;
|
||||
remote-endpoint = <&csi20vin1>;
|
||||
};
|
||||
vin1csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin1>;
|
||||
remote-endpoint = <&csi40vin1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1489,11 +1528,11 @@
|
||||
|
||||
vin2csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint= <&csi20vin2>;
|
||||
remote-endpoint = <&csi20vin2>;
|
||||
};
|
||||
vin2csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin2>;
|
||||
remote-endpoint = <&csi40vin2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1521,11 +1560,11 @@
|
||||
|
||||
vin3csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint= <&csi20vin3>;
|
||||
remote-endpoint = <&csi20vin3>;
|
||||
};
|
||||
vin3csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin3>;
|
||||
remote-endpoint = <&csi40vin3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1553,11 +1592,11 @@
|
||||
|
||||
vin4csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint= <&csi20vin4>;
|
||||
remote-endpoint = <&csi20vin4>;
|
||||
};
|
||||
vin4csi41: endpoint@3 {
|
||||
reg = <3>;
|
||||
remote-endpoint= <&csi41vin4>;
|
||||
remote-endpoint = <&csi41vin4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1585,11 +1624,11 @@
|
||||
|
||||
vin5csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint= <&csi20vin5>;
|
||||
remote-endpoint = <&csi20vin5>;
|
||||
};
|
||||
vin5csi41: endpoint@3 {
|
||||
reg = <3>;
|
||||
remote-endpoint= <&csi41vin5>;
|
||||
remote-endpoint = <&csi41vin5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1617,11 +1656,11 @@
|
||||
|
||||
vin6csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint= <&csi20vin6>;
|
||||
remote-endpoint = <&csi20vin6>;
|
||||
};
|
||||
vin6csi41: endpoint@3 {
|
||||
reg = <3>;
|
||||
remote-endpoint= <&csi41vin6>;
|
||||
remote-endpoint = <&csi41vin6>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1649,11 +1688,11 @@
|
||||
|
||||
vin7csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint= <&csi20vin7>;
|
||||
remote-endpoint = <&csi20vin7>;
|
||||
};
|
||||
vin7csi41: endpoint@3 {
|
||||
reg = <3>;
|
||||
remote-endpoint= <&csi41vin7>;
|
||||
remote-endpoint = <&csi41vin7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1921,70 +1960,267 @@
|
||||
};
|
||||
};
|
||||
|
||||
rcar_sound,ssi {
|
||||
ssi0: ssi-0 {
|
||||
interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
rcar_sound,ssiu {
|
||||
ssiu00: ssiu-0 {
|
||||
dmas = <&audma0 0x15>, <&audma1 0x16>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssi1: ssi-1 {
|
||||
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
ssiu01: ssiu-1 {
|
||||
dmas = <&audma0 0x35>, <&audma1 0x36>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssi2: ssi-2 {
|
||||
interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
ssiu02: ssiu-2 {
|
||||
dmas = <&audma0 0x37>, <&audma1 0x38>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssi3: ssi-3 {
|
||||
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
ssiu03: ssiu-3 {
|
||||
dmas = <&audma0 0x47>, <&audma1 0x48>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssi4: ssi-4 {
|
||||
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
ssiu04: ssiu-4 {
|
||||
dmas = <&audma0 0x3F>, <&audma1 0x40>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssi5: ssi-5 {
|
||||
interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
ssiu05: ssiu-5 {
|
||||
dmas = <&audma0 0x43>, <&audma1 0x44>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssi6: ssi-6 {
|
||||
interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
ssiu06: ssiu-6 {
|
||||
dmas = <&audma0 0x4F>, <&audma1 0x50>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssi7: ssi-7 {
|
||||
interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
ssiu07: ssiu-7 {
|
||||
dmas = <&audma0 0x53>, <&audma1 0x54>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssi8: ssi-8 {
|
||||
interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
ssiu10: ssiu-8 {
|
||||
dmas = <&audma0 0x49>, <&audma1 0x4a>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssi9: ssi-9 {
|
||||
interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
ssiu11: ssiu-9 {
|
||||
dmas = <&audma0 0x4B>, <&audma1 0x4C>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu12: ssiu-10 {
|
||||
dmas = <&audma0 0x57>, <&audma1 0x58>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu13: ssiu-11 {
|
||||
dmas = <&audma0 0x59>, <&audma1 0x5A>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu14: ssiu-12 {
|
||||
dmas = <&audma0 0x5F>, <&audma1 0x60>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu15: ssiu-13 {
|
||||
dmas = <&audma0 0xC3>, <&audma1 0xC4>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu16: ssiu-14 {
|
||||
dmas = <&audma0 0xC7>, <&audma1 0xC8>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu17: ssiu-15 {
|
||||
dmas = <&audma0 0xCB>, <&audma1 0xCC>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu20: ssiu-16 {
|
||||
dmas = <&audma0 0x63>, <&audma1 0x64>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu21: ssiu-17 {
|
||||
dmas = <&audma0 0x67>, <&audma1 0x68>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu22: ssiu-18 {
|
||||
dmas = <&audma0 0x6B>, <&audma1 0x6C>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu23: ssiu-19 {
|
||||
dmas = <&audma0 0x6D>, <&audma1 0x6E>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu24: ssiu-20 {
|
||||
dmas = <&audma0 0xCF>, <&audma1 0xCE>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu25: ssiu-21 {
|
||||
dmas = <&audma0 0xEB>, <&audma1 0xEC>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu26: ssiu-22 {
|
||||
dmas = <&audma0 0xED>, <&audma1 0xEE>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu27: ssiu-23 {
|
||||
dmas = <&audma0 0xEF>, <&audma1 0xF0>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu30: ssiu-24 {
|
||||
dmas = <&audma0 0x6f>, <&audma1 0x70>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu31: ssiu-25 {
|
||||
dmas = <&audma0 0x21>, <&audma1 0x22>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu32: ssiu-26 {
|
||||
dmas = <&audma0 0x23>, <&audma1 0x24>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu33: ssiu-27 {
|
||||
dmas = <&audma0 0x25>, <&audma1 0x26>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu34: ssiu-28 {
|
||||
dmas = <&audma0 0x27>, <&audma1 0x28>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu35: ssiu-29 {
|
||||
dmas = <&audma0 0x29>, <&audma1 0x2A>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu36: ssiu-30 {
|
||||
dmas = <&audma0 0x2B>, <&audma1 0x2C>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu37: ssiu-31 {
|
||||
dmas = <&audma0 0x2D>, <&audma1 0x2E>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu40: ssiu-32 {
|
||||
dmas = <&audma0 0x71>, <&audma1 0x72>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu41: ssiu-33 {
|
||||
dmas = <&audma0 0x17>, <&audma1 0x18>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu42: ssiu-34 {
|
||||
dmas = <&audma0 0x19>, <&audma1 0x1A>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu43: ssiu-35 {
|
||||
dmas = <&audma0 0x1B>, <&audma1 0x1C>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu44: ssiu-36 {
|
||||
dmas = <&audma0 0x1D>, <&audma1 0x1E>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu45: ssiu-37 {
|
||||
dmas = <&audma0 0x1F>, <&audma1 0x20>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu46: ssiu-38 {
|
||||
dmas = <&audma0 0x31>, <&audma1 0x32>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu47: ssiu-39 {
|
||||
dmas = <&audma0 0x33>, <&audma1 0x34>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu50: ssiu-40 {
|
||||
dmas = <&audma0 0x73>, <&audma1 0x74>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu60: ssiu-41 {
|
||||
dmas = <&audma0 0x75>, <&audma1 0x76>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu70: ssiu-42 {
|
||||
dmas = <&audma0 0x79>, <&audma1 0x7a>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu80: ssiu-43 {
|
||||
dmas = <&audma0 0x7b>, <&audma1 0x7c>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu90: ssiu-44 {
|
||||
dmas = <&audma0 0x7d>, <&audma1 0x7e>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu91: ssiu-45 {
|
||||
dmas = <&audma0 0x7F>, <&audma1 0x80>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu92: ssiu-46 {
|
||||
dmas = <&audma0 0x81>, <&audma1 0x82>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu93: ssiu-47 {
|
||||
dmas = <&audma0 0x83>, <&audma1 0x84>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu94: ssiu-48 {
|
||||
dmas = <&audma0 0xA3>, <&audma1 0xA4>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu95: ssiu-49 {
|
||||
dmas = <&audma0 0xA5>, <&audma1 0xA6>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu96: ssiu-50 {
|
||||
dmas = <&audma0 0xA7>, <&audma1 0xA8>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu97: ssiu-51 {
|
||||
dmas = <&audma0 0xA9>, <&audma1 0xAA>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
rcar_sound,ssi {
|
||||
ssi0: ssi-0 {
|
||||
interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x01>, <&audma1 0x02>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
ssi1: ssi-1 {
|
||||
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x03>, <&audma1 0x04>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
ssi2: ssi-2 {
|
||||
interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x05>, <&audma1 0x06>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssi3: ssi-3 {
|
||||
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x07>, <&audma1 0x08>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssi4: ssi-4 {
|
||||
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x09>, <&audma1 0x0a>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssi5: ssi-5 {
|
||||
interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x0b>, <&audma1 0x0c>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssi6: ssi-6 {
|
||||
interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x0d>, <&audma1 0x0e>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssi7: ssi-7 {
|
||||
interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x0f>, <&audma1 0x10>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssi8: ssi-8 {
|
||||
interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x11>, <&audma1 0x12>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssi9: ssi-9 {
|
||||
interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x13>, <&audma1 0x14>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -2098,11 +2334,11 @@
|
||||
compatible = "generic-ohci";
|
||||
reg = <0 0xee080000 0 0x100>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 703>;
|
||||
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
|
||||
phys = <&usb2_phy0>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 703>;
|
||||
resets = <&cpg 703>, <&cpg 704>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -2134,11 +2370,11 @@
|
||||
compatible = "generic-ohci";
|
||||
reg = <0 0xee0e0000 0 0x100>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 700>;
|
||||
clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>;
|
||||
phys = <&usb2_phy3>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 700>;
|
||||
resets = <&cpg 700>, <&cpg 705>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -2146,12 +2382,12 @@
|
||||
compatible = "generic-ehci";
|
||||
reg = <0 0xee080100 0 0x100>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 703>;
|
||||
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
|
||||
phys = <&usb2_phy0>;
|
||||
phy-names = "usb";
|
||||
companion = <&ohci0>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 703>;
|
||||
resets = <&cpg 703>, <&cpg 704>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -2185,12 +2421,12 @@
|
||||
compatible = "generic-ehci";
|
||||
reg = <0 0xee0e0100 0 0x100>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 700>;
|
||||
clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>;
|
||||
phys = <&usb2_phy3>;
|
||||
phy-names = "usb";
|
||||
companion = <&ohci3>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 700>;
|
||||
resets = <&cpg 700>, <&cpg 705>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -2199,9 +2435,9 @@
|
||||
"renesas,rcar-gen3-usb2-phy";
|
||||
reg = <0 0xee080200 0 0x700>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 703>;
|
||||
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 703>;
|
||||
resets = <&cpg 703>, <&cpg 704>;
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -2233,9 +2469,9 @@
|
||||
"renesas,rcar-gen3-usb2-phy";
|
||||
reg = <0 0xee0e0200 0 0x700>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 700>;
|
||||
clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 700>;
|
||||
resets = <&cpg 700>, <&cpg 705>;
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -2782,9 +3018,7 @@
|
||||
|
||||
du: display@feb00000 {
|
||||
compatible = "renesas,du-r8a7795";
|
||||
reg = <0 0xfeb00000 0 0x80000>,
|
||||
<0 0xfeb90000 0 0x14>;
|
||||
reg-names = "du", "lvds.0";
|
||||
reg = <0 0xfeb00000 0 0x80000>;
|
||||
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
|
||||
@ -2792,9 +3026,8 @@
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 722>,
|
||||
<&cpg CPG_MOD 721>,
|
||||
<&cpg CPG_MOD 727>;
|
||||
clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
|
||||
<&cpg CPG_MOD 721>;
|
||||
clock-names = "du.0", "du.1", "du.2", "du.3";
|
||||
vsps = <&vspd0 0 &vspd1 0 &vspd2 0 &vspd0 1>;
|
||||
status = "disabled";
|
||||
|
||||
@ -2822,6 +3055,33 @@
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
du_out_lvds0: endpoint {
|
||||
remote-endpoint = <&lvds0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lvds0: lvds@feb90000 {
|
||||
compatible = "renesas,r8a7795-lvds";
|
||||
reg = <0 0xfeb90000 0 0x14>;
|
||||
clocks = <&cpg CPG_MOD 727>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 727>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
lvds0_in: endpoint {
|
||||
remote-endpoint = <&du_out_lvds0>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
lvds0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -2855,7 +3115,10 @@
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&sensor1_passive>;
|
||||
cooling-device = <&a57_0 4 4>;
|
||||
cooling-device = <&a57_0 4 4>,
|
||||
<&a57_1 4 4>,
|
||||
<&a57_2 4 4>,
|
||||
<&a57_3 4 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -2881,7 +3144,10 @@
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&sensor2_passive>;
|
||||
cooling-device = <&a57_0 4 4>;
|
||||
cooling-device = <&a57_0 4 4>,
|
||||
<&a57_1 4 4>,
|
||||
<&a57_2 4 4>,
|
||||
<&a57_3 4 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -2907,7 +3173,10 @@
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&sensor3_passive>;
|
||||
cooling-device = <&a57_0 4 4>;
|
||||
cooling-device = <&a57_0 4 4>,
|
||||
<&a57_1 4 4>,
|
||||
<&a57_2 4 4>,
|
||||
<&a57_3 4 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -19,19 +19,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
&vcc_sdhi0 {
|
||||
u-boot,off-on-delay-us = <20000>;
|
||||
};
|
||||
|
||||
&sdhi2_pins {
|
||||
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
&sdhi2_pins_uhs {
|
||||
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
|
||||
@ -30,10 +30,9 @@
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 722>,
|
||||
<&cpg CPG_MOD 727>,
|
||||
<&versaclock5 1>,
|
||||
<&versaclock5 3>,
|
||||
<&versaclock5 2>;
|
||||
clock-names = "du.0", "du.1", "du.2", "lvds.0",
|
||||
clock-names = "du.0", "du.1", "du.2",
|
||||
"dclkin.0", "dclkin.1", "dclkin.2";
|
||||
};
|
||||
|
||||
@ -8,23 +8,6 @@
|
||||
#include "r8a7796-salvator-x.dts"
|
||||
#include "r8a7796-u-boot.dtsi"
|
||||
|
||||
&vcc_sdhi0 {
|
||||
u-boot,off-on-delay-us = <20000>;
|
||||
};
|
||||
|
||||
&vcc_sdhi3 {
|
||||
u-boot,off-on-delay-us = <20000>;
|
||||
};
|
||||
|
||||
&sdhi2_pins {
|
||||
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
&sdhi2_pins_uhs {
|
||||
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
|
||||
@ -29,11 +29,10 @@
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 722>,
|
||||
<&cpg CPG_MOD 727>,
|
||||
<&versaclock5 1>,
|
||||
<&x21_clk>,
|
||||
<&versaclock5 2>;
|
||||
clock-names = "du.0", "du.1", "du.2", "lvds.0",
|
||||
clock-names = "du.0", "du.1", "du.2",
|
||||
"dclkin.0", "dclkin.1", "dclkin.2";
|
||||
};
|
||||
|
||||
|
||||
@ -11,12 +11,14 @@
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&soc {
|
||||
rpc: rpc@0xee200000 {
|
||||
compatible = "renesas,rpc-r8a7796", "renesas,rpc";
|
||||
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
bank-width = <2>;
|
||||
status = "disabled";
|
||||
/ {
|
||||
soc {
|
||||
rpc: rpc@0xee200000 {
|
||||
compatible = "renesas,rpc-r8a7796", "renesas,rpc";
|
||||
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
bank-width = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the r8a7796 SoC
|
||||
* Device Tree Source for the R-Car M3-W (R8A77960) SoC
|
||||
*
|
||||
* Copyright (C) 2016-2017 Renesas Electronics Corp.
|
||||
*/
|
||||
@ -127,72 +127,104 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&a57_0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&a57_1>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&a53_0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&a53_1>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&a53_2>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&a53_3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
a57_0: cpu@0 {
|
||||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
|
||||
next-level-cache = <&L2_CA57>;
|
||||
enable-method = "psci";
|
||||
clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
|
||||
clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
a57_1: cpu@1 {
|
||||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
|
||||
next-level-cache = <&L2_CA57>;
|
||||
enable-method = "psci";
|
||||
clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
|
||||
clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
a53_0: cpu@100 {
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x100>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
|
||||
clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
capacity-dmips-mhz = <535>;
|
||||
};
|
||||
|
||||
a53_1: cpu@101 {
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x101>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
|
||||
clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
capacity-dmips-mhz = <535>;
|
||||
};
|
||||
|
||||
a53_2: cpu@102 {
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x102>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
|
||||
clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
capacity-dmips-mhz = <535>;
|
||||
};
|
||||
|
||||
a53_3: cpu@103 {
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x103>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
|
||||
next-level-cache = <&L2_CA53>;
|
||||
enable-method = "psci";
|
||||
clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
|
||||
clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
capacity-dmips-mhz = <535>;
|
||||
};
|
||||
|
||||
L2_CA57: cache-controller-0 {
|
||||
@ -259,7 +291,7 @@
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
@ -401,6 +433,76 @@
|
||||
reg = <0 0xe6060000 0 0x50c>;
|
||||
};
|
||||
|
||||
cmt0: timer@e60f0000 {
|
||||
compatible = "renesas,r8a7796-cmt0",
|
||||
"renesas,rcar-gen3-cmt0";
|
||||
reg = <0 0xe60f0000 0 0x1004>;
|
||||
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 303>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 303>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cmt1: timer@e6130000 {
|
||||
compatible = "renesas,r8a7796-cmt1",
|
||||
"renesas,rcar-gen3-cmt1";
|
||||
reg = <0 0xe6130000 0 0x1004>;
|
||||
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 302>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 302>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cmt2: timer@e6140000 {
|
||||
compatible = "renesas,r8a7796-cmt1",
|
||||
"renesas,rcar-gen3-cmt1";
|
||||
reg = <0 0xe6140000 0 0x1004>;
|
||||
interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 301>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 301>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cmt3: timer@e6148000 {
|
||||
compatible = "renesas,r8a7796-cmt1",
|
||||
"renesas,rcar-gen3-cmt1";
|
||||
reg = <0 0xe6148000 0 0x1004>;
|
||||
interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 300>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 300>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cpg: clock-controller@e6150000 {
|
||||
compatible = "renesas,r8a7796-cpg-mssr";
|
||||
reg = <0 0xe6150000 0 0x1000>;
|
||||
@ -434,7 +536,6 @@
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 522>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
intc_ex: interrupt-controller@e61c0000 {
|
||||
@ -675,9 +776,9 @@
|
||||
hsusb: usb@e6590000 {
|
||||
compatible = "renesas,usbhs-r8a7796",
|
||||
"renesas,rcar-gen3-usbhs";
|
||||
reg = <0 0xe6590000 0 0x100>;
|
||||
reg = <0 0xe6590000 0 0x200>;
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 704>;
|
||||
clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
|
||||
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
|
||||
<&usb_dmac1 0>, <&usb_dmac1 1>;
|
||||
dma-names = "ch0", "ch1", "ch2", "ch3";
|
||||
@ -685,7 +786,7 @@
|
||||
phys = <&usb2_phy0>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 704>;
|
||||
resets = <&cpg 704>, <&cpg 703>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1161,6 +1262,9 @@
|
||||
<&cpg CPG_CORE R8A7796_CLK_S3D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x13>, <&dmac1 0x12>,
|
||||
<&dmac2 0x13>, <&dmac2 0x12>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 310>;
|
||||
status = "disabled";
|
||||
@ -1299,11 +1403,11 @@
|
||||
|
||||
vin0csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint= <&csi20vin0>;
|
||||
remote-endpoint = <&csi20vin0>;
|
||||
};
|
||||
vin0csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin0>;
|
||||
remote-endpoint = <&csi40vin0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1331,11 +1435,11 @@
|
||||
|
||||
vin1csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint= <&csi20vin1>;
|
||||
remote-endpoint = <&csi20vin1>;
|
||||
};
|
||||
vin1csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin1>;
|
||||
remote-endpoint = <&csi40vin1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1363,11 +1467,11 @@
|
||||
|
||||
vin2csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint= <&csi20vin2>;
|
||||
remote-endpoint = <&csi20vin2>;
|
||||
};
|
||||
vin2csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin2>;
|
||||
remote-endpoint = <&csi40vin2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1395,11 +1499,11 @@
|
||||
|
||||
vin3csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint= <&csi20vin3>;
|
||||
remote-endpoint = <&csi20vin3>;
|
||||
};
|
||||
vin3csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin3>;
|
||||
remote-endpoint = <&csi40vin3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1427,11 +1531,11 @@
|
||||
|
||||
vin4csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint= <&csi20vin4>;
|
||||
remote-endpoint = <&csi20vin4>;
|
||||
};
|
||||
vin4csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin4>;
|
||||
remote-endpoint = <&csi40vin4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1459,11 +1563,11 @@
|
||||
|
||||
vin5csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint= <&csi20vin5>;
|
||||
remote-endpoint = <&csi20vin5>;
|
||||
};
|
||||
vin5csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin5>;
|
||||
remote-endpoint = <&csi40vin5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1491,11 +1595,11 @@
|
||||
|
||||
vin6csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint= <&csi20vin6>;
|
||||
remote-endpoint = <&csi20vin6>;
|
||||
};
|
||||
vin6csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin6>;
|
||||
remote-endpoint = <&csi40vin6>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1523,11 +1627,11 @@
|
||||
|
||||
vin7csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint= <&csi20vin7>;
|
||||
remote-endpoint = <&csi20vin7>;
|
||||
};
|
||||
vin7csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin7>;
|
||||
remote-endpoint = <&csi40vin7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1795,56 +1899,267 @@
|
||||
};
|
||||
};
|
||||
|
||||
rcar_sound,ssiu {
|
||||
ssiu00: ssiu-0 {
|
||||
dmas = <&audma0 0x15>, <&audma1 0x16>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu01: ssiu-1 {
|
||||
dmas = <&audma0 0x35>, <&audma1 0x36>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu02: ssiu-2 {
|
||||
dmas = <&audma0 0x37>, <&audma1 0x38>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu03: ssiu-3 {
|
||||
dmas = <&audma0 0x47>, <&audma1 0x48>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu04: ssiu-4 {
|
||||
dmas = <&audma0 0x3F>, <&audma1 0x40>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu05: ssiu-5 {
|
||||
dmas = <&audma0 0x43>, <&audma1 0x44>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu06: ssiu-6 {
|
||||
dmas = <&audma0 0x4F>, <&audma1 0x50>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu07: ssiu-7 {
|
||||
dmas = <&audma0 0x53>, <&audma1 0x54>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu10: ssiu-8 {
|
||||
dmas = <&audma0 0x49>, <&audma1 0x4a>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu11: ssiu-9 {
|
||||
dmas = <&audma0 0x4B>, <&audma1 0x4C>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu12: ssiu-10 {
|
||||
dmas = <&audma0 0x57>, <&audma1 0x58>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu13: ssiu-11 {
|
||||
dmas = <&audma0 0x59>, <&audma1 0x5A>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu14: ssiu-12 {
|
||||
dmas = <&audma0 0x5F>, <&audma1 0x60>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu15: ssiu-13 {
|
||||
dmas = <&audma0 0xC3>, <&audma1 0xC4>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu16: ssiu-14 {
|
||||
dmas = <&audma0 0xC7>, <&audma1 0xC8>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu17: ssiu-15 {
|
||||
dmas = <&audma0 0xCB>, <&audma1 0xCC>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu20: ssiu-16 {
|
||||
dmas = <&audma0 0x63>, <&audma1 0x64>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu21: ssiu-17 {
|
||||
dmas = <&audma0 0x67>, <&audma1 0x68>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu22: ssiu-18 {
|
||||
dmas = <&audma0 0x6B>, <&audma1 0x6C>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu23: ssiu-19 {
|
||||
dmas = <&audma0 0x6D>, <&audma1 0x6E>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu24: ssiu-20 {
|
||||
dmas = <&audma0 0xCF>, <&audma1 0xCE>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu25: ssiu-21 {
|
||||
dmas = <&audma0 0xEB>, <&audma1 0xEC>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu26: ssiu-22 {
|
||||
dmas = <&audma0 0xED>, <&audma1 0xEE>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu27: ssiu-23 {
|
||||
dmas = <&audma0 0xEF>, <&audma1 0xF0>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu30: ssiu-24 {
|
||||
dmas = <&audma0 0x6f>, <&audma1 0x70>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu31: ssiu-25 {
|
||||
dmas = <&audma0 0x21>, <&audma1 0x22>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu32: ssiu-26 {
|
||||
dmas = <&audma0 0x23>, <&audma1 0x24>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu33: ssiu-27 {
|
||||
dmas = <&audma0 0x25>, <&audma1 0x26>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu34: ssiu-28 {
|
||||
dmas = <&audma0 0x27>, <&audma1 0x28>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu35: ssiu-29 {
|
||||
dmas = <&audma0 0x29>, <&audma1 0x2A>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu36: ssiu-30 {
|
||||
dmas = <&audma0 0x2B>, <&audma1 0x2C>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu37: ssiu-31 {
|
||||
dmas = <&audma0 0x2D>, <&audma1 0x2E>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu40: ssiu-32 {
|
||||
dmas = <&audma0 0x71>, <&audma1 0x72>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu41: ssiu-33 {
|
||||
dmas = <&audma0 0x17>, <&audma1 0x18>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu42: ssiu-34 {
|
||||
dmas = <&audma0 0x19>, <&audma1 0x1A>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu43: ssiu-35 {
|
||||
dmas = <&audma0 0x1B>, <&audma1 0x1C>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu44: ssiu-36 {
|
||||
dmas = <&audma0 0x1D>, <&audma1 0x1E>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu45: ssiu-37 {
|
||||
dmas = <&audma0 0x1F>, <&audma1 0x20>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu46: ssiu-38 {
|
||||
dmas = <&audma0 0x31>, <&audma1 0x32>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu47: ssiu-39 {
|
||||
dmas = <&audma0 0x33>, <&audma1 0x34>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu50: ssiu-40 {
|
||||
dmas = <&audma0 0x73>, <&audma1 0x74>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu60: ssiu-41 {
|
||||
dmas = <&audma0 0x75>, <&audma1 0x76>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu70: ssiu-42 {
|
||||
dmas = <&audma0 0x79>, <&audma1 0x7a>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu80: ssiu-43 {
|
||||
dmas = <&audma0 0x7b>, <&audma1 0x7c>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu90: ssiu-44 {
|
||||
dmas = <&audma0 0x7d>, <&audma1 0x7e>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu91: ssiu-45 {
|
||||
dmas = <&audma0 0x7F>, <&audma1 0x80>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu92: ssiu-46 {
|
||||
dmas = <&audma0 0x81>, <&audma1 0x82>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu93: ssiu-47 {
|
||||
dmas = <&audma0 0x83>, <&audma1 0x84>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu94: ssiu-48 {
|
||||
dmas = <&audma0 0xA3>, <&audma1 0xA4>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu95: ssiu-49 {
|
||||
dmas = <&audma0 0xA5>, <&audma1 0xA6>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu96: ssiu-50 {
|
||||
dmas = <&audma0 0xA7>, <&audma1 0xA8>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssiu97: ssiu-51 {
|
||||
dmas = <&audma0 0xA9>, <&audma1 0xAA>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
};
|
||||
|
||||
rcar_sound,ssi {
|
||||
ssi0: ssi-0 {
|
||||
interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
dmas = <&audma0 0x01>, <&audma1 0x02>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssi1: ssi-1 {
|
||||
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
dmas = <&audma0 0x03>, <&audma1 0x04>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssi2: ssi-2 {
|
||||
interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
dmas = <&audma0 0x05>, <&audma1 0x06>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssi3: ssi-3 {
|
||||
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
dmas = <&audma0 0x07>, <&audma1 0x08>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssi4: ssi-4 {
|
||||
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
dmas = <&audma0 0x09>, <&audma1 0x0a>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssi5: ssi-5 {
|
||||
interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
dmas = <&audma0 0x0b>, <&audma1 0x0c>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssi6: ssi-6 {
|
||||
interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
dmas = <&audma0 0x0d>, <&audma1 0x0e>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssi7: ssi-7 {
|
||||
interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
dmas = <&audma0 0x0f>, <&audma1 0x10>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssi8: ssi-8 {
|
||||
interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
dmas = <&audma0 0x11>, <&audma1 0x12>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
ssi9: ssi-9 {
|
||||
interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
dmas = <&audma0 0x13>, <&audma1 0x14>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
};
|
||||
|
||||
@ -1970,11 +2285,11 @@
|
||||
compatible = "generic-ohci";
|
||||
reg = <0 0xee080000 0 0x100>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 703>;
|
||||
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
|
||||
phys = <&usb2_phy0>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 703>;
|
||||
resets = <&cpg 703>, <&cpg 704>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1994,12 +2309,12 @@
|
||||
compatible = "generic-ehci";
|
||||
reg = <0 0xee080100 0 0x100>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 703>;
|
||||
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
|
||||
phys = <&usb2_phy0>;
|
||||
phy-names = "usb";
|
||||
companion= <&ohci0>;
|
||||
companion = <&ohci0>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 703>;
|
||||
resets = <&cpg 703>, <&cpg 704>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -2010,7 +2325,7 @@
|
||||
clocks = <&cpg CPG_MOD 702>;
|
||||
phys = <&usb2_phy1>;
|
||||
phy-names = "usb";
|
||||
companion= <&ohci1>;
|
||||
companion = <&ohci1>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 702>;
|
||||
status = "disabled";
|
||||
@ -2021,9 +2336,9 @@
|
||||
"renesas,rcar-gen3-usb2-phy";
|
||||
reg = <0 0xee080200 0 0x700>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 703>;
|
||||
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 703>;
|
||||
resets = <&cpg 703>, <&cpg 704>;
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -2437,17 +2752,14 @@
|
||||
|
||||
du: display@feb00000 {
|
||||
compatible = "renesas,du-r8a7796";
|
||||
reg = <0 0xfeb00000 0 0x70000>,
|
||||
<0 0xfeb90000 0 0x14>;
|
||||
reg-names = "du", "lvds.0";
|
||||
reg = <0 0xfeb00000 0 0x70000>;
|
||||
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 722>,
|
||||
<&cpg CPG_MOD 727>;
|
||||
clock-names = "du.0", "du.1", "du.2", "lvds.0";
|
||||
<&cpg CPG_MOD 722>;
|
||||
clock-names = "du.0", "du.1", "du.2";
|
||||
status = "disabled";
|
||||
|
||||
vsps = <&vspd0 &vspd1 &vspd2>;
|
||||
@ -2470,6 +2782,33 @@
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
du_out_lvds0: endpoint {
|
||||
remote-endpoint = <&lvds0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lvds0: lvds@feb90000 {
|
||||
compatible = "renesas,r8a7796-lvds";
|
||||
reg = <0 0xfeb90000 0 0x14>;
|
||||
clocks = <&cpg CPG_MOD 727>;
|
||||
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 727>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
lvds0_in: endpoint {
|
||||
remote-endpoint = <&du_out_lvds0>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
lvds0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -2503,7 +2842,7 @@
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&sensor1_passive>;
|
||||
cooling-device = <&a57_0 5 5>;
|
||||
cooling-device = <&a57_0 5 5>, <&a57_1 5 5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -2529,7 +2868,7 @@
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&sensor2_passive>;
|
||||
cooling-device = <&a57_0 5 5>;
|
||||
cooling-device = <&a57_0 5 5>, <&a57_1 5 5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -2555,7 +2894,7 @@
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&sensor3_passive>;
|
||||
cooling-device = <&a57_0 5 5>;
|
||||
cooling-device = <&a57_0 5 5>, <&a57_1 5 5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
34
arch/arm/dts/r8a77965-m3nulcb-u-boot.dts
Normal file
34
arch/arm/dts/r8a77965-m3nulcb-u-boot.dts
Normal file
@ -0,0 +1,34 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source extras for U-Boot for the ULCB board
|
||||
*
|
||||
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
*/
|
||||
|
||||
#include "r8a77965-m3nulcb.dts"
|
||||
#include "r8a77965-u-boot.dtsi"
|
||||
|
||||
/ {
|
||||
cpld {
|
||||
compatible = "renesas,ulcb-cpld";
|
||||
status = "okay";
|
||||
gpio-sck = <&gpio6 8 0>;
|
||||
gpio-mosi = <&gpio6 7 0>;
|
||||
gpio-miso = <&gpio6 10 0>;
|
||||
gpio-sstbz = <&gpio2 3 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr104;
|
||||
max-frequency = <208000000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi2 {
|
||||
mmc-hs400-1_8v;
|
||||
max-frequency = <200000000>;
|
||||
status = "okay";
|
||||
};
|
||||
33
arch/arm/dts/r8a77965-m3nulcb.dts
Normal file
33
arch/arm/dts/r8a77965-m3nulcb.dts
Normal file
@ -0,0 +1,33 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the M3NULCB (R-Car Starter Kit Pro) board
|
||||
*
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
* Copyright (C) 2018 Cogent Embedded, Inc.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "r8a77965.dtsi"
|
||||
#include "ulcb.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Renesas M3NULCB board based on r8a77965";
|
||||
compatible = "renesas,m3nulcb", "renesas,r8a77965";
|
||||
|
||||
memory@48000000 {
|
||||
device_type = "memory";
|
||||
/* first 128MB is reserved for secure area. */
|
||||
reg = <0x0 0x48000000 0x0 0x78000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&cpg CPG_MOD 721>,
|
||||
<&versaclock5 1>,
|
||||
<&versaclock5 3>,
|
||||
<&versaclock5 2>;
|
||||
clock-names = "du.0", "du.1", "du.3",
|
||||
"dclkin.0", "dclkin.1", "dclkin.3";
|
||||
};
|
||||
@ -8,23 +8,6 @@
|
||||
#include "r8a77965-salvator-x.dts"
|
||||
#include "r8a77965-u-boot.dtsi"
|
||||
|
||||
&vcc_sdhi0 {
|
||||
u-boot,off-on-delay-us = <20000>;
|
||||
};
|
||||
|
||||
&vcc_sdhi3 {
|
||||
u-boot,off-on-delay-us = <20000>;
|
||||
};
|
||||
|
||||
&sdhi2_pins {
|
||||
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
&sdhi2_pins_uhs {
|
||||
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
|
||||
@ -11,12 +11,14 @@
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&soc {
|
||||
rpc: rpc@0xee200000 {
|
||||
compatible = "renesas,rpc-r8a77965", "renesas,rpc";
|
||||
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
bank-width = <2>;
|
||||
status = "disabled";
|
||||
/ {
|
||||
soc {
|
||||
rpc: rpc@0xee200000 {
|
||||
compatible = "renesas,rpc-r8a77965", "renesas,rpc";
|
||||
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
bank-width = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the r8a77965 SoC
|
||||
* Device Tree Source for the R-Car M3-N (R8A77965) SoC
|
||||
*
|
||||
* Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
|
||||
*
|
||||
@ -12,7 +12,7 @@
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/power/r8a77965-sysc.h>
|
||||
|
||||
#define CPG_AUDIO_CLK_I 10
|
||||
#define CPG_AUDIO_CLK_I R8A77965_CLK_S0D4
|
||||
|
||||
/ {
|
||||
compatible = "renesas,r8a77965";
|
||||
@ -60,26 +60,70 @@
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
cluster0_opp: opp_table0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp-500000000 {
|
||||
opp-hz = /bits/ 64 <500000000>;
|
||||
opp-microvolt = <830000>;
|
||||
clock-latency-ns = <300000>;
|
||||
};
|
||||
opp-1000000000 {
|
||||
opp-hz = /bits/ 64 <1000000000>;
|
||||
opp-microvolt = <830000>;
|
||||
clock-latency-ns = <300000>;
|
||||
};
|
||||
opp-1500000000 {
|
||||
opp-hz = /bits/ 64 <1500000000>;
|
||||
opp-microvolt = <830000>;
|
||||
clock-latency-ns = <300000>;
|
||||
opp-suspend;
|
||||
};
|
||||
opp-1600000000 {
|
||||
opp-hz = /bits/ 64 <1600000000>;
|
||||
opp-microvolt = <900000>;
|
||||
clock-latency-ns = <300000>;
|
||||
turbo-mode;
|
||||
};
|
||||
opp-1700000000 {
|
||||
opp-hz = /bits/ 64 <1700000000>;
|
||||
opp-microvolt = <900000>;
|
||||
clock-latency-ns = <300000>;
|
||||
turbo-mode;
|
||||
};
|
||||
opp-1800000000 {
|
||||
opp-hz = /bits/ 64 <1800000000>;
|
||||
opp-microvolt = <960000>;
|
||||
clock-latency-ns = <300000>;
|
||||
turbo-mode;
|
||||
};
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
a57_0: cpu@0 {
|
||||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x0>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A77965_PD_CA57_CPU0>;
|
||||
next-level-cache = <&L2_CA57>;
|
||||
enable-method = "psci";
|
||||
clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
};
|
||||
|
||||
a57_1: cpu@1 {
|
||||
compatible = "arm,cortex-a57", "arm,armv8";
|
||||
compatible = "arm,cortex-a57";
|
||||
reg = <0x1>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A77965_PD_CA57_CPU1>;
|
||||
next-level-cache = <&L2_CA57>;
|
||||
enable-method = "psci";
|
||||
clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
};
|
||||
|
||||
L2_CA57: cache-controller-0 {
|
||||
@ -131,7 +175,7 @@
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
@ -306,7 +350,6 @@
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 522>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
intc_ex: interrupt-controller@e61c0000 {
|
||||
@ -545,11 +588,11 @@
|
||||
};
|
||||
|
||||
hsusb: usb@e6590000 {
|
||||
compatible = "renesas,usbhs-r8a7796",
|
||||
compatible = "renesas,usbhs-r8a77965",
|
||||
"renesas,rcar-gen3-usbhs";
|
||||
reg = <0 0xe6590000 0 0x100>;
|
||||
reg = <0 0xe6590000 0 0x200>;
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 704>;
|
||||
clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
|
||||
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
|
||||
<&usb_dmac1 0>, <&usb_dmac1 1>;
|
||||
dma-names = "ch0", "ch1", "ch2", "ch3";
|
||||
@ -557,7 +600,7 @@
|
||||
phys = <&usb2_phy0>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 704>;
|
||||
resets = <&cpg 704>, <&cpg 703>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -634,6 +677,14 @@
|
||||
resets = <&cpg 219>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <16>;
|
||||
iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
|
||||
<&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
|
||||
<&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
|
||||
<&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
|
||||
<&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
|
||||
<&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
|
||||
<&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
|
||||
<&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
|
||||
};
|
||||
|
||||
dmac1: dma-controller@e7300000 {
|
||||
@ -668,6 +719,14 @@
|
||||
resets = <&cpg 218>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <16>;
|
||||
iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
|
||||
<&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
|
||||
<&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
|
||||
<&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
|
||||
<&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
|
||||
<&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
|
||||
<&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
|
||||
<&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
|
||||
};
|
||||
|
||||
dmac2: dma-controller@e7310000 {
|
||||
@ -702,6 +761,14 @@
|
||||
resets = <&cpg 217>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <16>;
|
||||
iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
|
||||
<&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
|
||||
<&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
|
||||
<&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
|
||||
<&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
|
||||
<&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
|
||||
<&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
|
||||
<&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
|
||||
};
|
||||
|
||||
ipmmu_ds0: mmu@e6740000 {
|
||||
@ -728,14 +795,6 @@
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_ir: mmu@ff8b0000 {
|
||||
compatible = "renesas,ipmmu-r8a77965";
|
||||
reg = <0 0xff8b0000 0 0x1000>;
|
||||
renesas,ipmmu-main = <&ipmmu_mm 3>;
|
||||
power-domains = <&sysc R8A77965_PD_A3IR>;
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
ipmmu_mm: mmu@e67b0000 {
|
||||
compatible = "renesas,ipmmu-r8a77965";
|
||||
reg = <0 0xe67b0000 0 0x1000>;
|
||||
@ -833,11 +892,69 @@
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 812>;
|
||||
phy-mode = "rgmii";
|
||||
iommus = <&ipmmu_ds0 16>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can0: can@e6c30000 {
|
||||
compatible = "renesas,can-r8a77965",
|
||||
"renesas,rcar-gen3-can";
|
||||
reg = <0 0xe6c30000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 916>,
|
||||
<&cpg CPG_CORE R8A77965_CLK_CANFD>,
|
||||
<&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 916>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can1: can@e6c38000 {
|
||||
compatible = "renesas,can-r8a77965",
|
||||
"renesas,rcar-gen3-can";
|
||||
reg = <0 0xe6c38000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 915>,
|
||||
<&cpg CPG_CORE R8A77965_CLK_CANFD>,
|
||||
<&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 915>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
canfd: can@e66c0000 {
|
||||
compatible = "renesas,r8a77965-canfd",
|
||||
"renesas,rcar-gen3-canfd";
|
||||
reg = <0 0xe66c0000 0 0x8000>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 914>,
|
||||
<&cpg CPG_CORE R8A77965_CLK_CANFD>,
|
||||
<&can_clk>;
|
||||
clock-names = "fck", "canfd", "can_clk";
|
||||
assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>;
|
||||
assigned-clock-rates = <40000000>;
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 914>;
|
||||
status = "disabled";
|
||||
|
||||
channel0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
channel1 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
pwm0: pwm@e6e30000 {
|
||||
compatible = "renesas,pwm-r8a77965", "renesas,pwm-rcar";
|
||||
reg = <0 0xe6e30000 0 8>;
|
||||
@ -951,6 +1068,9 @@
|
||||
<&cpg CPG_CORE R8A77965_CLK_S3D1>,
|
||||
<&scif_clk>;
|
||||
clock-names = "fck", "brg_int", "scif_clk";
|
||||
dmas = <&dmac1 0x13>, <&dmac1 0x12>,
|
||||
<&dmac2 0x13>, <&dmac2 0x12>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 310>;
|
||||
status = "disabled";
|
||||
@ -1089,11 +1209,11 @@
|
||||
|
||||
vin0csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint= <&csi20vin0>;
|
||||
remote-endpoint = <&csi20vin0>;
|
||||
};
|
||||
vin0csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin0>;
|
||||
remote-endpoint = <&csi40vin0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1121,11 +1241,11 @@
|
||||
|
||||
vin1csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint= <&csi20vin1>;
|
||||
remote-endpoint = <&csi20vin1>;
|
||||
};
|
||||
vin1csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin1>;
|
||||
remote-endpoint = <&csi40vin1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1153,11 +1273,11 @@
|
||||
|
||||
vin2csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint= <&csi20vin2>;
|
||||
remote-endpoint = <&csi20vin2>;
|
||||
};
|
||||
vin2csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin2>;
|
||||
remote-endpoint = <&csi40vin2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1185,11 +1305,11 @@
|
||||
|
||||
vin3csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint= <&csi20vin3>;
|
||||
remote-endpoint = <&csi20vin3>;
|
||||
};
|
||||
vin3csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin3>;
|
||||
remote-endpoint = <&csi40vin3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1217,11 +1337,11 @@
|
||||
|
||||
vin4csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint= <&csi20vin4>;
|
||||
remote-endpoint = <&csi20vin4>;
|
||||
};
|
||||
vin4csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin4>;
|
||||
remote-endpoint = <&csi40vin4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1249,11 +1369,11 @@
|
||||
|
||||
vin5csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint= <&csi20vin5>;
|
||||
remote-endpoint = <&csi20vin5>;
|
||||
};
|
||||
vin5csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin5>;
|
||||
remote-endpoint = <&csi40vin5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1281,11 +1401,11 @@
|
||||
|
||||
vin6csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint= <&csi20vin6>;
|
||||
remote-endpoint = <&csi20vin6>;
|
||||
};
|
||||
vin6csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin6>;
|
||||
remote-endpoint = <&csi40vin6>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1313,55 +1433,278 @@
|
||||
|
||||
vin7csi20: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint= <&csi20vin7>;
|
||||
remote-endpoint = <&csi20vin7>;
|
||||
};
|
||||
vin7csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin7>;
|
||||
remote-endpoint = <&csi40vin7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rcar_sound: sound@ec500000 {
|
||||
/*
|
||||
* #sound-dai-cells is required
|
||||
*
|
||||
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
|
||||
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
|
||||
*/
|
||||
/*
|
||||
* #clock-cells is required for audio_clkout0/1/2/3
|
||||
*
|
||||
* clkout : #clock-cells = <0>; <&rcar_sound>;
|
||||
* clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
|
||||
*/
|
||||
compatible = "renesas,rcar_sound-r8a77965", "renesas,rcar_sound-gen3";
|
||||
reg = <0 0xec500000 0 0x1000>, /* SCU */
|
||||
<0 0xec5a0000 0 0x100>, /* ADG */
|
||||
<0 0xec540000 0 0x1000>, /* SSIU */
|
||||
<0 0xec541000 0 0x280>, /* SSI */
|
||||
<0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
|
||||
/* placeholder */
|
||||
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
|
||||
|
||||
clocks = <&cpg CPG_MOD 1005>,
|
||||
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
|
||||
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
|
||||
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
|
||||
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
|
||||
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
|
||||
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
|
||||
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
|
||||
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
|
||||
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
|
||||
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
|
||||
<&audio_clk_a>, <&audio_clk_b>,
|
||||
<&audio_clk_c>,
|
||||
<&cpg CPG_CORE R8A77965_CLK_S0D4>;
|
||||
clock-names = "ssi-all",
|
||||
"ssi.9", "ssi.8", "ssi.7", "ssi.6",
|
||||
"ssi.5", "ssi.4", "ssi.3", "ssi.2",
|
||||
"ssi.1", "ssi.0",
|
||||
"src.9", "src.8", "src.7", "src.6",
|
||||
"src.5", "src.4", "src.3", "src.2",
|
||||
"src.1", "src.0",
|
||||
"mix.1", "mix.0",
|
||||
"ctu.1", "ctu.0",
|
||||
"dvc.0", "dvc.1",
|
||||
"clk_a", "clk_b", "clk_c", "clk_i";
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 1005>,
|
||||
<&cpg 1006>, <&cpg 1007>,
|
||||
<&cpg 1008>, <&cpg 1009>,
|
||||
<&cpg 1010>, <&cpg 1011>,
|
||||
<&cpg 1012>, <&cpg 1013>,
|
||||
<&cpg 1014>, <&cpg 1015>;
|
||||
reset-names = "ssi-all",
|
||||
"ssi.9", "ssi.8", "ssi.7", "ssi.6",
|
||||
"ssi.5", "ssi.4", "ssi.3", "ssi.2",
|
||||
"ssi.1", "ssi.0";
|
||||
status = "disabled";
|
||||
|
||||
rcar_sound,dvc {
|
||||
dvc0: dvc-0 {
|
||||
dmas = <&audma1 0xbc>;
|
||||
dma-names = "tx";
|
||||
};
|
||||
dvc1: dvc-1 {
|
||||
dmas = <&audma1 0xbe>;
|
||||
dma-names = "tx";
|
||||
};
|
||||
};
|
||||
|
||||
rcar_sound,mix {
|
||||
mix0: mix-0 { };
|
||||
mix1: mix-1 { };
|
||||
};
|
||||
|
||||
rcar_sound,ctu {
|
||||
ctu00: ctu-0 { };
|
||||
ctu01: ctu-1 { };
|
||||
ctu02: ctu-2 { };
|
||||
ctu03: ctu-3 { };
|
||||
ctu10: ctu-4 { };
|
||||
ctu11: ctu-5 { };
|
||||
ctu12: ctu-6 { };
|
||||
ctu13: ctu-7 { };
|
||||
};
|
||||
|
||||
rcar_sound,src {
|
||||
src0: src-0 {
|
||||
interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x85>, <&audma1 0x9a>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
src1: src-1 {
|
||||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x87>, <&audma1 0x9c>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
src2: src-2 {
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x89>, <&audma1 0x9e>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
src3: src-3 {
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x8b>, <&audma1 0xa0>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
src4: src-4 {
|
||||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x8d>, <&audma1 0xb0>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
src5: src-5 {
|
||||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x8f>, <&audma1 0xb2>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
src6: src-6 {
|
||||
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x91>, <&audma1 0xb4>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
src7: src-7 {
|
||||
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x93>, <&audma1 0xb6>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
src8: src-8 {
|
||||
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x95>, <&audma1 0xb8>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
src9: src-9 {
|
||||
interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x97>, <&audma1 0xba>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
};
|
||||
|
||||
rcar_sound,ssi {
|
||||
ssi0: ssi-0 {
|
||||
interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
ssi1: ssi-1 {
|
||||
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
ssi2: ssi-2 {
|
||||
interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
ssi3: ssi-3 {
|
||||
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
ssi4: ssi-4 {
|
||||
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
ssi5: ssi-5 {
|
||||
interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
ssi6: ssi-6 {
|
||||
interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
ssi7: ssi-7 {
|
||||
interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
ssi8: ssi-8 {
|
||||
interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
ssi9: ssi-9 {
|
||||
interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
|
||||
dma-names = "rx", "tx", "rxu", "txu";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
audma0: dma-controller@ec700000 {
|
||||
compatible = "renesas,dmac-r8a77965",
|
||||
"renesas,rcar-dmac";
|
||||
reg = <0 0xec700000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14", "ch15";
|
||||
clocks = <&cpg CPG_MOD 502>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 502>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <16>;
|
||||
};
|
||||
|
||||
audma1: dma-controller@ec720000 {
|
||||
compatible = "renesas,dmac-r8a77965",
|
||||
"renesas,rcar-dmac";
|
||||
reg = <0 0xec720000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "error",
|
||||
"ch0", "ch1", "ch2", "ch3",
|
||||
"ch4", "ch5", "ch6", "ch7",
|
||||
"ch8", "ch9", "ch10", "ch11",
|
||||
"ch12", "ch13", "ch14", "ch15";
|
||||
clocks = <&cpg CPG_MOD 501>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 501>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <16>;
|
||||
};
|
||||
|
||||
xhci0: usb@ee000000 {
|
||||
@ -1390,11 +1733,11 @@
|
||||
compatible = "generic-ohci";
|
||||
reg = <0 0xee080000 0 0x100>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 703>;
|
||||
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
|
||||
phys = <&usb2_phy0>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 703>;
|
||||
resets = <&cpg 703>, <&cpg 704>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1414,12 +1757,12 @@
|
||||
compatible = "generic-ehci";
|
||||
reg = <0 0xee080100 0 0x100>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 703>;
|
||||
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
|
||||
phys = <&usb2_phy0>;
|
||||
phy-names = "usb";
|
||||
companion = <&ohci0>;
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 703>;
|
||||
resets = <&cpg 703>, <&cpg 704>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -1441,9 +1784,9 @@
|
||||
"renesas,rcar-gen3-usb2-phy";
|
||||
reg = <0 0xee080200 0 0x700>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 703>;
|
||||
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 703>;
|
||||
resets = <&cpg 703>, <&cpg 704>;
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -1452,9 +1795,9 @@
|
||||
compatible = "renesas,usb2-phy-r8a77965",
|
||||
"renesas,rcar-gen3-usb2-phy";
|
||||
reg = <0 0xee0a0200 0 0x700>;
|
||||
clocks = <&cpg CPG_MOD 703>;
|
||||
clocks = <&cpg CPG_MOD 702>;
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 703>;
|
||||
resets = <&cpg 702>;
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -1507,6 +1850,17 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sata: sata@ee300000 {
|
||||
compatible = "renesas,sata-r8a77965",
|
||||
"renesas,rcar-gen3-sata";
|
||||
reg = <0 0xee300000 0 0x200000>;
|
||||
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 815>;
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 815>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f1010000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
@ -1578,6 +1932,16 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
fdp1@fe940000 {
|
||||
compatible = "renesas,fdp1";
|
||||
reg = <0 0xfe940000 0 0x2400>;
|
||||
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 119>;
|
||||
power-domains = <&sysc R8A77965_PD_A3VP>;
|
||||
resets = <&cpg 119>;
|
||||
renesas,fcp = <&fcpf0>;
|
||||
};
|
||||
|
||||
fcpf0: fcp@fe950000 {
|
||||
compatible = "renesas,fcpf";
|
||||
reg = <0 0xfe950000 0 0x200>;
|
||||
@ -1832,6 +2196,33 @@
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
du_out_lvds0: endpoint {
|
||||
remote-endpoint = <&lvds0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lvds0: lvds@feb90000 {
|
||||
compatible = "renesas,r8a77965-lvds";
|
||||
reg = <0 0xfeb90000 0 0x14>;
|
||||
clocks = <&cpg CPG_MOD 727>;
|
||||
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 727>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
lvds0_in: endpoint {
|
||||
remote-endpoint = <&du_out_lvds0>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
lvds0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -1843,14 +2234,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
sensor_thermal1: sensor-thermal1 {
|
||||
polling-delay-passive = <250>;
|
||||
@ -1895,6 +2278,14 @@
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
/* External USB clocks - can be overridden by the board */
|
||||
usb3s0_clk: usb3s0 {
|
||||
compatible = "fixed-clock";
|
||||
|
||||
@ -11,12 +11,14 @@
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
|
||||
&soc {
|
||||
rpc: rpc@0xee200000 {
|
||||
compatible = "renesas,rpc-r8a77970", "renesas,rpc";
|
||||
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
bank-width = <2>;
|
||||
status = "disabled";
|
||||
/ {
|
||||
soc {
|
||||
rpc: rpc@0xee200000 {
|
||||
compatible = "renesas,rpc-r8a77970", "renesas,rpc";
|
||||
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
bank-width = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the r8a77970 SoC
|
||||
* Device Tree Source for the R-Car V3M (R8A77970) SoC
|
||||
*
|
||||
* Copyright (C) 2016-2017 Renesas Electronics Corp.
|
||||
* Copyright (C) 2017 Cogent Embedded, Inc.
|
||||
@ -24,13 +24,20 @@
|
||||
i2c4 = &i2c4;
|
||||
};
|
||||
|
||||
/* External CAN clock - to be overridden by boards that provide it */
|
||||
can_clk: can {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
a53_0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0>;
|
||||
clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
|
||||
power-domains = <&sysc R8A77970_PD_CA53_CPU0>;
|
||||
@ -40,7 +47,7 @@
|
||||
|
||||
a53_1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <1>;
|
||||
clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
|
||||
power-domains = <&sysc R8A77970_PD_CA53_CPU1>;
|
||||
@ -82,13 +89,6 @@
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
/* External CAN clock - to be overridden by boards that provide it */
|
||||
can_clk: can {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
/* External SCIF clock - to be overridden by boards that provide it */
|
||||
scif_clk: scif {
|
||||
compatible = "fixed-clock";
|
||||
@ -96,7 +96,7 @@
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
@ -209,6 +209,76 @@
|
||||
reg = <0 0xe6060000 0 0x504>;
|
||||
};
|
||||
|
||||
cmt0: timer@e60f0000 {
|
||||
compatible = "renesas,r8a77970-cmt0",
|
||||
"renesas,rcar-gen3-cmt0";
|
||||
reg = <0 0xe60f0000 0 0x1004>;
|
||||
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 303>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 303>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cmt1: timer@e6130000 {
|
||||
compatible = "renesas,r8a77970-cmt1",
|
||||
"renesas,rcar-gen3-cmt1";
|
||||
reg = <0 0xe6130000 0 0x1004>;
|
||||
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 302>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 302>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cmt2: timer@e6140000 {
|
||||
compatible = "renesas,r8a77970-cmt1",
|
||||
"renesas,rcar-gen3-cmt1";
|
||||
reg = <0 0xe6140000 0 0x1004>;
|
||||
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 301>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 301>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cmt3: timer@e6148000 {
|
||||
compatible = "renesas,r8a77970-cmt1",
|
||||
"renesas,rcar-gen3-cmt1";
|
||||
reg = <0 0xe6148000 0 0x1004>;
|
||||
interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 300>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 300>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cpg: clock-controller@e6150000 {
|
||||
compatible = "renesas,r8a77970-cpg-mssr";
|
||||
reg = <0 0xe6150000 0 0x1000>;
|
||||
@ -230,6 +300,19 @@
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
thermal: thermal@e6190000 {
|
||||
compatible = "renesas,thermal-r8a77970";
|
||||
reg = <0 0xe6190000 0 0x10
|
||||
0 0xe6190100 0 0x120>;
|
||||
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 522>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 522>;
|
||||
#thermal-sensor-cells = <0>;
|
||||
};
|
||||
|
||||
intc_ex: interrupt-controller@e61c0000 {
|
||||
compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
|
||||
#interrupt-cells = <2>;
|
||||
@ -246,6 +329,71 @@
|
||||
resets = <&cpg 407>;
|
||||
};
|
||||
|
||||
tmu0: timer@e61e0000 {
|
||||
compatible = "renesas,tmu-r8a77970", "renesas,tmu";
|
||||
reg = <0 0xe61e0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 125>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 125>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu1: timer@e6fc0000 {
|
||||
compatible = "renesas,tmu-r8a77970", "renesas,tmu";
|
||||
reg = <0 0xe6fc0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 124>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 124>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu2: timer@e6fd0000 {
|
||||
compatible = "renesas,tmu-r8a77970", "renesas,tmu";
|
||||
reg = <0 0xe6fd0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 123>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 123>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu3: timer@e6fe0000 {
|
||||
compatible = "renesas,tmu-r8a77970", "renesas,tmu";
|
||||
reg = <0 0xe6fe0000 0 0x30>;
|
||||
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 122>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 122>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tmu4: timer@ffc00000 {
|
||||
compatible = "renesas,tmu-r8a77970", "renesas,tmu";
|
||||
reg = <0 0xffc00000 0 0x30>;
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 121>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 121>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@e6500000 {
|
||||
compatible = "renesas,i2c-r8a77970",
|
||||
"renesas,rcar-gen3-i2c";
|
||||
@ -473,6 +621,56 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm0: pwm@e6e30000 {
|
||||
compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar";
|
||||
reg = <0 0xe6e30000 0 8>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&cpg CPG_MOD 523>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 523>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm1: pwm@e6e31000 {
|
||||
compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar";
|
||||
reg = <0 0xe6e31000 0 8>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&cpg CPG_MOD 523>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 523>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2: pwm@e6e32000 {
|
||||
compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar";
|
||||
reg = <0 0xe6e32000 0 8>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&cpg CPG_MOD 523>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 523>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm3: pwm@e6e33000 {
|
||||
compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
|
||||
reg = <0 0xe6e33000 0 8>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&cpg CPG_MOD 523>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 523>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm4: pwm@e6e34000 {
|
||||
compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar";
|
||||
reg = <0 0xe6e34000 0 8>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&cpg CPG_MOD 523>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 523>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scif0: serial@e6e60000 {
|
||||
compatible = "renesas,scif-r8a77970",
|
||||
"renesas,rcar-gen3-scif",
|
||||
@ -544,6 +742,80 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tpu: pwm@e6e80000 {
|
||||
compatible = "renesas,tpu-r8a77970", "renesas,tpu";
|
||||
reg = <0 0xe6e80000 0 0x148>;
|
||||
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 304>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 304>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
msiof0: spi@e6e90000 {
|
||||
compatible = "renesas,msiof-r8a77970",
|
||||
"renesas,rcar-gen3-msiof";
|
||||
reg = <0 0xe6e90000 0 0x64>;
|
||||
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 211>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 211>;
|
||||
dmas = <&dmac1 0x41>, <&dmac1 0x40>,
|
||||
<&dmac2 0x41>, <&dmac2 0x40>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
msiof1: spi@e6ea0000 {
|
||||
compatible = "renesas,msiof-r8a77970",
|
||||
"renesas,rcar-gen3-msiof";
|
||||
reg = <0 0xe6ea0000 0 0x0064>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 210>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 210>;
|
||||
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
|
||||
<&dmac2 0x43>, <&dmac2 0x42>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
msiof2: spi@e6c00000 {
|
||||
compatible = "renesas,msiof-r8a77970",
|
||||
"renesas,rcar-gen3-msiof";
|
||||
reg = <0 0xe6c00000 0 0x0064>;
|
||||
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 209>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 209>;
|
||||
dmas = <&dmac1 0x45>, <&dmac1 0x44>,
|
||||
<&dmac2 0x45>, <&dmac2 0x44>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
msiof3: spi@e6c10000 {
|
||||
compatible = "renesas,msiof-r8a77970",
|
||||
"renesas,rcar-gen3-msiof";
|
||||
reg = <0 0xe6c10000 0 0x0064>;
|
||||
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 208>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 208>;
|
||||
dmas = <&dmac1 0x47>, <&dmac1 0x46>,
|
||||
<&dmac2 0x47>, <&dmac2 0x46>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vin0: video@e6ef0000 {
|
||||
compatible = "renesas,vin-r8a77970";
|
||||
@ -567,7 +839,7 @@
|
||||
|
||||
vin0csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin0>;
|
||||
remote-endpoint = <&csi40vin0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -595,7 +867,7 @@
|
||||
|
||||
vin1csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin1>;
|
||||
remote-endpoint = <&csi40vin1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -623,7 +895,7 @@
|
||||
|
||||
vin2csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin2>;
|
||||
remote-endpoint = <&csi40vin2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -651,7 +923,7 @@
|
||||
|
||||
vin3csi40: endpoint@2 {
|
||||
reg = <2>;
|
||||
remote-endpoint= <&csi40vin3>;
|
||||
remote-endpoint = <&csi40vin3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -754,6 +1026,18 @@
|
||||
#iommu-cells = <1>;
|
||||
};
|
||||
|
||||
mmc0: mmc@ee140000 {
|
||||
compatible = "renesas,sdhi-r8a77970",
|
||||
"renesas,rcar-gen3-sdhi";
|
||||
reg = <0 0xee140000 0 0x2000>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 314>;
|
||||
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 314>;
|
||||
max-frequency = <200000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f1010000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
@ -891,6 +1175,25 @@
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu-thermal {
|
||||
polling-delay-passive = <250>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&thermal>;
|
||||
|
||||
trips {
|
||||
cpu-crit {
|
||||
temperature = <120000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
|
||||
@ -8,181 +8,24 @@
|
||||
#include "r8a77990-ebisu.dts"
|
||||
#include "r8a77990-u-boot.dtsi"
|
||||
|
||||
/ {
|
||||
reg_1p8v: regulator0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_sdhi0: regulator-vcc-sdhi0 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI0 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
u-boot,off-on-delay-us = <20000>;
|
||||
};
|
||||
|
||||
vccq_sdhi0: regulator-vccq-sdhi0 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI0 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
vcc_sdhi1: regulator-vcc-sdhi1 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI1 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
u-boot,off-on-delay-us = <20000>;
|
||||
};
|
||||
|
||||
vccq_sdhi1: regulator-vccq-sdhi1 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI1 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pfc {
|
||||
pinctrl-0 = <&scif_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
scif2_pins: scif2 {
|
||||
groups = "scif2_data_a";
|
||||
function = "scif2";
|
||||
};
|
||||
|
||||
scif_clk_pins: scif_clk {
|
||||
groups = "scif_clk_a";
|
||||
function = "scif_clk";
|
||||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi0_pins_uhs: sd0_uhs {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sdhi1_pins: sd1 {
|
||||
groups = "sdhi1_data4", "sdhi1_ctrl";
|
||||
function = "sdhi1";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi1_pins_uhs: sd1_uhs {
|
||||
groups = "sdhi1_data4", "sdhi1_ctrl";
|
||||
function = "sdhi1";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sdhi3_pins: sd2 {
|
||||
groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
|
||||
function = "sdhi3";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sdhi3_pins_uhs: sd2_uhs {
|
||||
groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
|
||||
function = "sdhi3";
|
||||
power-source = <1800>;
|
||||
};
|
||||
};
|
||||
|
||||
&scif2 {
|
||||
pinctrl-0 = <&scif2_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
/* full size SD */
|
||||
pinctrl-0 = <&sdhi0_pins>;
|
||||
pinctrl-1 = <&sdhi0_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi0>;
|
||||
vqmmc-supply = <&vccq_sdhi0>;
|
||||
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
|
||||
bus-width = <4>;
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
max-frequency = <208000000>;
|
||||
};
|
||||
|
||||
&sdhi1 {
|
||||
/* microSD */
|
||||
pinctrl-0 = <&sdhi1_pins>;
|
||||
pinctrl-1 = <&sdhi1_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi1>;
|
||||
vqmmc-supply = <&vccq_sdhi1>;
|
||||
cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
|
||||
bus-width = <4>;
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
max-frequency = <208000000>;
|
||||
};
|
||||
|
||||
&sdhi3 {
|
||||
/* used for on-board 8bit eMMC */
|
||||
pinctrl-0 = <&sdhi3_pins>;
|
||||
pinctrl-1 = <&sdhi3_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <®_3p3v>;
|
||||
vqmmc-supply = <®_1p8v>;
|
||||
bus-width = <8>;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -28,6 +28,235 @@
|
||||
/* first 128MB is reserved for secure area. */
|
||||
reg = <0x0 0x48000000 0x0 0x38000000>;
|
||||
};
|
||||
|
||||
audio_clkout: audio-clkout {
|
||||
/*
|
||||
* This is same as <&rcar_sound 0>
|
||||
* but needed to avoid cs2000/rcar_sound probe dead-lock
|
||||
*/
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <11289600>;
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm3 0 50000>;
|
||||
|
||||
brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
|
||||
default-brightness-level = <10>;
|
||||
|
||||
power-supply = <®_12p0v>;
|
||||
};
|
||||
|
||||
cvbs-in {
|
||||
compatible = "composite-video-connector";
|
||||
label = "CVBS IN";
|
||||
|
||||
port {
|
||||
cvbs_con: endpoint {
|
||||
remote-endpoint = <&adv7482_ain7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-in {
|
||||
compatible = "hdmi-connector";
|
||||
label = "HDMI IN";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_in_con: endpoint {
|
||||
remote-endpoint = <&adv7482_hdmi>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-out {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_out: endpoint {
|
||||
remote-endpoint = <&adv7511_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lvds-decoder {
|
||||
compatible = "thine,thc63lvd1024";
|
||||
vcc-supply = <®_3p3v>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
thc63lvd1024_in: endpoint {
|
||||
remote-endpoint = <&lvds0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
thc63lvd1024_out: endpoint {
|
||||
remote-endpoint = <&adv7511_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vga {
|
||||
compatible = "vga-connector";
|
||||
|
||||
port {
|
||||
vga_in: endpoint {
|
||||
remote-endpoint = <&adv7123_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vga-encoder {
|
||||
compatible = "adi,adv7123";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7123_in: endpoint {
|
||||
remote-endpoint = <&du_out_rgb>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7123_out: endpoint {
|
||||
remote-endpoint = <&vga_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
reg_1p8v: regulator0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vbus0_usb2: regulator-vbus0-usb2 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "USB20_VBUS_CN";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
|
||||
gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
rsnd_ak4613: sound {
|
||||
compatible = "simple-audio-card";
|
||||
|
||||
simple-audio-card,name = "rsnd-ak4613";
|
||||
simple-audio-card,format = "left_j";
|
||||
simple-audio-card,bitclock-master = <&sndcpu>;
|
||||
simple-audio-card,frame-master = <&sndcpu>;
|
||||
|
||||
sndcpu: simple-audio-card,cpu {
|
||||
sound-dai = <&rcar_sound>;
|
||||
};
|
||||
|
||||
sndcodec: simple-audio-card,codec {
|
||||
sound-dai = <&ak4613>;
|
||||
};
|
||||
};
|
||||
|
||||
x12_clk: x12 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24576000>;
|
||||
};
|
||||
|
||||
reg_12p0v: regulator2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "D12.0V";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
x13_clk: x13 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <74250000>;
|
||||
};
|
||||
|
||||
vcc_sdhi0: regulator-vcc-sdhi0 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI0 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi0: regulator-vccq-sdhi0 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI0 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
|
||||
vcc_sdhi1: regulator-vcc-sdhi1 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "SDHI1 Vcc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vccq_sdhi1: regulator-vccq-sdhi1 {
|
||||
compatible = "regulator-gpio";
|
||||
|
||||
regulator-name = "SDHI1 VccQ";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <1>;
|
||||
states = <3300000 1
|
||||
1800000 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&audio_clk_a {
|
||||
clock-frequency = <22579200>;
|
||||
};
|
||||
|
||||
&avb {
|
||||
@ -35,7 +264,6 @@
|
||||
pinctrl-names = "default";
|
||||
renesas,no-ether-link;
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-txid";
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
@ -47,7 +275,53 @@
|
||||
};
|
||||
};
|
||||
|
||||
&canfd {
|
||||
pinctrl-0 = <&canfd0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
channel0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&csi40 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
csi40_in: endpoint {
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
remote-endpoint = <&adv7482_txa>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&x13_clk>;
|
||||
clock-names = "du.0", "du.1", "dclkin.0";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
endpoint {
|
||||
remote-endpoint = <&adv7123_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -55,7 +329,151 @@
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
&hsusb {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
hdmi-encoder@39 {
|
||||
compatible = "adi,adv7511w";
|
||||
reg = <0x39>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7511_in: endpoint {
|
||||
remote-endpoint = <&thc63lvd1024_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7511_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
video-receiver@70 {
|
||||
compatible = "adi,adv7482";
|
||||
reg = <0x70>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupt-names = "intrq1", "intrq2";
|
||||
interrupts = <7 IRQ_TYPE_LEVEL_LOW>,
|
||||
<17 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
port@7 {
|
||||
reg = <7>;
|
||||
|
||||
adv7482_ain7: endpoint {
|
||||
remote-endpoint = <&cvbs_con>;
|
||||
};
|
||||
};
|
||||
|
||||
port@8 {
|
||||
reg = <8>;
|
||||
|
||||
adv7482_hdmi: endpoint {
|
||||
remote-endpoint = <&hdmi_in_con>;
|
||||
};
|
||||
};
|
||||
|
||||
port@a {
|
||||
reg = <0xa>;
|
||||
|
||||
adv7482_txa: endpoint {
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
remote-endpoint = <&csi40_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
status = "okay";
|
||||
|
||||
ak4613: codec@10 {
|
||||
compatible = "asahi-kasei,ak4613";
|
||||
#sound-dai-cells = <0>;
|
||||
reg = <0x10>;
|
||||
clocks = <&rcar_sound 3>;
|
||||
|
||||
asahi-kasei,in1-single-end;
|
||||
asahi-kasei,in2-single-end;
|
||||
asahi-kasei,out1-single-end;
|
||||
asahi-kasei,out2-single-end;
|
||||
asahi-kasei,out3-single-end;
|
||||
asahi-kasei,out4-single-end;
|
||||
asahi-kasei,out5-single-end;
|
||||
asahi-kasei,out6-single-end;
|
||||
};
|
||||
|
||||
cs2000: clk-multiplier@4f {
|
||||
#clock-cells = <0>;
|
||||
compatible = "cirrus,cs2000-cp";
|
||||
reg = <0x4f>;
|
||||
clocks = <&audio_clkout>, <&x12_clk>;
|
||||
clock-names = "clk_in", "ref_clk";
|
||||
|
||||
assigned-clocks = <&cs2000>;
|
||||
assigned-clock-rates = <24576000>; /* 1/1 divide */
|
||||
};
|
||||
};
|
||||
|
||||
&lvds0 {
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 727>,
|
||||
<&x13_clk>,
|
||||
<&extal_clk>;
|
||||
clock-names = "fck", "dclkin.0", "extal";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
lvds0_out: endpoint {
|
||||
remote-endpoint = <&thc63lvd1024_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lvds1 {
|
||||
clocks = <&cpg CPG_MOD 727>,
|
||||
<&x13_clk>,
|
||||
<&extal_clk>;
|
||||
clock-names = "fck", "dclkin.0", "extal";
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_bus_clk {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
&pciec0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -67,8 +485,74 @@
|
||||
};
|
||||
};
|
||||
|
||||
canfd0_pins: canfd0 {
|
||||
groups = "canfd0_data";
|
||||
function = "canfd0";
|
||||
};
|
||||
|
||||
du_pins: du {
|
||||
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
|
||||
function = "du";
|
||||
};
|
||||
|
||||
pwm3_pins: pwm3 {
|
||||
groups = "pwm3_b";
|
||||
function = "pwm3";
|
||||
};
|
||||
|
||||
pwm5_pins: pwm5 {
|
||||
groups = "pwm5_a";
|
||||
function = "pwm5";
|
||||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi0_pins_uhs: sd0_uhs {
|
||||
groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
function = "sdhi0";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sdhi1_pins: sd1 {
|
||||
groups = "sdhi1_data4", "sdhi1_ctrl";
|
||||
function = "sdhi1";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi1_pins_uhs: sd1_uhs {
|
||||
groups = "sdhi1_data4", "sdhi1_ctrl";
|
||||
function = "sdhi1";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sdhi3_pins: sd3 {
|
||||
groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds";
|
||||
function = "sdhi3";
|
||||
power-source = <1800>;
|
||||
};
|
||||
|
||||
sound_pins: sound {
|
||||
groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data";
|
||||
function = "ssi";
|
||||
};
|
||||
|
||||
sound_clk_pins: sound_clk {
|
||||
groups = "audio_clk_a", "audio_clk_b_a", "audio_clk_c_a",
|
||||
"audio_clkout_a", "audio_clkout1_a";
|
||||
function = "audio_clk";
|
||||
};
|
||||
|
||||
scif2_pins: scif2 {
|
||||
groups = "scif2_data_a";
|
||||
function = "scif2";
|
||||
};
|
||||
|
||||
usb0_pins: usb {
|
||||
groups = "usb0_b";
|
||||
groups = "usb0_b", "usb0_id";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
@ -78,19 +562,91 @@
|
||||
};
|
||||
};
|
||||
|
||||
&pwm3 {
|
||||
pinctrl-0 = <&pwm3_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm5 {
|
||||
pinctrl-0 = <&pwm5_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rcar_sound {
|
||||
pinctrl-0 = <&sound_pins &sound_clk_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
/* Single DAI */
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
/* audio_clkout0/1/2/3 */
|
||||
#clock-cells = <1>;
|
||||
clock-frequency = <12288000 11289600>;
|
||||
clkout-lr-synchronous;
|
||||
|
||||
status = "okay";
|
||||
|
||||
/* update <audio_clk_b> to <cs2000> */
|
||||
clocks = <&cpg CPG_MOD 1005>,
|
||||
<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
|
||||
<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
|
||||
<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
|
||||
<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
|
||||
<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
|
||||
<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
|
||||
<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
|
||||
<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
|
||||
<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
|
||||
<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
||||
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
|
||||
<&audio_clk_a>, <&cs2000>, <&audio_clk_c>,
|
||||
<&cpg CPG_CORE R8A77990_CLK_ZA2>;
|
||||
|
||||
rcar_sound,dai {
|
||||
dai0 {
|
||||
playback = <&ssi0 &src0 &dvc0>;
|
||||
capture = <&ssi1 &src1 &dvc1>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&rwdt {
|
||||
timeout-sec = <60>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scif2 {
|
||||
pinctrl-0 = <&scif2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
shared-pin;
|
||||
};
|
||||
|
||||
&usb2_phy0 {
|
||||
pinctrl-0 = <&usb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vbus-supply = <&vbus0_usb2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_peri0 {
|
||||
companion = <&xhci0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vin4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -100,3 +656,47 @@
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
pinctrl-0 = <&sdhi0_pins>;
|
||||
pinctrl-1 = <&sdhi0_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi0>;
|
||||
vqmmc-supply = <&vccq_sdhi0>;
|
||||
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
|
||||
bus-width = <4>;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi1 {
|
||||
pinctrl-0 = <&sdhi1_pins>;
|
||||
pinctrl-1 = <&sdhi1_pins_uhs>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi1>;
|
||||
vqmmc-supply = <&vccq_sdhi1>;
|
||||
cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
|
||||
bus-width = <4>;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi3 {
|
||||
/* used for on-board 8bit eMMC */
|
||||
pinctrl-0 = <&sdhi3_pins>;
|
||||
pinctrl-1 = <&sdhi3_pins>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <®_3p3v>;
|
||||
vqmmc-supply = <®_1p8v>;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -7,36 +7,14 @@
|
||||
|
||||
#include "r8a779x-u-boot.dtsi"
|
||||
|
||||
&soc {
|
||||
rpc: rpc@0xee200000 {
|
||||
compatible = "renesas,rpc-r8a77990", "renesas,rpc";
|
||||
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
bank-width = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi0: sd@ee100000 {
|
||||
compatible = "renesas,sdhi-r8a77990";
|
||||
reg = <0 0xee100000 0 0x2000>;
|
||||
clocks = <&cpg CPG_MOD 314>;
|
||||
max-frequency = <200000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi1: sd@ee120000 {
|
||||
compatible = "renesas,sdhi-r8a77990";
|
||||
reg = <0 0xee120000 0 0x2000>;
|
||||
clocks = <&cpg CPG_MOD 313>;
|
||||
max-frequency = <200000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi3: sd@ee160000 {
|
||||
compatible = "renesas,sdhi-r8a77990";
|
||||
reg = <0 0xee160000 0 0x2000>;
|
||||
clocks = <&cpg CPG_MOD 311>;
|
||||
max-frequency = <200000000>;
|
||||
status = "disabled";
|
||||
/ {
|
||||
soc {
|
||||
rpc: rpc@0xee200000 {
|
||||
compatible = "renesas,rpc-r8a77990", "renesas,rpc";
|
||||
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
bank-width = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -2,7 +2,7 @@
|
||||
/*
|
||||
* Device Tree Source for the Draak board
|
||||
*
|
||||
* Copyright (C) 2016 Renesas Electronics Corp.
|
||||
* Copyright (C) 2016-2018 Renesas Electronics Corp.
|
||||
* Copyright (C) 2017 Glider bvba
|
||||
*/
|
||||
|
||||
@ -24,6 +24,106 @@
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm1 0 50000>;
|
||||
|
||||
brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
|
||||
default-brightness-level = <10>;
|
||||
|
||||
power-supply = <®_12p0v>;
|
||||
enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
composite-in {
|
||||
compatible = "composite-video-connector";
|
||||
|
||||
port {
|
||||
composite_con_in: endpoint {
|
||||
remote-endpoint = <&adv7180_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-in {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&adv7612_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-out {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_out: endpoint {
|
||||
remote-endpoint = <&adv7511_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lvds-decoder {
|
||||
compatible = "thine,thc63lvd1024";
|
||||
vcc-supply = <®_3p3v>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
thc63lvd1024_in: endpoint {
|
||||
remote-endpoint = <&lvds0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
thc63lvd1024_out: endpoint {
|
||||
remote-endpoint = <&adv7511_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
memory@48000000 {
|
||||
device_type = "memory";
|
||||
/* first 128MB is reserved for secure area. */
|
||||
reg = <0x0 0x48000000 0x0 0x18000000>;
|
||||
};
|
||||
|
||||
reg_1p8v: regulator0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_12p0v: regulator1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "D12.0V";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vga {
|
||||
compatible = "vga-connector";
|
||||
|
||||
@ -56,51 +156,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
composite-in {
|
||||
compatible = "composite-video-connector";
|
||||
|
||||
port {
|
||||
composite_con_in: endpoint {
|
||||
remote-endpoint = <&adv7180_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-in {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&adv7612_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
memory@48000000 {
|
||||
device_type = "memory";
|
||||
/* first 128MB is reserved for secure area. */
|
||||
reg = <0x0 0x48000000 0x0 0x18000000>;
|
||||
};
|
||||
|
||||
reg_1p8v: regulator0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
x12_clk: x12 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
@ -108,10 +163,210 @@
|
||||
};
|
||||
};
|
||||
|
||||
&avb {
|
||||
pinctrl-0 = <&avb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
renesas,no-ether-link;
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-txid";
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
rxc-skew-ps = <1500>;
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio5>;
|
||||
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&x12_clk>;
|
||||
clock-names = "du.0", "du.1", "dclkin.0";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
endpoint {
|
||||
remote-endpoint = <&adv7123_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&extal_clk {
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
&hsusb {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
composite-in@20 {
|
||||
compatible = "adi,adv7180cp";
|
||||
reg = <0x20>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7180_in: endpoint {
|
||||
remote-endpoint = <&composite_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
|
||||
/*
|
||||
* The VIN4 video input path is shared between
|
||||
* CVBS and HDMI inputs through SW[49-53]
|
||||
* switches.
|
||||
*
|
||||
* CVBS is the default selection, link it to
|
||||
* VIN4 here.
|
||||
*/
|
||||
adv7180_out: endpoint {
|
||||
remote-endpoint = <&vin4_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
hdmi-encoder@39 {
|
||||
compatible = "adi,adv7511w";
|
||||
reg = <0x39>, <0x3f>, <0x38>, <0x3c>;
|
||||
reg-names = "main", "edid", "packet", "cec";
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
/* Depends on LVDS */
|
||||
max-clock = <135000000>;
|
||||
min-vrefresh = <50>;
|
||||
|
||||
adi,input-depth = <8>;
|
||||
adi,input-colorspace = "rgb";
|
||||
adi,input-clock = "1x";
|
||||
adi,input-style = <1>;
|
||||
adi,input-justification = "evenly";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7511_in: endpoint {
|
||||
remote-endpoint = <&thc63lvd1024_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
adv7511_out: endpoint {
|
||||
remote-endpoint = <&hdmi_con_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-decoder@4c {
|
||||
compatible = "adi,adv7612";
|
||||
reg = <0x4c>;
|
||||
default-input = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
adv7612_in: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
/*
|
||||
* The VIN4 video input path is shared between
|
||||
* CVBS and HDMI inputs through SW[49-53]
|
||||
* switches.
|
||||
*
|
||||
* CVBS is the default selection, leave HDMI
|
||||
* not connected here.
|
||||
*/
|
||||
adv7612_out: endpoint {
|
||||
pclk-sample = <0>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "rohm,br24t01", "atmel,24c01";
|
||||
reg = <0x50>;
|
||||
pagesize = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lvds0 {
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 727>,
|
||||
<&x12_clk>,
|
||||
<&extal_clk>;
|
||||
clock-names = "fck", "dclkin.0", "extal";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
lvds0_out: endpoint {
|
||||
remote-endpoint = <&thc63lvd1024_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lvds1 {
|
||||
clocks = <&cpg CPG_MOD 727>,
|
||||
<&x12_clk>,
|
||||
<&extal_clk>;
|
||||
clock-names = "fck", "dclkin.0", "extal";
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pfc {
|
||||
avb0_pins: avb {
|
||||
mux {
|
||||
@ -173,136 +428,23 @@
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
&pwm0 {
|
||||
pinctrl-0 = <&pwm0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "rohm,br24t01", "atmel,24c01";
|
||||
reg = <0x50>;
|
||||
pagesize = <8>;
|
||||
};
|
||||
|
||||
composite-in@20 {
|
||||
compatible = "adi,adv7180cp";
|
||||
reg = <0x20>;
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
adv7180_in: endpoint {
|
||||
remote-endpoint = <&composite_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
|
||||
/*
|
||||
* The VIN4 video input path is shared between
|
||||
* CVBS and HDMI inputs through SW[49-53]
|
||||
* switches.
|
||||
*
|
||||
* CVBS is the default selection, link it to
|
||||
* VIN4 here.
|
||||
*/
|
||||
adv7180_out: endpoint {
|
||||
remote-endpoint = <&vin4_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
hdmi-decoder@4c {
|
||||
compatible = "adi,adv7612";
|
||||
reg = <0x4c>;
|
||||
default-input = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
adv7612_in: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
/*
|
||||
* The VIN4 video input path is shared between
|
||||
* CVBS and HDMI inputs through SW[49-53]
|
||||
* switches.
|
||||
*
|
||||
* CVBS is the default selection, leave HDMI
|
||||
* not connected here.
|
||||
*/
|
||||
adv7612_out: endpoint {
|
||||
pclk-sample = <0>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
&pwm1 {
|
||||
pinctrl-0 = <&pwm1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&du {
|
||||
pinctrl-0 = <&du_pins>;
|
||||
pinctrl-names = "default";
|
||||
&rwdt {
|
||||
timeout-sec = <60>;
|
||||
status = "okay";
|
||||
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>,
|
||||
<&x12_clk>;
|
||||
clock-names = "du.0", "du.1", "dclkin.0";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
endpoint {
|
||||
remote-endpoint = <&adv7123_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&avb {
|
||||
pinctrl-0 = <&avb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
renesas,no-ether-link;
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-txid";
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
rxc-skew-ps = <1500>;
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio5>;
|
||||
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&scif2 {
|
||||
@ -330,25 +472,7 @@
|
||||
pinctrl-0 = <&usb0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
pinctrl-0 = <&pwm0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
pinctrl-0 = <&pwm1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rwdt {
|
||||
timeout-sec = <60>;
|
||||
renesas,no-otg-pins;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
@ -7,12 +7,14 @@
|
||||
|
||||
#include "r8a779x-u-boot.dtsi"
|
||||
|
||||
&soc {
|
||||
rpc: rpc@0xee200000 {
|
||||
compatible = "renesas,rpc-r8a77995", "renesas,rpc";
|
||||
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
bank-width = <2>;
|
||||
status = "disabled";
|
||||
/ {
|
||||
soc {
|
||||
rpc: rpc@0xee200000 {
|
||||
compatible = "renesas,rpc-r8a77995", "renesas,rpc";
|
||||
reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
bank-width = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for the r8a77995 SoC
|
||||
* Device Tree Source for the R-Car D3 (R8A77995) SoC
|
||||
*
|
||||
* Copyright (C) 2016 Renesas Electronics Corp.
|
||||
* Copyright (C) 2017 Glider bvba
|
||||
@ -27,7 +27,7 @@
|
||||
#size-cells = <0>;
|
||||
|
||||
a53_0: cpu@0 {
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0>;
|
||||
device_type = "cpu";
|
||||
power-domains = <&sysc R8A77995_PD_CA53_CPU0>;
|
||||
@ -66,7 +66,7 @@
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
@ -344,6 +344,51 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hsusb: usb@e6590000 {
|
||||
compatible = "renesas,usbhs-r8a77995",
|
||||
"renesas,rcar-gen3-usbhs";
|
||||
reg = <0 0xe6590000 0 0x200>;
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
|
||||
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
|
||||
<&usb_dmac1 0>, <&usb_dmac1 1>;
|
||||
dma-names = "ch0", "ch1", "ch2", "ch3";
|
||||
renesas,buswait = <11>;
|
||||
phys = <&usb2_phy0>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 704>, <&cpg 703>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_dmac0: dma-controller@e65a0000 {
|
||||
compatible = "renesas,r8a77995-usb-dmac",
|
||||
"renesas,usb-dmac";
|
||||
reg = <0 0xe65a0000 0 0x100>;
|
||||
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1";
|
||||
clocks = <&cpg CPG_MOD 330>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 330>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <2>;
|
||||
};
|
||||
|
||||
usb_dmac1: dma-controller@e65b0000 {
|
||||
compatible = "renesas,r8a77995-usb-dmac",
|
||||
"renesas,usb-dmac";
|
||||
reg = <0 0xe65b0000 0 0x100>;
|
||||
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ch0", "ch1";
|
||||
clocks = <&cpg CPG_MOD 331>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 331>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <2>;
|
||||
};
|
||||
|
||||
canfd: can@e66c0000 {
|
||||
compatible = "renesas,r8a77995-canfd",
|
||||
"renesas,rcar-gen3-canfd";
|
||||
@ -391,6 +436,10 @@
|
||||
resets = <&cpg 219>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <8>;
|
||||
iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
|
||||
<&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
|
||||
<&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
|
||||
<&ipmmu_ds0 6>, <&ipmmu_ds0 7>;
|
||||
};
|
||||
|
||||
dmac1: dma-controller@e7300000 {
|
||||
@ -415,6 +464,10 @@
|
||||
resets = <&cpg 218>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <8>;
|
||||
iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
|
||||
<&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
|
||||
<&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
|
||||
<&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
|
||||
};
|
||||
|
||||
dmac2: dma-controller@e7310000 {
|
||||
@ -439,6 +492,10 @@
|
||||
resets = <&cpg 217>;
|
||||
#dma-cells = <1>;
|
||||
dma-channels = <8>;
|
||||
iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
|
||||
<&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
|
||||
<&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
|
||||
<&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
|
||||
};
|
||||
|
||||
ipmmu_ds0: mmu@e6740000 {
|
||||
@ -817,11 +874,11 @@
|
||||
compatible = "generic-ohci";
|
||||
reg = <0 0xee080000 0 0x100>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 703>;
|
||||
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
|
||||
phys = <&usb2_phy0>;
|
||||
phy-names = "usb";
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 703>;
|
||||
resets = <&cpg 703>, <&cpg 704>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -829,12 +886,12 @@
|
||||
compatible = "generic-ehci";
|
||||
reg = <0 0xee080100 0 0x100>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 703>;
|
||||
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
|
||||
phys = <&usb2_phy0>;
|
||||
phy-names = "usb";
|
||||
companion = <&ohci0>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 703>;
|
||||
resets = <&cpg 703>, <&cpg 704>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -843,9 +900,9 @@
|
||||
"renesas,rcar-gen3-usb2-phy";
|
||||
reg = <0 0xee080200 0 0x700>;
|
||||
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 703>;
|
||||
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 703>;
|
||||
resets = <&cpg 703>, <&cpg 704>;
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -960,12 +1017,68 @@
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
du_out_lvds0: endpoint {
|
||||
remote-endpoint = <&lvds0_in>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
du_out_lvds1: endpoint {
|
||||
remote-endpoint = <&lvds1_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lvds0: lvds-encoder@feb90000 {
|
||||
compatible = "renesas,r8a77995-lvds";
|
||||
reg = <0 0xfeb90000 0 0x20>;
|
||||
clocks = <&cpg CPG_MOD 727>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 727>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
lvds0_in: endpoint {
|
||||
remote-endpoint = <&du_out_lvds0>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
lvds0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lvds1: lvds-encoder@feb90100 {
|
||||
compatible = "renesas,r8a77995-lvds";
|
||||
reg = <0 0xfeb90100 0 0x20>;
|
||||
clocks = <&cpg CPG_MOD 727>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 726>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
lvds1_in: endpoint {
|
||||
remote-endpoint = <&du_out_lvds1>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
lvds1_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -420,7 +420,10 @@
|
||||
|
||||
video-receiver@70 {
|
||||
compatible = "adi,adv7482";
|
||||
reg = <0x70>;
|
||||
reg = <0x70 0x71 0x72 0x73 0x74 0x75
|
||||
0x60 0x61 0x62 0x63 0x64 0x65>;
|
||||
reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
|
||||
"infoframe", "cbus", "cec", "sdp", "txa", "txb" ;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -471,6 +474,8 @@
|
||||
&i2c_dvfs {
|
||||
status = "okay";
|
||||
|
||||
clock-frequency = <400000>;
|
||||
|
||||
pmic: pmic@30 {
|
||||
pinctrl-0 = <&irq0_pins>;
|
||||
pinctrl-names = "default";
|
||||
@ -600,12 +605,6 @@
|
||||
};
|
||||
|
||||
sdhi2_pins: sd2 {
|
||||
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
|
||||
function = "sdhi2";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi2_pins_uhs: sd2_uhs {
|
||||
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
|
||||
function = "sdhi2";
|
||||
power-source = <1800>;
|
||||
@ -702,7 +701,10 @@
|
||||
<&cpg CPG_CORE CPG_AUDIO_CLK_I>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
rsnd_port0: port@0 {
|
||||
reg = <0>;
|
||||
rsnd_endpoint0: endpoint {
|
||||
remote-endpoint = <&ak4613_endpoint>;
|
||||
|
||||
@ -748,19 +750,21 @@
|
||||
wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
|
||||
bus-width = <4>;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi2 {
|
||||
/* used for on-board 8bit eMMC */
|
||||
pinctrl-0 = <&sdhi2_pins>;
|
||||
pinctrl-1 = <&sdhi2_pins_uhs>;
|
||||
pinctrl-1 = <&sdhi2_pins>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <®_3p3v>;
|
||||
vqmmc-supply = <®_1p8v>;
|
||||
bus-width = <8>;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
non-removable;
|
||||
fixed-emmc-driver-type = <1>;
|
||||
status = "okay";
|
||||
@ -777,6 +781,7 @@
|
||||
wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
|
||||
bus-width = <4>;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -807,6 +812,8 @@
|
||||
phys = <&usb3_phy0>;
|
||||
phy-names = "usb";
|
||||
|
||||
companion = <&xhci0>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
@ -6,6 +6,14 @@
|
||||
* Copyright (C) 2016 Cogent Embedded, Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* SSI-AK4613
|
||||
* aplay -D plughw:0,0 xxx.wav
|
||||
* arecord -D plughw:0,0 xxx.wav
|
||||
* SSI-HDMI
|
||||
* aplay -D plughw:0,1 xxx.wav
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
@ -18,6 +26,7 @@
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
@ -82,20 +91,13 @@
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
rsnd_ak4613: sound {
|
||||
compatible = "simple-audio-card";
|
||||
sound_card: sound {
|
||||
compatible = "audio-graph-card";
|
||||
label = "rcar-sound";
|
||||
|
||||
simple-audio-card,format = "left_j";
|
||||
simple-audio-card,bitclock-master = <&sndcpu>;
|
||||
simple-audio-card,frame-master = <&sndcpu>;
|
||||
|
||||
sndcpu: simple-audio-card,cpu {
|
||||
sound-dai = <&rcar_sound>;
|
||||
};
|
||||
|
||||
sndcodec: simple-audio-card,codec {
|
||||
sound-dai = <&ak4613>;
|
||||
};
|
||||
dais = <&rsnd_port0 /* ak4613 */
|
||||
&rsnd_port1 /* HDMI0 */
|
||||
>;
|
||||
};
|
||||
|
||||
vcc_sdhi0: regulator-vcc-sdhi0 {
|
||||
@ -181,6 +183,12 @@
|
||||
remote-endpoint = <&hdmi0_con>;
|
||||
};
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
dw_hdmi0_snd_in: endpoint {
|
||||
remote-endpoint = <&rsnd_for_hdmi>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -210,6 +218,12 @@
|
||||
asahi-kasei,out4-single-end;
|
||||
asahi-kasei,out5-single-end;
|
||||
asahi-kasei,out6-single-end;
|
||||
|
||||
port {
|
||||
ak4613_endpoint: endpoint {
|
||||
remote-endpoint = <&rsnd_for_ak4613>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cs2000: clk-multiplier@4f {
|
||||
@ -241,6 +255,8 @@
|
||||
&i2c_dvfs {
|
||||
status = "okay";
|
||||
|
||||
clock-frequency = <400000>;
|
||||
|
||||
pmic: pmic@30 {
|
||||
pinctrl-0 = <&irq0_pins>;
|
||||
pinctrl-names = "default";
|
||||
@ -327,12 +343,6 @@
|
||||
};
|
||||
|
||||
sdhi2_pins: sd2 {
|
||||
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
|
||||
function = "sdhi2";
|
||||
power-source = <3300>;
|
||||
};
|
||||
|
||||
sdhi2_pins_uhs: sd2_uhs {
|
||||
groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds";
|
||||
function = "sdhi2";
|
||||
power-source = <1800>;
|
||||
@ -387,10 +397,33 @@
|
||||
<&audio_clk_c>,
|
||||
<&cpg CPG_CORE CPG_AUDIO_CLK_I>;
|
||||
|
||||
rcar_sound,dai {
|
||||
dai0 {
|
||||
playback = <&ssi0 &src0 &dvc0>;
|
||||
capture = <&ssi1 &src1 &dvc1>;
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
rsnd_port0: port@0 {
|
||||
reg = <0>;
|
||||
rsnd_for_ak4613: endpoint {
|
||||
remote-endpoint = <&ak4613_endpoint>;
|
||||
|
||||
dai-format = "left_j";
|
||||
bitclock-master = <&rsnd_for_ak4613>;
|
||||
frame-master = <&rsnd_for_ak4613>;
|
||||
|
||||
playback = <&ssi0 &src0 &dvc0>;
|
||||
capture = <&ssi1 &src1 &dvc1>;
|
||||
};
|
||||
};
|
||||
rsnd_port1: port@1 {
|
||||
reg = <1>;
|
||||
rsnd_for_hdmi: endpoint {
|
||||
remote-endpoint = <&dw_hdmi0_snd_in>;
|
||||
|
||||
dai-format = "i2s";
|
||||
bitclock-master = <&rsnd_for_hdmi>;
|
||||
frame-master = <&rsnd_for_hdmi>;
|
||||
|
||||
playback = <&ssi2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -416,19 +449,21 @@
|
||||
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
|
||||
bus-width = <4>;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi2 {
|
||||
/* used for on-board 8bit eMMC */
|
||||
pinctrl-0 = <&sdhi2_pins>;
|
||||
pinctrl-1 = <&sdhi2_pins_uhs>;
|
||||
pinctrl-1 = <&sdhi2_pins>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
|
||||
vmmc-supply = <®_3p3v>;
|
||||
vqmmc-supply = <®_1p8v>;
|
||||
bus-width = <8>;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -12,6 +12,11 @@ config R8A7796
|
||||
imply CLK_R8A7796
|
||||
imply PINCTRL_PFC_R8A7796
|
||||
|
||||
config R8A77965
|
||||
bool "Renesas SoC R8A77965"
|
||||
imply CLK_R8A77965
|
||||
imply PINCTRL_PFC_R8A77965
|
||||
|
||||
config R8A77970
|
||||
bool "Renesas SoC R8A77970"
|
||||
imply CLK_R8A77970
|
||||
@ -55,6 +60,10 @@ config TARGET_SALVATOR_X
|
||||
bool "Salvator-X board"
|
||||
imply R8A7795
|
||||
imply R8A7796
|
||||
imply R8A77965
|
||||
imply SYS_MALLOC_F
|
||||
imply MULTI_DTB_FIT
|
||||
imply MULTI_DTB_FIT_USER_DEFINED_AREA
|
||||
help
|
||||
Support for Renesas R-Car Gen3 platform
|
||||
|
||||
@ -62,6 +71,10 @@ config TARGET_ULCB
|
||||
bool "ULCB board"
|
||||
imply R8A7795
|
||||
imply R8A7796
|
||||
imply R8A77965
|
||||
imply SYS_MALLOC_F
|
||||
imply MULTI_DTB_FIT
|
||||
imply MULTI_DTB_FIT_USER_DEFINED_AREA
|
||||
help
|
||||
Support for Renesas R-Car Gen3 ULCB platform
|
||||
|
||||
@ -76,4 +89,15 @@ source "board/renesas/ebisu/Kconfig"
|
||||
source "board/renesas/salvator-x/Kconfig"
|
||||
source "board/renesas/ulcb/Kconfig"
|
||||
|
||||
config MULTI_DTB_FIT_UNCOMPRESS_SZ
|
||||
default 0x80000 if TARGET_SALVATOR_X
|
||||
default 0x80000 if TARGET_ULCB
|
||||
|
||||
config MULTI_DTB_FIT_USER_DEF_ADDR
|
||||
default 0x49000000 if TARGET_SALVATOR_X
|
||||
default 0x49000000 if TARGET_ULCB
|
||||
|
||||
config SYS_MALLOC_F_LEN
|
||||
default 0x8000 if RCAR_GEN3
|
||||
|
||||
endif
|
||||
|
||||
@ -16,6 +16,21 @@
|
||||
#include <linux/linkage.h>
|
||||
#include <asm/macro.h>
|
||||
|
||||
.align 8
|
||||
.globl rcar_atf_boot_args
|
||||
rcar_atf_boot_args:
|
||||
.dword 0
|
||||
.dword 0
|
||||
.dword 0
|
||||
.dword 0
|
||||
|
||||
ENTRY(save_boot_params)
|
||||
adr x8, rcar_atf_boot_args
|
||||
stp x0, x1, [x8], #16
|
||||
stp x2, x3, [x8], #16
|
||||
b save_boot_params_ret
|
||||
ENDPROC(save_boot_params)
|
||||
|
||||
ENTRY(lowlevel_init)
|
||||
mov x29, lr /* Save LR */
|
||||
|
||||
|
||||
@ -8,57 +8,4 @@
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/rmobile.h>
|
||||
#include <asm/arch/rcar-mstp.h>
|
||||
|
||||
#define TSTR0 0x04
|
||||
#define TSTR0_STR0 0x01
|
||||
|
||||
static struct mstp_ctl mstptbl[] = {
|
||||
{ SMSTPCR0, MSTP0_BITS, CONFIG_SMSTP0_ENA,
|
||||
RMSTPCR0, MSTP0_BITS, CONFIG_RMSTP0_ENA },
|
||||
{ SMSTPCR1, MSTP1_BITS, CONFIG_SMSTP1_ENA,
|
||||
RMSTPCR1, MSTP1_BITS, CONFIG_RMSTP1_ENA },
|
||||
{ SMSTPCR2, MSTP2_BITS, CONFIG_SMSTP2_ENA,
|
||||
RMSTPCR2, MSTP2_BITS, CONFIG_RMSTP2_ENA },
|
||||
{ SMSTPCR3, MSTP3_BITS, CONFIG_SMSTP3_ENA,
|
||||
RMSTPCR3, MSTP3_BITS, CONFIG_RMSTP3_ENA },
|
||||
{ SMSTPCR4, MSTP4_BITS, CONFIG_SMSTP4_ENA,
|
||||
RMSTPCR4, MSTP4_BITS, CONFIG_RMSTP4_ENA },
|
||||
{ SMSTPCR5, MSTP5_BITS, CONFIG_SMSTP5_ENA,
|
||||
RMSTPCR5, MSTP5_BITS, CONFIG_RMSTP5_ENA },
|
||||
#ifdef CONFIG_RCAR_GEN3
|
||||
{ SMSTPCR6, MSTP6_BITS, CONFIG_SMSTP6_ENA,
|
||||
RMSTPCR6, MSTP6_BITS, CONFIG_RMSTP6_ENA },
|
||||
#endif
|
||||
{ SMSTPCR7, MSTP7_BITS, CONFIG_SMSTP7_ENA,
|
||||
RMSTPCR7, MSTP7_BITS, CONFIG_RMSTP7_ENA },
|
||||
{ SMSTPCR8, MSTP8_BITS, CONFIG_SMSTP8_ENA,
|
||||
RMSTPCR8, MSTP8_BITS, CONFIG_RMSTP8_ENA },
|
||||
{ SMSTPCR9, MSTP9_BITS, CONFIG_SMSTP9_ENA,
|
||||
RMSTPCR9, MSTP9_BITS, CONFIG_RMSTP9_ENA },
|
||||
{ SMSTPCR10, MSTP10_BITS, CONFIG_SMSTP10_ENA,
|
||||
RMSTPCR10, MSTP10_BITS, CONFIG_RMSTP10_ENA },
|
||||
{ SMSTPCR11, MSTP11_BITS, CONFIG_SMSTP1_ENA,
|
||||
RMSTPCR11, MSTP11_BITS, CONFIG_RMSTP11_ENA },
|
||||
};
|
||||
|
||||
void arch_preboot_os(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* stop TMU0 */
|
||||
mstp_clrbits_le32(TMU_BASE + TSTR0, TMU_BASE + TSTR0, TSTR0_STR0);
|
||||
|
||||
/* Stop module clock */
|
||||
for (i = 0; i < ARRAY_SIZE(mstptbl); i++) {
|
||||
mstp_setclrbits_le32((uintptr_t)mstptbl[i].s_addr,
|
||||
mstptbl[i].s_dis,
|
||||
mstptbl[i].s_ena);
|
||||
mstp_setclrbits_le32((uintptr_t)mstptbl[i].r_addr,
|
||||
mstptbl[i].r_dis,
|
||||
mstptbl[i].r_ena);
|
||||
}
|
||||
}
|
||||
|
||||
@ -5,3 +5,4 @@ F: board/renesas/ulcb/
|
||||
F: include/configs/ulcb.h
|
||||
F: configs/r8a7795_ulcb_defconfig
|
||||
F: configs/r8a7796_ulcb_defconfig
|
||||
F: configs/r8a77965_ulcb_defconfig
|
||||
|
||||
@ -97,6 +97,10 @@ int board_fit_config_name_match(const char *name)
|
||||
!strcmp(name, "r8a7796-m3ulcb-u-boot"))
|
||||
return 0;
|
||||
|
||||
if ((cpu_type == RMOBILE_CPU_TYPE_R8A77965) &&
|
||||
!strcmp(name, "r8a77965-m3nulcb-u-boot"))
|
||||
return 0;
|
||||
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -75,7 +75,7 @@ static int spl_ymodem_load_image(struct spl_image_info *spl_image,
|
||||
int ret;
|
||||
connection_info_t info;
|
||||
char buf[BUF_SIZE];
|
||||
struct image_header *ih;
|
||||
struct image_header *ih = NULL;
|
||||
ulong addr = 0;
|
||||
|
||||
info.mode = xyzModem_ymodem;
|
||||
@ -111,7 +111,7 @@ static int spl_ymodem_load_image(struct spl_image_info *spl_image,
|
||||
ih = (struct image_header *)buf;
|
||||
ret = spl_parse_image_header(spl_image, ih);
|
||||
if (ret)
|
||||
return ret;
|
||||
goto end_stream;
|
||||
#ifdef CONFIG_SPL_GZIP
|
||||
if (ih->ih_comp == IH_COMP_GZIP)
|
||||
addr = CONFIG_SYS_LOAD_ADDR;
|
||||
@ -128,18 +128,6 @@ static int spl_ymodem_load_image(struct spl_image_info *spl_image,
|
||||
size += res;
|
||||
addr += res;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPL_GZIP
|
||||
if (ih->ih_comp == IH_COMP_GZIP) {
|
||||
if (gunzip((void *)(spl_image->load_addr + sizeof(*ih)),
|
||||
CONFIG_SYS_BOOTM_LEN,
|
||||
(void *)(CONFIG_SYS_LOAD_ADDR + sizeof(*ih)),
|
||||
&size)) {
|
||||
puts("Uncompressing error\n");
|
||||
return -EIO;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
end_stream:
|
||||
@ -147,6 +135,21 @@ end_stream:
|
||||
xyzModem_stream_terminate(false, &getcymodem);
|
||||
|
||||
printf("Loaded %lu bytes\n", size);
|
||||
return 0;
|
||||
|
||||
#ifdef CONFIG_SPL_GZIP
|
||||
if (!(IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
|
||||
image_get_magic((struct image_header *)buf) == FDT_MAGIC) &&
|
||||
(ih->ih_comp == IH_COMP_GZIP)) {
|
||||
if (gunzip((void *)(spl_image->load_addr + sizeof(*ih)),
|
||||
CONFIG_SYS_BOOTM_LEN,
|
||||
(void *)(CONFIG_SYS_LOAD_ADDR + sizeof(*ih)),
|
||||
&size)) {
|
||||
puts("Uncompressing error\n");
|
||||
return -EIO;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
SPL_LOAD_IMAGE_METHOD("UART", 0, BOOT_DEVICE_UART, spl_ymodem_load_image);
|
||||
|
||||
@ -1,7 +1,6 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_RMOBILE=y
|
||||
CONFIG_SYS_TEXT_BASE=0x50000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_RCAR_GEN3=y
|
||||
CONFIG_TARGET_SALVATOR_X=y
|
||||
CONFIG_SMBIOS_PRODUCT_NAME=""
|
||||
@ -29,7 +28,8 @@ CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a7795-salvator-x-u-boot"
|
||||
CONFIG_OF_LIST="r8a7795-salvator-x-u-boot r8a7796-salvator-x-u-boot r8a77965-salvator-x-u-boot"
|
||||
CONFIG_MULTI_DTB_FIT=y
|
||||
CONFIG_MULTI_DTB_FIT_LZO=y
|
||||
CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
|
||||
@ -28,8 +28,9 @@ CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a7795-h3ulcb-u-boot"
|
||||
CONFIG_OF_LIST="r8a7795-h3ulcb-u-boot r8a7796-m3ulcb-u-boot"
|
||||
CONFIG_MULTI_DTB_FIT=y
|
||||
CONFIG_OF_LIST="r8a7795-h3ulcb-u-boot r8a7796-m3ulcb-u-boot r8a77965-m3nulcb-u-boot"
|
||||
CONFIG_MULTI_DTB_FIT_LZO=y
|
||||
CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
|
||||
@ -29,7 +29,8 @@ CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a77965-salvator-x-u-boot"
|
||||
CONFIG_OF_LIST="r8a7795-salvator-x-u-boot r8a7796-salvator-x-u-boot r8a77965-salvator-x-u-boot"
|
||||
CONFIG_MULTI_DTB_FIT=y
|
||||
CONFIG_MULTI_DTB_FIT_LZO=y
|
||||
CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
|
||||
67
configs/r8a77965_ulcb_defconfig
Normal file
67
configs/r8a77965_ulcb_defconfig
Normal file
@ -0,0 +1,67 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_RMOBILE=y
|
||||
CONFIG_SYS_TEXT_BASE=0x50000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_RCAR_GEN3=y
|
||||
CONFIG_TARGET_ULCB=y
|
||||
CONFIG_SMBIOS_PRODUCT_NAME=""
|
||||
CONFIG_FIT=y
|
||||
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
|
||||
CONFIG_SUPPORT_RAW_INITRD=y
|
||||
CONFIG_DEFAULT_FDT_FILE="r8a77965-m3nulcb.dtb"
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a77965-m3nulcb-u-boot"
|
||||
CONFIG_OF_LIST="r8a7795-h3ulcb-u-boot r8a7796-m3ulcb-u-boot r8a77965-m3nulcb-u-boot"
|
||||
CONFIG_MULTI_DTB_FIT_LZO=y
|
||||
CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_CLK_RENESAS=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_RCAR_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_RCAR_IIC=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS400_SUPPORT=y
|
||||
CONFIG_RENESAS_SDHI=y
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ90X1=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_RENESAS_RAVB=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCONF=y
|
||||
CONFIG_PINCTRL_PFC=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_SCIF_CONSOLE=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_SMBIOS_MANUFACTURER=""
|
||||
@ -29,7 +29,8 @@ CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a7796-salvator-x-u-boot"
|
||||
CONFIG_OF_LIST="r8a7795-salvator-x-u-boot r8a7796-salvator-x-u-boot r8a77965-salvator-x-u-boot"
|
||||
CONFIG_MULTI_DTB_FIT=y
|
||||
CONFIG_MULTI_DTB_FIT_LZO=y
|
||||
CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
|
||||
@ -28,8 +28,9 @@ CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a7796-m3ulcb-u-boot"
|
||||
CONFIG_OF_LIST="r8a7795-h3ulcb-u-boot r8a7796-m3ulcb-u-boot"
|
||||
CONFIG_MULTI_DTB_FIT=y
|
||||
CONFIG_OF_LIST="r8a7795-h3ulcb-u-boot r8a7796-m3ulcb-u-boot r8a77965-m3nulcb-u-boot"
|
||||
CONFIG_MULTI_DTB_FIT_LZO=y
|
||||
CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
|
||||
@ -32,6 +32,7 @@ Currently the following boards are supported:
|
||||
| R8A7796 M3-W | Renesas Electronics ULCB | r8a7796_ulcb
|
||||
|---------------+----------------------------------------+-------------------
|
||||
| R8A77965 M3-N | Renesas Electronics Salvator-XS | r8a77965_salvator-x_defconfig
|
||||
| R8A77965 M3-N | Renesas Electronics ULCB | r8a77965_ulcb
|
||||
|---------------+----------------------------------------+-------------------
|
||||
| R8A77970 V3M | Renesas Electronics Eagle | r8a77970_eagle_defconfig
|
||||
|---------------+----------------------------------------+-------------------
|
||||
|
||||
@ -60,6 +60,12 @@ config CLK_R8A7796
|
||||
help
|
||||
Enable this to support the clocks on Renesas R8A7796 SoC.
|
||||
|
||||
config CLK_R8A77965
|
||||
bool "Renesas R8A77965 clock driver"
|
||||
depends on CLK_RCAR_GEN3
|
||||
help
|
||||
Enable this to support the clocks on Renesas R8A77965 SoC.
|
||||
|
||||
config CLK_R8A77970
|
||||
bool "Renesas R8A77970 clock driver"
|
||||
depends on CLK_RCAR_GEN3
|
||||
|
||||
@ -8,6 +8,7 @@ obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_RCAR_GEN3) += clk-rcar-gen3.o
|
||||
obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A77965) += r8a77965-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
|
||||
|
||||
@ -96,7 +96,7 @@ static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk,
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (core->type == CLK_TYPE_GEN3_PE) {
|
||||
if (core->type == CLK_TYPE_GEN3_MDSEL) {
|
||||
parent->dev = clk->dev;
|
||||
parent->id = core->parent >> (priv->sscg ? 16 : 0);
|
||||
parent->id &= 0xffff;
|
||||
@ -257,7 +257,7 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
|
||||
core->parent, core->mult, core->div, rate);
|
||||
return rate;
|
||||
|
||||
case CLK_TYPE_GEN3_PE:
|
||||
case CLK_TYPE_GEN3_MDSEL:
|
||||
div = (core->div >> (priv->sscg ? 16 : 0)) & 0xffff;
|
||||
rate = gen3_clk_get_rate64(&parent) / div;
|
||||
debug("%s[%i] PE clk: parent=%i div=%u => rate=%llu\n",
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* r8a7790 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
@ -6,10 +7,6 @@
|
||||
* Based on clk-rcar-gen2.c
|
||||
*
|
||||
* Copyright (C) 2013 Ideas On Board SPRL
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
@ -139,6 +136,7 @@ static const struct mssr_mod_clk r8a7790_mod_clks[] = {
|
||||
DEF_MOD("cmt1", 329, R8A7790_CLK_R),
|
||||
DEF_MOD("usbhs-dmac0", 330, R8A7790_CLK_HP),
|
||||
DEF_MOD("usbhs-dmac1", 331, R8A7790_CLK_HP),
|
||||
DEF_MOD("rwdt", 402, R8A7790_CLK_R),
|
||||
DEF_MOD("irqc", 407, R8A7790_CLK_CP),
|
||||
DEF_MOD("intc-sys", 408, R8A7790_CLK_ZS),
|
||||
DEF_MOD("audio-dmac1", 501, R8A7790_CLK_HP),
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Renesas R8A7791 CPG MSSR driver
|
||||
*
|
||||
@ -6,8 +6,11 @@
|
||||
*
|
||||
* Based on the following driver from Linux kernel:
|
||||
* r8a7791 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2015-2017 Glider bvba
|
||||
*
|
||||
* Based on clk-rcar-gen2.c
|
||||
*
|
||||
* Copyright (C) 2013 Ideas On Board SPRL
|
||||
*/
|
||||
|
||||
@ -54,7 +57,6 @@ static const struct cpg_core_clk r8a7791_core_clks[] = {
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_BASE("z", R8A7791_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0),
|
||||
DEF_BASE("lb", R8A7791_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
|
||||
DEF_BASE("adsp", R8A7791_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
|
||||
DEF_BASE("sdh", R8A7791_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
|
||||
DEF_BASE("sd0", R8A7791_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
|
||||
@ -67,6 +69,7 @@ static const struct cpg_core_clk r8a7791_core_clks[] = {
|
||||
DEF_FIXED("hp", R8A7791_CLK_HP, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("i", R8A7791_CLK_I, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED("b", R8A7791_CLK_B, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("lb", R8A7791_CLK_LB, CLK_PLL1, 24, 1),
|
||||
DEF_FIXED("p", R8A7791_CLK_P, CLK_PLL1, 24, 1),
|
||||
DEF_FIXED("cl", R8A7791_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("m2", R8A7791_CLK_M2, CLK_PLL1, 8, 1),
|
||||
@ -125,6 +128,7 @@ static const struct mssr_mod_clk r8a7791_mod_clks[] = {
|
||||
DEF_MOD("cmt1", 329, R8A7791_CLK_R),
|
||||
DEF_MOD("usbhs-dmac0", 330, R8A7791_CLK_HP),
|
||||
DEF_MOD("usbhs-dmac1", 331, R8A7791_CLK_HP),
|
||||
DEF_MOD("rwdt", 402, R8A7791_CLK_R),
|
||||
DEF_MOD("irqc", 407, R8A7791_CLK_CP),
|
||||
DEF_MOD("intc-sys", 408, R8A7791_CLK_ZS),
|
||||
DEF_MOD("audio-dmac1", 501, R8A7791_CLK_HP),
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* r8a7792 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
@ -6,10 +7,6 @@
|
||||
* Based on clk-rcar-gen2.c
|
||||
*
|
||||
* Copyright (C) 2013 Ideas On Board SPRL
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
@ -52,7 +49,6 @@ static const struct cpg_core_clk r8a7792_core_clks[] = {
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_BASE("lb", R8A7792_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
|
||||
DEF_BASE("qspi", R8A7792_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
|
||||
|
||||
DEF_FIXED("z", R8A7792_CLK_Z, CLK_PLL0, 1, 1),
|
||||
@ -62,6 +58,7 @@ static const struct cpg_core_clk r8a7792_core_clks[] = {
|
||||
DEF_FIXED("hp", R8A7792_CLK_HP, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("i", R8A7792_CLK_I, CLK_PLL1, 3, 1),
|
||||
DEF_FIXED("b", R8A7792_CLK_B, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("lb", R8A7792_CLK_LB, CLK_PLL1, 24, 1),
|
||||
DEF_FIXED("p", R8A7792_CLK_P, CLK_PLL1, 24, 1),
|
||||
DEF_FIXED("cl", R8A7792_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("m2", R8A7792_CLK_M2, CLK_PLL1, 8, 1),
|
||||
@ -97,6 +94,7 @@ static const struct mssr_mod_clk r8a7792_mod_clks[] = {
|
||||
DEF_MOD("tpu0", 304, R8A7792_CLK_CP),
|
||||
DEF_MOD("sdhi0", 314, R8A7792_CLK_SD),
|
||||
DEF_MOD("cmt1", 329, R8A7792_CLK_R),
|
||||
DEF_MOD("rwdt", 402, R8A7792_CLK_R),
|
||||
DEF_MOD("irqc", 407, R8A7792_CLK_CP),
|
||||
DEF_MOD("intc-sys", 408, R8A7792_CLK_ZS),
|
||||
DEF_MOD("audio-dmac0", 502, R8A7792_CLK_HP),
|
||||
|
||||
@ -1,3 +1,4 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* r8a7794 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
@ -6,10 +7,6 @@
|
||||
* Based on clk-rcar-gen2.c
|
||||
*
|
||||
* Copyright (C) 2013 Ideas On Board SPRL
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
@ -54,7 +51,6 @@ static const struct cpg_core_clk r8a7794_core_clks[] = {
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_BASE("lb", R8A7794_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
|
||||
DEF_BASE("adsp", R8A7794_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
|
||||
DEF_BASE("sdh", R8A7794_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
|
||||
DEF_BASE("sd0", R8A7794_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
|
||||
@ -68,6 +64,7 @@ static const struct cpg_core_clk r8a7794_core_clks[] = {
|
||||
DEF_FIXED("hp", R8A7794_CLK_HP, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("i", R8A7794_CLK_I, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED("b", R8A7794_CLK_B, CLK_PLL1, 12, 1),
|
||||
DEF_FIXED("lb", R8A7794_CLK_LB, CLK_PLL1, 24, 1),
|
||||
DEF_FIXED("p", R8A7794_CLK_P, CLK_PLL1, 24, 1),
|
||||
DEF_FIXED("cl", R8A7794_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("cp", R8A7794_CLK_CP, CLK_PLL1, 48, 1),
|
||||
@ -120,6 +117,7 @@ static const struct mssr_mod_clk r8a7794_mod_clks[] = {
|
||||
DEF_MOD("cmt1", 329, R8A7794_CLK_R),
|
||||
DEF_MOD("usbhs-dmac0", 330, R8A7794_CLK_HP),
|
||||
DEF_MOD("usbhs-dmac1", 331, R8A7794_CLK_HP),
|
||||
DEF_MOD("rwdt", 402, R8A7794_CLK_R),
|
||||
DEF_MOD("irqc", 407, R8A7794_CLK_CP),
|
||||
DEF_MOD("intc-sys", 408, R8A7794_CLK_ZS),
|
||||
DEF_MOD("audio-dmac0", 502, R8A7794_CLK_HP),
|
||||
|
||||
@ -1,13 +1,12 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Renesas R8A7795 CPG MSSR driver
|
||||
* r8a7795 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
* Copyright (C) 2015 Glider bvba
|
||||
*
|
||||
* Based on the following driver from Linux kernel:
|
||||
* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
|
||||
* Based on clk-rcar-gen3.c
|
||||
*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
@ -71,7 +70,11 @@ static const struct cpg_core_clk r8a7795_core_clks[] = {
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
|
||||
|
||||
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_BASE("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
|
||||
DEF_BASE("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2),
|
||||
DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
|
||||
DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
|
||||
@ -101,9 +104,16 @@ static const struct cpg_core_clk r8a7795_core_clks[] = {
|
||||
DEF_GEN3_RPC("rpc", R8A7795_CLK_RPC, CLK_RPCSRC, 0x238),
|
||||
|
||||
DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cr", R8A7795_CLK_CR, CLK_PLL1_DIV4, 2, 1),
|
||||
DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A7795_CLK_CPEX, CLK_EXTAL, 2, 1),
|
||||
|
||||
/* NOTE: HDMI, CSI, CAN etc. clock are missing */
|
||||
DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
|
||||
DEF_DIV6P1("csi0", R8A7795_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
|
||||
DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
|
||||
DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
|
||||
|
||||
DEF_GEN3_OSC("osc", R8A7795_CLK_OSC, CLK_EXTAL, 8),
|
||||
|
||||
DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
|
||||
};
|
||||
@ -124,6 +134,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
|
||||
DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S0D3),
|
||||
DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S0D3),
|
||||
DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3),
|
||||
DEF_MOD("sceg-pub", 229, R8A7795_CLK_CR),
|
||||
DEF_MOD("cmt3", 300, R8A7795_CLK_R),
|
||||
DEF_MOD("cmt2", 301, R8A7795_CLK_R),
|
||||
DEF_MOD("cmt1", 302, R8A7795_CLK_R),
|
||||
@ -143,7 +154,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
|
||||
DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("rwdt", 402, R8A7795_CLK_R),
|
||||
DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
|
||||
DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1),
|
||||
DEF_MOD("intc-ap", 408, R8A7795_CLK_S0D3),
|
||||
DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3),
|
||||
DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3),
|
||||
DEF_MOD("drif7", 508, R8A7795_CLK_S3D2),
|
||||
@ -269,25 +280,25 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
|
||||
* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
|
||||
* 14 13 19 17 (MHz)
|
||||
*-------------------------------------------------------------------
|
||||
* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
|
||||
* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
|
||||
*-------------------------------------------------------------------------
|
||||
* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
|
||||
* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
|
||||
* 0 0 1 0 Prohibited setting
|
||||
* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
|
||||
* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
|
||||
* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120
|
||||
* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
|
||||
* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
|
||||
* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
|
||||
* 0 1 1 0 Prohibited setting
|
||||
* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120
|
||||
* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96
|
||||
* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96
|
||||
* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
|
||||
* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
|
||||
* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
|
||||
* 1 0 1 0 Prohibited setting
|
||||
* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96
|
||||
* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144
|
||||
* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144
|
||||
* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
|
||||
* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
|
||||
* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
|
||||
* 1 1 1 0 Prohibited setting
|
||||
* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144
|
||||
* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
|
||||
(((md) & BIT(13)) >> 11) | \
|
||||
@ -295,23 +306,23 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
|
||||
(((md) & BIT(17)) >> 17))
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div */
|
||||
{ 1, 192, 1, 192, 1, },
|
||||
{ 1, 192, 1, 128, 1, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 192, 1, 192, 1, },
|
||||
{ 1, 160, 1, 160, 1, },
|
||||
{ 1, 160, 1, 106, 1, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 160, 1, 160, 1, },
|
||||
{ 1, 128, 1, 128, 1, },
|
||||
{ 1, 128, 1, 84, 1, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 128, 1, 128, 1, },
|
||||
{ 2, 192, 1, 192, 1, },
|
||||
{ 2, 192, 1, 128, 1, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 2, 192, 1, 192, 1, },
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 192, 1, 128, 1, 16, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 160, 1, 106, 1, 19, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 128, 1, 128, 1, 24, },
|
||||
{ 1, 128, 1, 84, 1, 24, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 128, 1, 128, 1, 24, },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
{ 2, 192, 1, 128, 1, 32, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
};
|
||||
|
||||
static const struct mstp_stop_table r8a7795_mstp_table[] = {
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Renesas R8A7796 CPG MSSR driver
|
||||
*
|
||||
@ -8,6 +8,11 @@
|
||||
* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*
|
||||
* Based on r8a7795-cpg-mssr.c
|
||||
*
|
||||
* Copyright (C) 2015 Glider bvba
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
@ -71,7 +76,11 @@ static const struct cpg_core_clk r8a7796_core_clks[] = {
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
|
||||
|
||||
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_BASE("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
|
||||
DEF_BASE("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2),
|
||||
DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
|
||||
DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
|
||||
@ -102,13 +111,20 @@ static const struct cpg_core_clk r8a7796_core_clks[] = {
|
||||
|
||||
DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A7796_CLK_CPEX, CLK_EXTAL, 2, 1),
|
||||
|
||||
/* NOTE: HDMI, CSI, CAN etc. clock are missing */
|
||||
DEF_DIV6P1("canfd", R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
|
||||
DEF_DIV6P1("csi0", R8A7796_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
|
||||
DEF_DIV6P1("mso", R8A7796_CLK_MSO, CLK_PLL1_DIV4, 0x014),
|
||||
DEF_DIV6P1("hdmi", R8A7796_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
|
||||
|
||||
DEF_GEN3_OSC("osc", R8A7796_CLK_OSC, CLK_EXTAL, 8),
|
||||
|
||||
DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a7796_mod_clks[] = {
|
||||
DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
|
||||
DEF_MOD("scif5", 202, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("scif4", 203, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("scif3", 204, R8A7796_CLK_S3D4),
|
||||
@ -137,7 +153,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = {
|
||||
DEF_MOD("usb-dmac1", 331, R8A7796_CLK_S3D1),
|
||||
DEF_MOD("rwdt", 402, R8A7796_CLK_R),
|
||||
DEF_MOD("intc-ex", 407, R8A7796_CLK_CP),
|
||||
DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1),
|
||||
DEF_MOD("intc-ap", 408, R8A7796_CLK_S0D3),
|
||||
DEF_MOD("audmac1", 501, R8A7796_CLK_S0D3),
|
||||
DEF_MOD("audmac0", 502, R8A7796_CLK_S0D3),
|
||||
DEF_MOD("drif7", 508, R8A7796_CLK_S3D2),
|
||||
@ -242,25 +258,25 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = {
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
|
||||
* MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
|
||||
* 14 13 19 17 (MHz)
|
||||
*-------------------------------------------------------------------
|
||||
* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
|
||||
* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
|
||||
*-------------------------------------------------------------------------
|
||||
* 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
|
||||
* 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
|
||||
* 0 0 1 0 Prohibited setting
|
||||
* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
|
||||
* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
|
||||
* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120
|
||||
* 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
|
||||
* 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
|
||||
* 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
|
||||
* 0 1 1 0 Prohibited setting
|
||||
* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120
|
||||
* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96
|
||||
* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96
|
||||
* 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
|
||||
* 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
|
||||
* 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
|
||||
* 1 0 1 0 Prohibited setting
|
||||
* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96
|
||||
* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144
|
||||
* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144
|
||||
* 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
|
||||
* 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
|
||||
* 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
|
||||
* 1 1 1 0 Prohibited setting
|
||||
* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144
|
||||
* 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
|
||||
(((md) & BIT(13)) >> 11) | \
|
||||
@ -268,23 +284,23 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = {
|
||||
(((md) & BIT(17)) >> 17))
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div */
|
||||
{ 1, 192, 1, 192, 1, },
|
||||
{ 1, 192, 1, 128, 1, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 192, 1, 192, 1, },
|
||||
{ 1, 160, 1, 160, 1, },
|
||||
{ 1, 160, 1, 106, 1, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 160, 1, 160, 1, },
|
||||
{ 1, 128, 1, 128, 1, },
|
||||
{ 1, 128, 1, 84, 1, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 128, 1, 128, 1, },
|
||||
{ 2, 192, 1, 192, 1, },
|
||||
{ 2, 192, 1, 128, 1, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 2, 192, 1, 192, 1, },
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 192, 1, 128, 1, 16, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 160, 1, 106, 1, 19, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 128, 1, 128, 1, 24, },
|
||||
{ 1, 128, 1, 84, 1, 24, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 128, 1, 128, 1, 24, },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
{ 2, 192, 1, 128, 1, 32, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
};
|
||||
|
||||
static const struct mstp_stop_table r8a7796_mstp_table[] = {
|
||||
@ -322,30 +338,11 @@ static const struct cpg_mssr_info r8a7796_cpg_mssr_info = {
|
||||
.get_pll_config = r8a7796_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct cpg_mssr_info r8a77965_cpg_mssr_info = {
|
||||
.core_clk = r8a7796_core_clks,
|
||||
.core_clk_size = ARRAY_SIZE(r8a7796_core_clks),
|
||||
.mod_clk = r8a7796_mod_clks,
|
||||
.mod_clk_size = ARRAY_SIZE(r8a7796_mod_clks),
|
||||
.mstp_table = r8a7796_mstp_table,
|
||||
.mstp_table_size = ARRAY_SIZE(r8a7796_mstp_table),
|
||||
.reset_node = "renesas,r8a77965-rst",
|
||||
.extalr_node = "extalr",
|
||||
.mod_clk_base = MOD_CLK_BASE,
|
||||
.clk_extal_id = CLK_EXTAL,
|
||||
.clk_extalr_id = CLK_EXTALR,
|
||||
.get_pll_config = r8a7796_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a7796_clk_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a7796-cpg-mssr",
|
||||
.data = (ulong)&r8a7796_cpg_mssr_info,
|
||||
},
|
||||
{
|
||||
.compatible = "renesas,r8a77965-cpg-mssr",
|
||||
.data = (ulong)&r8a77965_cpg_mssr_info,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
|
||||
355
drivers/clk/renesas/r8a77965-cpg-mssr.c
Normal file
355
drivers/clk/renesas/r8a77965-cpg-mssr.c
Normal file
@ -0,0 +1,355 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* r8a77965 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
|
||||
*
|
||||
* Based on r8a7795-cpg-mssr.c
|
||||
*
|
||||
* Copyright (C) 2015 Glider bvba
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clk-uclass.h>
|
||||
#include <dm.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a77965-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen3-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A77965_CLK_OSC,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
CLK_EXTALR,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL0,
|
||||
CLK_PLL1,
|
||||
CLK_PLL3,
|
||||
CLK_PLL4,
|
||||
CLK_PLL1_DIV2,
|
||||
CLK_PLL1_DIV4,
|
||||
CLK_S0,
|
||||
CLK_S1,
|
||||
CLK_S2,
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_RPCSRC,
|
||||
CLK_SSPSRC,
|
||||
CLK_RINT,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a77965_core_clks[] = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
DEF_INPUT("extalr", CLK_EXTALR),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
|
||||
DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
|
||||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
|
||||
|
||||
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_BASE("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
|
||||
DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED("ztrd2", R8A77965_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
|
||||
DEF_FIXED("zt", R8A77965_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED("zx", R8A77965_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED("s0d1", R8A77965_CLK_S0D1, CLK_S0, 1, 1),
|
||||
DEF_FIXED("s0d2", R8A77965_CLK_S0D2, CLK_S0, 2, 1),
|
||||
DEF_FIXED("s0d3", R8A77965_CLK_S0D3, CLK_S0, 3, 1),
|
||||
DEF_FIXED("s0d4", R8A77965_CLK_S0D4, CLK_S0, 4, 1),
|
||||
DEF_FIXED("s0d6", R8A77965_CLK_S0D6, CLK_S0, 6, 1),
|
||||
DEF_FIXED("s0d8", R8A77965_CLK_S0D8, CLK_S0, 8, 1),
|
||||
DEF_FIXED("s0d12", R8A77965_CLK_S0D12, CLK_S0, 12, 1),
|
||||
DEF_FIXED("s1d1", R8A77965_CLK_S1D1, CLK_S1, 1, 1),
|
||||
DEF_FIXED("s1d2", R8A77965_CLK_S1D2, CLK_S1, 2, 1),
|
||||
DEF_FIXED("s1d4", R8A77965_CLK_S1D4, CLK_S1, 4, 1),
|
||||
DEF_FIXED("s2d1", R8A77965_CLK_S2D1, CLK_S2, 1, 1),
|
||||
DEF_FIXED("s2d2", R8A77965_CLK_S2D2, CLK_S2, 2, 1),
|
||||
DEF_FIXED("s2d4", R8A77965_CLK_S2D4, CLK_S2, 4, 1),
|
||||
DEF_FIXED("s3d1", R8A77965_CLK_S3D1, CLK_S3, 1, 1),
|
||||
DEF_FIXED("s3d2", R8A77965_CLK_S3D2, CLK_S3, 2, 1),
|
||||
DEF_FIXED("s3d4", R8A77965_CLK_S3D4, CLK_S3, 4, 1),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A77965_CLK_SD0, CLK_SDSRC, 0x074),
|
||||
DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, CLK_SDSRC, 0x078),
|
||||
DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, CLK_SDSRC, 0x268),
|
||||
DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, CLK_SDSRC, 0x26c),
|
||||
|
||||
DEF_GEN3_RPC("rpc", R8A77965_CLK_RPC, CLK_RPCSRC, 0x238),
|
||||
|
||||
DEF_FIXED("cl", R8A77965_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cp", R8A77965_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A77965_CLK_CPEX, CLK_EXTAL, 2, 1),
|
||||
|
||||
DEF_DIV6P1("canfd", R8A77965_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
|
||||
DEF_DIV6P1("csi0", R8A77965_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
|
||||
DEF_DIV6P1("mso", R8A77965_CLK_MSO, CLK_PLL1_DIV4, 0x014),
|
||||
DEF_DIV6P1("hdmi", R8A77965_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
|
||||
|
||||
DEF_GEN3_OSC("osc", R8A77965_CLK_OSC, CLK_EXTAL, 8),
|
||||
|
||||
DEF_BASE("r", R8A77965_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a77965_mod_clks[] = {
|
||||
DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1),
|
||||
DEF_MOD("scif5", 202, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("scif4", 203, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("scif3", 204, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("scif1", 206, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("scif0", 207, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("msiof3", 208, R8A77965_CLK_MSO),
|
||||
DEF_MOD("msiof2", 209, R8A77965_CLK_MSO),
|
||||
DEF_MOD("msiof1", 210, R8A77965_CLK_MSO),
|
||||
DEF_MOD("msiof0", 211, R8A77965_CLK_MSO),
|
||||
DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S0D3),
|
||||
DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S0D3),
|
||||
DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3),
|
||||
|
||||
DEF_MOD("cmt3", 300, R8A77965_CLK_R),
|
||||
DEF_MOD("cmt2", 301, R8A77965_CLK_R),
|
||||
DEF_MOD("cmt1", 302, R8A77965_CLK_R),
|
||||
DEF_MOD("cmt0", 303, R8A77965_CLK_R),
|
||||
DEF_MOD("scif2", 310, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("sdif3", 311, R8A77965_CLK_SD3),
|
||||
DEF_MOD("sdif2", 312, R8A77965_CLK_SD2),
|
||||
DEF_MOD("sdif1", 313, R8A77965_CLK_SD1),
|
||||
DEF_MOD("sdif0", 314, R8A77965_CLK_SD0),
|
||||
DEF_MOD("pcie1", 318, R8A77965_CLK_S3D1),
|
||||
DEF_MOD("pcie0", 319, R8A77965_CLK_S3D1),
|
||||
DEF_MOD("usb3-if0", 328, R8A77965_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac0", 330, R8A77965_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac1", 331, R8A77965_CLK_S3D1),
|
||||
|
||||
DEF_MOD("rwdt", 402, R8A77965_CLK_R),
|
||||
DEF_MOD("intc-ex", 407, R8A77965_CLK_CP),
|
||||
DEF_MOD("intc-ap", 408, R8A77965_CLK_S0D3),
|
||||
|
||||
DEF_MOD("audmac1", 501, R8A77965_CLK_S0D3),
|
||||
DEF_MOD("audmac0", 502, R8A77965_CLK_S0D3),
|
||||
DEF_MOD("drif7", 508, R8A77965_CLK_S3D2),
|
||||
DEF_MOD("drif6", 509, R8A77965_CLK_S3D2),
|
||||
DEF_MOD("drif5", 510, R8A77965_CLK_S3D2),
|
||||
DEF_MOD("drif4", 511, R8A77965_CLK_S3D2),
|
||||
DEF_MOD("drif3", 512, R8A77965_CLK_S3D2),
|
||||
DEF_MOD("drif2", 513, R8A77965_CLK_S3D2),
|
||||
DEF_MOD("drif1", 514, R8A77965_CLK_S3D2),
|
||||
DEF_MOD("drif0", 515, R8A77965_CLK_S3D2),
|
||||
DEF_MOD("hscif4", 516, R8A77965_CLK_S3D1),
|
||||
DEF_MOD("hscif3", 517, R8A77965_CLK_S3D1),
|
||||
DEF_MOD("hscif2", 518, R8A77965_CLK_S3D1),
|
||||
DEF_MOD("hscif1", 519, R8A77965_CLK_S3D1),
|
||||
DEF_MOD("hscif0", 520, R8A77965_CLK_S3D1),
|
||||
DEF_MOD("thermal", 522, R8A77965_CLK_CP),
|
||||
DEF_MOD("pwm", 523, R8A77965_CLK_S0D12),
|
||||
|
||||
DEF_MOD("fcpvd1", 602, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("fcpvd0", 603, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("fcpvb0", 607, R8A77965_CLK_S0D1),
|
||||
DEF_MOD("fcpvi0", 611, R8A77965_CLK_S0D1),
|
||||
DEF_MOD("fcpf0", 615, R8A77965_CLK_S0D1),
|
||||
DEF_MOD("fcpcs", 619, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("vspd1", 622, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("vspd0", 623, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("vspb", 626, R8A77965_CLK_S0D1),
|
||||
DEF_MOD("vspi0", 631, R8A77965_CLK_S0D1),
|
||||
|
||||
DEF_MOD("ehci1", 702, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("ehci0", 703, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("hsusb", 704, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("csi20", 714, R8A77965_CLK_CSI0),
|
||||
DEF_MOD("csi40", 716, R8A77965_CLK_CSI0),
|
||||
DEF_MOD("du3", 721, R8A77965_CLK_S2D1),
|
||||
DEF_MOD("du1", 723, R8A77965_CLK_S2D1),
|
||||
DEF_MOD("du0", 724, R8A77965_CLK_S2D1),
|
||||
DEF_MOD("lvds", 727, R8A77965_CLK_S2D1),
|
||||
DEF_MOD("hdmi0", 729, R8A77965_CLK_HDMI),
|
||||
|
||||
DEF_MOD("vin7", 804, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("vin6", 805, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("vin5", 806, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("vin4", 807, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("vin3", 808, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("vin2", 809, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("vin1", 810, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("vin0", 811, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("etheravb", 812, R8A77965_CLK_S0D6),
|
||||
DEF_MOD("sata0", 815, R8A77965_CLK_S3D2),
|
||||
DEF_MOD("imr1", 822, R8A77965_CLK_S0D2),
|
||||
DEF_MOD("imr0", 823, R8A77965_CLK_S0D2),
|
||||
|
||||
DEF_MOD("gpio7", 905, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("gpio6", 906, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("gpio5", 907, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("gpio4", 908, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("gpio3", 909, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("gpio2", 910, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("gpio1", 911, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("gpio0", 912, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("can-fd", 914, R8A77965_CLK_S3D2),
|
||||
DEF_MOD("can-if1", 915, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("can-if0", 916, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("rpc", 917, R8A77965_CLK_RPC),
|
||||
DEF_MOD("i2c6", 918, R8A77965_CLK_S0D6),
|
||||
DEF_MOD("i2c5", 919, R8A77965_CLK_S0D6),
|
||||
DEF_MOD("i2c-dvfs", 926, R8A77965_CLK_CP),
|
||||
DEF_MOD("i2c4", 927, R8A77965_CLK_S0D6),
|
||||
DEF_MOD("i2c3", 928, R8A77965_CLK_S0D6),
|
||||
DEF_MOD("i2c2", 929, R8A77965_CLK_S3D2),
|
||||
DEF_MOD("i2c1", 930, R8A77965_CLK_S3D2),
|
||||
DEF_MOD("i2c0", 931, R8A77965_CLK_S3D2),
|
||||
|
||||
DEF_MOD("ssi-all", 1005, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("scu-all", 1017, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL3 PLL4 OSC
|
||||
* 14 13 19 17 (MHz)
|
||||
*-----------------------------------------------------------------
|
||||
* 0 0 0 0 16.66 x 1 x180 x192 x192 x144 /16
|
||||
* 0 0 0 1 16.66 x 1 x180 x192 x128 x144 /16
|
||||
* 0 0 1 0 Prohibited setting
|
||||
* 0 0 1 1 16.66 x 1 x180 x192 x192 x144 /16
|
||||
* 0 1 0 0 20 x 1 x150 x160 x160 x120 /19
|
||||
* 0 1 0 1 20 x 1 x150 x160 x106 x120 /19
|
||||
* 0 1 1 0 Prohibited setting
|
||||
* 0 1 1 1 20 x 1 x150 x160 x160 x120 /19
|
||||
* 1 0 0 0 25 x 1 x120 x128 x128 x96 /24
|
||||
* 1 0 0 1 25 x 1 x120 x128 x84 x96 /24
|
||||
* 1 0 1 0 Prohibited setting
|
||||
* 1 0 1 1 25 x 1 x120 x128 x128 x96 /24
|
||||
* 1 1 0 0 33.33 / 2 x180 x192 x192 x144 /32
|
||||
* 1 1 0 1 33.33 / 2 x180 x192 x128 x144 /32
|
||||
* 1 1 1 0 Prohibited setting
|
||||
* 1 1 1 1 33.33 / 2 x180 x192 x192 x144 /32
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
|
||||
(((md) & BIT(13)) >> 11) | \
|
||||
(((md) & BIT(19)) >> 18) | \
|
||||
(((md) & BIT(17)) >> 17))
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 192, 1, 128, 1, 16, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 160, 1, 106, 1, 19, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 128, 1, 128, 1, 24, },
|
||||
{ 1, 128, 1, 84, 1, 24, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 128, 1, 128, 1, 24, },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
{ 2, 192, 1, 128, 1, 32, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
};
|
||||
|
||||
static const struct mstp_stop_table r8a77965_mstp_table[] = {
|
||||
{ 0x00200000, 0x0, 0x00200000, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0x340E2FDC, 0x2040, 0x340E2FDC, 0 },
|
||||
{ 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
|
||||
{ 0x80000184, 0x180, 0x80000184, 0 },
|
||||
{ 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
|
||||
{ 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 },
|
||||
{ 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 },
|
||||
{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
|
||||
{ 0x000000B7, 0x0, 0x000000B7, 0 },
|
||||
};
|
||||
|
||||
static const void *r8a77965_get_pll_config(const u32 cpg_mode)
|
||||
{
|
||||
return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
}
|
||||
|
||||
static const struct cpg_mssr_info r8a77965_cpg_mssr_info = {
|
||||
.core_clk = r8a77965_core_clks,
|
||||
.core_clk_size = ARRAY_SIZE(r8a77965_core_clks),
|
||||
.mod_clk = r8a77965_mod_clks,
|
||||
.mod_clk_size = ARRAY_SIZE(r8a77965_mod_clks),
|
||||
.mstp_table = r8a77965_mstp_table,
|
||||
.mstp_table_size = ARRAY_SIZE(r8a77965_mstp_table),
|
||||
.reset_node = "renesas,r8a77965-rst",
|
||||
.extalr_node = "extalr",
|
||||
.mod_clk_base = MOD_CLK_BASE,
|
||||
.clk_extal_id = CLK_EXTAL,
|
||||
.clk_extalr_id = CLK_EXTALR,
|
||||
.get_pll_config = r8a77965_get_pll_config,
|
||||
};
|
||||
|
||||
static const struct udevice_id r8a77965_clk_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,r8a77965-cpg-mssr",
|
||||
.data = (ulong)&r8a77965_cpg_mssr_info,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_r8a77965) = {
|
||||
.name = "clk_r8a77965",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = r8a77965_clk_ids,
|
||||
.priv_auto_alloc_size = sizeof(struct gen3_clk_priv),
|
||||
.ops = &gen3_clk_ops,
|
||||
.probe = gen3_clk_probe,
|
||||
.remove = gen3_clk_remove,
|
||||
};
|
||||
@ -1,13 +1,13 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Renesas R8A77990 CPG MSSR driver
|
||||
* r8a77990 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
*
|
||||
* Based on the following driver from Linux kernel:
|
||||
* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
|
||||
* Based on r8a7795-cpg-mssr.c
|
||||
*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
* Copyright (C) 2015 Glider bvba
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
@ -44,6 +44,8 @@ enum clk_ids {
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_RPCSRC,
|
||||
CLK_RINT,
|
||||
CLK_OCO,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
@ -73,6 +75,10 @@ static const struct cpg_core_clk r8a77990_core_clks[] = {
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
|
||||
|
||||
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
|
||||
|
||||
DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1),
|
||||
DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1),
|
||||
@ -103,10 +109,10 @@ static const struct cpg_core_clk r8a77990_core_clks[] = {
|
||||
DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("cp", R8A77990_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A77990_CLK_CPEX, CLK_EXTAL, 4, 1),
|
||||
DEF_FIXED("osc", R8A77990_CLK_OSC, CLK_EXTAL, 384, 1),
|
||||
DEF_FIXED("r", R8A77990_CLK_R, CLK_EXTAL, 1536, 1),
|
||||
|
||||
DEF_GEN3_PE("s0d6c", R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 6),
|
||||
DEF_DIV6_RO("osc", R8A77990_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
|
||||
|
||||
DEF_GEN3_PE("s0d6c", R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 2),
|
||||
DEF_GEN3_PE("s3d1c", R8A77990_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
|
||||
DEF_GEN3_PE("s3d2c", R8A77990_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
|
||||
DEF_GEN3_PE("s3d4c", R8A77990_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
|
||||
@ -114,6 +120,8 @@ static const struct cpg_core_clk r8a77990_core_clks[] = {
|
||||
DEF_DIV6P1("canfd", R8A77990_CLK_CANFD, CLK_PLL0D6, 0x244),
|
||||
DEF_DIV6P1("csi0", R8A77990_CLK_CSI0, CLK_PLL1D2, 0x00c),
|
||||
DEF_DIV6P1("mso", R8A77990_CLK_MSO, CLK_PLL1D2, 0x014),
|
||||
|
||||
DEF_GEN3_RCKSEL("r", R8A77990_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a77990_mod_clks[] = {
|
||||
@ -178,12 +186,10 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = {
|
||||
DEF_MOD("ehci0", 703, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("hsusb", 704, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("csi40", 716, R8A77990_CLK_CSI0),
|
||||
DEF_MOD("du1", 723, R8A77990_CLK_S2D1),
|
||||
DEF_MOD("du0", 724, R8A77990_CLK_S2D1),
|
||||
DEF_MOD("du1", 723, R8A77990_CLK_S1D1),
|
||||
DEF_MOD("du0", 724, R8A77990_CLK_S1D1),
|
||||
DEF_MOD("lvds", 727, R8A77990_CLK_S2D1),
|
||||
|
||||
DEF_MOD("vin7", 804, R8A77990_CLK_S1D2),
|
||||
DEF_MOD("vin6", 805, R8A77990_CLK_S1D2),
|
||||
DEF_MOD("vin5", 806, R8A77990_CLK_S1D2),
|
||||
DEF_MOD("vin4", 807, R8A77990_CLK_S1D2),
|
||||
DEF_MOD("etheravb", 812, R8A77990_CLK_S3D2),
|
||||
@ -208,6 +214,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = {
|
||||
DEF_MOD("i2c1", 930, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("i2c0", 931, R8A77990_CLK_S3D2),
|
||||
|
||||
DEF_MOD("i2c7", 1003, R8A77990_CLK_S3D2),
|
||||
DEF_MOD("ssi-all", 1005, R8A77990_CLK_S3D4),
|
||||
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
|
||||
@ -243,8 +250,8 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = {
|
||||
/*
|
||||
* MD19 EXTAL (MHz) PLL0 PLL1 PLL3
|
||||
*--------------------------------------------------------------------
|
||||
* 0 48 x 1 x100/4 x100/3 x100/3
|
||||
* 1 48 x 1 x100/4 x100/3 x58/3
|
||||
* 0 48 x 1 x100/1 x100/3 x100/3
|
||||
* 1 48 x 1 x100/1 x100/3 x58/3
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
|
||||
|
||||
|
||||
@ -1,13 +1,13 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Renesas R8A77995 CPG MSSR driver
|
||||
* r8a77995 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
|
||||
* Copyright (C) 2017 Glider bvba
|
||||
*
|
||||
* Based on the following driver from Linux kernel:
|
||||
* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
|
||||
* Based on r8a7795-cpg-mssr.c
|
||||
*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
* Copyright (C) 2015 Glider bvba
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
@ -21,7 +21,7 @@
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A77995_CLK_CP,
|
||||
LAST_DT_CORE_CLK = R8A77995_CLK_CPEX,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
@ -42,7 +42,8 @@ enum clk_ids {
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_RPCSRC,
|
||||
CLK_SSPSRC,
|
||||
CLK_RINT,
|
||||
CLK_OCO,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
@ -70,6 +71,10 @@ static const struct cpg_core_clk r8a77995_core_clks[] = {
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
|
||||
|
||||
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
|
||||
|
||||
DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1),
|
||||
DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
|
||||
@ -88,8 +93,9 @@ static const struct cpg_core_clk r8a77995_core_clks[] = {
|
||||
|
||||
DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("osc", R8A77995_CLK_OSC, CLK_EXTAL, 384, 1),
|
||||
DEF_FIXED("r", R8A77995_CLK_R, CLK_EXTAL, 1536, 1),
|
||||
DEF_FIXED("cpex", R8A77995_CLK_CPEX, CLK_EXTAL, 4, 1),
|
||||
|
||||
DEF_DIV6_RO("osc", R8A77995_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
|
||||
|
||||
DEF_GEN3_RPC("rpc", R8A77995_CLK_RPC, CLK_RPCSRC, 0x238),
|
||||
|
||||
@ -99,6 +105,11 @@ static const struct cpg_core_clk r8a77995_core_clks[] = {
|
||||
DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, CLK_SDSRC, 0x268),
|
||||
|
||||
DEF_DIV6P1("canfd", R8A77995_CLK_CANFD, CLK_PLL0D3, 0x244),
|
||||
DEF_DIV6P1("mso", R8A77995_CLK_MSO, CLK_PLL1D2, 0x014),
|
||||
|
||||
DEF_GEN3_RCKSEL("r", R8A77995_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a77995_mod_clks[] = {
|
||||
@ -124,7 +135,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = {
|
||||
DEF_MOD("usb-dmac1", 331, R8A77995_CLK_S3D1),
|
||||
DEF_MOD("rwdt", 402, R8A77995_CLK_R),
|
||||
DEF_MOD("intc-ex", 407, R8A77995_CLK_CP),
|
||||
DEF_MOD("intc-ap", 408, R8A77995_CLK_S3D1),
|
||||
DEF_MOD("intc-ap", 408, R8A77995_CLK_S1D2),
|
||||
DEF_MOD("audmac0", 502, R8A77995_CLK_S3D1),
|
||||
DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C),
|
||||
DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C),
|
||||
@ -138,12 +149,9 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = {
|
||||
DEF_MOD("vspbs", 627, R8A77995_CLK_S0D1),
|
||||
DEF_MOD("ehci0", 703, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("hsusb", 704, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("du1", 723, R8A77995_CLK_S2D1),
|
||||
DEF_MOD("du0", 724, R8A77995_CLK_S2D1),
|
||||
DEF_MOD("du1", 723, R8A77995_CLK_S1D1),
|
||||
DEF_MOD("du0", 724, R8A77995_CLK_S1D1),
|
||||
DEF_MOD("lvds", 727, R8A77995_CLK_S2D1),
|
||||
DEF_MOD("vin7", 804, R8A77995_CLK_S1D2),
|
||||
DEF_MOD("vin6", 805, R8A77995_CLK_S1D2),
|
||||
DEF_MOD("vin5", 806, R8A77995_CLK_S1D2),
|
||||
DEF_MOD("vin4", 807, R8A77995_CLK_S1D2),
|
||||
DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2),
|
||||
DEF_MOD("imr0", 823, R8A77995_CLK_S1D2),
|
||||
@ -182,14 +190,14 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = {
|
||||
* MD19 EXTAL (MHz) PLL0 PLL1 PLL3
|
||||
*--------------------------------------------------------------------
|
||||
* 0 48 x 1 x250/4 x100/3 x100/3
|
||||
* 1 48 x 1 x250/4 x100/3 x116/6
|
||||
* 1 48 x 1 x250/4 x100/3 x58/3
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] = {
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div */
|
||||
{ 1, 100, 3, 100, 3, },
|
||||
{ 1, 100, 3, 116, 6, },
|
||||
{ 1, 100, 3, 58, 3, },
|
||||
};
|
||||
|
||||
static const struct mstp_stop_table r8a77995_mstp_table[] = {
|
||||
|
||||
@ -19,21 +19,43 @@ enum rcar_gen3_clk_types {
|
||||
CLK_TYPE_GEN3_PLL3,
|
||||
CLK_TYPE_GEN3_PLL4,
|
||||
CLK_TYPE_GEN3_SD,
|
||||
CLK_TYPE_GEN3_RPC,
|
||||
CLK_TYPE_GEN3_R,
|
||||
CLK_TYPE_GEN3_PE,
|
||||
CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */
|
||||
CLK_TYPE_GEN3_Z,
|
||||
CLK_TYPE_GEN3_Z2,
|
||||
CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
|
||||
CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
|
||||
CLK_TYPE_GEN3_RPCSRC,
|
||||
CLK_TYPE_GEN3_RPC,
|
||||
CLK_TYPE_GEN3_RPCD2,
|
||||
|
||||
/* SoC specific definitions start here */
|
||||
CLK_TYPE_GEN3_SOC_BASE,
|
||||
};
|
||||
|
||||
#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
|
||||
|
||||
#define DEF_GEN3_RPC(_name, _id, _parent, _offset) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset)
|
||||
|
||||
#define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
|
||||
(_parent0) << 16 | (_parent1), \
|
||||
.div = (_div0) << 16 | (_div1), .offset = _md)
|
||||
|
||||
#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
|
||||
_div_clean) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_PE, \
|
||||
(_parent_sscg) << 16 | (_parent_clean), \
|
||||
.div = (_div_sscg) << 16 | (_div_clean))
|
||||
DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \
|
||||
_parent_clean, _div_clean)
|
||||
|
||||
#define DEF_GEN3_OSC(_name, _id, _parent, _div) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
|
||||
|
||||
#define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \
|
||||
(_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1))
|
||||
|
||||
|
||||
struct rcar_gen3_cpg_pll_config {
|
||||
u8 extal_div;
|
||||
@ -41,8 +63,10 @@ struct rcar_gen3_cpg_pll_config {
|
||||
u8 pll1_div;
|
||||
u8 pll3_mult;
|
||||
u8 pll3_div;
|
||||
u8 osc_prediv;
|
||||
};
|
||||
|
||||
#define CPG_RPCCKCR 0x238
|
||||
#define CPG_RCKCR 0x240
|
||||
|
||||
struct gen3_clk_priv {
|
||||
|
||||
@ -57,6 +57,7 @@ enum clk_types {
|
||||
CLK_TYPE_FF, /* Fixed Factor Clock */
|
||||
CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
|
||||
CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */
|
||||
CLK_TYPE_FR, /* Fixed Rate Clock */
|
||||
|
||||
/* Custom definitions start here */
|
||||
CLK_TYPE_CUSTOM,
|
||||
@ -75,6 +76,8 @@ enum clk_types {
|
||||
DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
|
||||
#define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \
|
||||
DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
|
||||
#define DEF_RATE(_name, _id, _rate) \
|
||||
DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate)
|
||||
|
||||
/*
|
||||
* Definitions of Module Clocks
|
||||
|
||||
@ -769,19 +769,9 @@ static int sh_ether_start(struct udevice *dev)
|
||||
struct sh_eth_dev *eth = &priv->shdev;
|
||||
int ret;
|
||||
|
||||
ret = clk_enable(&priv->clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = sh_eth_init_common(eth, pdata->enetaddr);
|
||||
if (ret)
|
||||
goto err_clk;
|
||||
|
||||
ret = sh_eth_phy_config(dev);
|
||||
if (ret) {
|
||||
printf(SHETHER_NAME ": phy config timeout\n");
|
||||
goto err_start;
|
||||
}
|
||||
return ret;
|
||||
|
||||
ret = sh_eth_start_common(eth);
|
||||
if (ret)
|
||||
@ -792,17 +782,17 @@ static int sh_ether_start(struct udevice *dev)
|
||||
err_start:
|
||||
sh_eth_tx_desc_free(eth);
|
||||
sh_eth_rx_desc_free(eth);
|
||||
err_clk:
|
||||
clk_disable(&priv->clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void sh_ether_stop(struct udevice *dev)
|
||||
{
|
||||
struct sh_ether_priv *priv = dev_get_priv(dev);
|
||||
struct sh_eth_dev *eth = &priv->shdev;
|
||||
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
||||
|
||||
phy_shutdown(port_info->phydev);
|
||||
sh_eth_stop(&priv->shdev);
|
||||
clk_disable(&priv->clk);
|
||||
}
|
||||
|
||||
static int sh_ether_probe(struct udevice *udev)
|
||||
@ -853,8 +843,20 @@ static int sh_ether_probe(struct udevice *udev)
|
||||
eth->port_info[eth->port].iobase =
|
||||
(void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
|
||||
|
||||
ret = clk_enable(&priv->clk);
|
||||
if (ret)
|
||||
goto err_mdio_register;
|
||||
|
||||
ret = sh_eth_phy_config(udev);
|
||||
if (ret) {
|
||||
printf(SHETHER_NAME ": phy config timeout\n");
|
||||
goto err_phy_config;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_phy_config:
|
||||
clk_disable(&priv->clk);
|
||||
err_mdio_register:
|
||||
mdio_free(mdiodev);
|
||||
return ret;
|
||||
@ -866,6 +868,7 @@ static int sh_ether_remove(struct udevice *udev)
|
||||
struct sh_eth_dev *eth = &priv->shdev;
|
||||
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
||||
|
||||
clk_disable(&priv->clk);
|
||||
free(port_info->phydev);
|
||||
mdio_unregister(priv->bus);
|
||||
mdio_free(priv->bus);
|
||||
|
||||
@ -76,6 +76,16 @@ config PINCTRL_PFC_R8A7796
|
||||
the GPIO definitions and pin control functions for each available
|
||||
multiplex function.
|
||||
|
||||
config PINCTRL_PFC_R8A77965
|
||||
bool "Renesas RCar Gen3 R8A77965 pin control driver"
|
||||
depends on PINCTRL_PFC
|
||||
help
|
||||
Support pin multiplexing control on Renesas RCar Gen3 R8A77965 SoCs.
|
||||
|
||||
The driver is controlled by a device tree node which contains both
|
||||
the GPIO definitions and pin control functions for each available
|
||||
multiplex function.
|
||||
|
||||
config PINCTRL_PFC_R8A77970
|
||||
bool "Renesas RCar Gen3 R8A77970 pin control driver"
|
||||
depends on PINCTRL_PFC
|
||||
|
||||
@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o
|
||||
obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
|
||||
|
||||
@ -5694,7 +5694,18 @@ static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
|
||||
return 31 - (pin & 0x1f);
|
||||
}
|
||||
|
||||
static int r8a7790_pinmux_soc_init(struct sh_pfc *pfc)
|
||||
{
|
||||
/* Initialize TDSEL on old revisions */
|
||||
if ((rmobile_get_cpu_rev_integer() == 1) &&
|
||||
(rmobile_get_cpu_rev_fraction() == 0))
|
||||
sh_pfc_write(pfc, 0xe6060088, 0x00155554);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = {
|
||||
.init = r8a7790_pinmux_soc_init,
|
||||
.pin_to_pocctrl = r8a7790_pin_to_pocctrl,
|
||||
};
|
||||
|
||||
|
||||
@ -3221,8 +3221,7 @@ static const unsigned int qspi_data4_b_pins[] = {
|
||||
RCAR_GP_PIN(6, 4),
|
||||
};
|
||||
static const unsigned int qspi_data4_b_mux[] = {
|
||||
SPCLK_B_MARK, MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
|
||||
IO2_B_MARK, IO3_B_MARK, SSL_B_MARK,
|
||||
MOSI_IO0_B_MARK, MISO_IO1_B_MARK, IO2_B_MARK, IO3_B_MARK,
|
||||
};
|
||||
/* - SCIF0 ------------------------------------------------------------------ */
|
||||
static const unsigned int scif0_data_pins[] = {
|
||||
@ -4322,7 +4321,7 @@ static const unsigned int vin1_clk_pins[] = {
|
||||
static const unsigned int vin1_clk_mux[] = {
|
||||
VI1_CLK_MARK,
|
||||
};
|
||||
static const union vin_data vin1_b_data_pins = {
|
||||
static const union vin_data vin1_data_b_pins = {
|
||||
.data24 = {
|
||||
/* B */
|
||||
RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
|
||||
@ -4341,7 +4340,7 @@ static const union vin_data vin1_b_data_pins = {
|
||||
RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
|
||||
},
|
||||
};
|
||||
static const union vin_data vin1_b_data_mux = {
|
||||
static const union vin_data vin1_data_b_mux = {
|
||||
.data24 = {
|
||||
/* B */
|
||||
VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
|
||||
@ -4360,7 +4359,7 @@ static const union vin_data vin1_b_data_mux = {
|
||||
VI1_R6_B_MARK, VI1_R7_B_MARK,
|
||||
},
|
||||
};
|
||||
static const unsigned int vin1_b_data18_pins[] = {
|
||||
static const unsigned int vin1_data18_b_pins[] = {
|
||||
/* B */
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
|
||||
@ -4374,47 +4373,44 @@ static const unsigned int vin1_b_data18_pins[] = {
|
||||
RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
|
||||
RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
|
||||
};
|
||||
static const unsigned int vin1_b_data18_mux[] = {
|
||||
static const unsigned int vin1_data18_b_mux[] = {
|
||||
/* B */
|
||||
VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
|
||||
VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
|
||||
VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
|
||||
VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
|
||||
/* G */
|
||||
VI1_G0_B_MARK, VI1_G1_B_MARK,
|
||||
VI1_G2_B_MARK, VI1_G3_B_MARK,
|
||||
VI1_G4_B_MARK, VI1_G5_B_MARK,
|
||||
VI1_G6_B_MARK, VI1_G7_B_MARK,
|
||||
/* R */
|
||||
VI1_R0_B_MARK, VI1_R1_B_MARK,
|
||||
VI1_R2_B_MARK, VI1_R3_B_MARK,
|
||||
VI1_R4_B_MARK, VI1_R5_B_MARK,
|
||||
VI1_R6_B_MARK, VI1_R7_B_MARK,
|
||||
};
|
||||
static const unsigned int vin1_b_sync_pins[] = {
|
||||
static const unsigned int vin1_sync_b_pins[] = {
|
||||
RCAR_GP_PIN(3, 17), /* HSYNC */
|
||||
RCAR_GP_PIN(3, 18), /* VSYNC */
|
||||
};
|
||||
static const unsigned int vin1_b_sync_mux[] = {
|
||||
static const unsigned int vin1_sync_b_mux[] = {
|
||||
VI1_HSYNC_N_B_MARK,
|
||||
VI1_VSYNC_N_B_MARK,
|
||||
};
|
||||
static const unsigned int vin1_b_field_pins[] = {
|
||||
static const unsigned int vin1_field_b_pins[] = {
|
||||
RCAR_GP_PIN(3, 20),
|
||||
};
|
||||
static const unsigned int vin1_b_field_mux[] = {
|
||||
static const unsigned int vin1_field_b_mux[] = {
|
||||
VI1_FIELD_B_MARK,
|
||||
};
|
||||
static const unsigned int vin1_b_clkenb_pins[] = {
|
||||
static const unsigned int vin1_clkenb_b_pins[] = {
|
||||
RCAR_GP_PIN(3, 19),
|
||||
};
|
||||
static const unsigned int vin1_b_clkenb_mux[] = {
|
||||
static const unsigned int vin1_clkenb_b_mux[] = {
|
||||
VI1_CLKENB_B_MARK,
|
||||
};
|
||||
static const unsigned int vin1_b_clk_pins[] = {
|
||||
static const unsigned int vin1_clk_b_pins[] = {
|
||||
RCAR_GP_PIN(3, 16),
|
||||
};
|
||||
static const unsigned int vin1_b_clk_mux[] = {
|
||||
static const unsigned int vin1_clk_b_mux[] = {
|
||||
VI1_CLK_B_MARK,
|
||||
};
|
||||
/* - VIN2 ----------------------------------------------------------------- */
|
||||
@ -4459,7 +4455,7 @@ static const unsigned int vin2_clk_mux[] = {
|
||||
|
||||
static const struct {
|
||||
struct sh_pfc_pin_group common[346];
|
||||
struct sh_pfc_pin_group r8a779x[9];
|
||||
struct sh_pfc_pin_group automotive[9];
|
||||
} pinmux_groups = {
|
||||
.common = {
|
||||
SH_PFC_PIN_GROUP(audio_clk_a),
|
||||
@ -4792,24 +4788,24 @@ static const struct {
|
||||
SH_PFC_PIN_GROUP(vin1_field),
|
||||
SH_PFC_PIN_GROUP(vin1_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin1_clk),
|
||||
VIN_DATA_PIN_GROUP(vin1_b_data, 24),
|
||||
VIN_DATA_PIN_GROUP(vin1_b_data, 20),
|
||||
SH_PFC_PIN_GROUP(vin1_b_data18),
|
||||
VIN_DATA_PIN_GROUP(vin1_b_data, 16),
|
||||
VIN_DATA_PIN_GROUP(vin1_b_data, 12),
|
||||
VIN_DATA_PIN_GROUP(vin1_b_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin1_b_data, 8),
|
||||
SH_PFC_PIN_GROUP(vin1_b_sync),
|
||||
SH_PFC_PIN_GROUP(vin1_b_field),
|
||||
SH_PFC_PIN_GROUP(vin1_b_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin1_b_clk),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
|
||||
SH_PFC_PIN_GROUP(vin1_data18_b),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 12, _b),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 10, _b),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 8, _b),
|
||||
SH_PFC_PIN_GROUP(vin1_sync_b),
|
||||
SH_PFC_PIN_GROUP(vin1_field_b),
|
||||
SH_PFC_PIN_GROUP(vin1_clkenb_b),
|
||||
SH_PFC_PIN_GROUP(vin1_clk_b),
|
||||
SH_PFC_PIN_GROUP(vin2_data8),
|
||||
SH_PFC_PIN_GROUP(vin2_sync),
|
||||
SH_PFC_PIN_GROUP(vin2_field),
|
||||
SH_PFC_PIN_GROUP(vin2_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin2_clk),
|
||||
},
|
||||
.r8a779x = {
|
||||
.automotive = {
|
||||
SH_PFC_PIN_GROUP(adi_common),
|
||||
SH_PFC_PIN_GROUP(adi_chsel0),
|
||||
SH_PFC_PIN_GROUP(adi_chsel1),
|
||||
@ -5244,7 +5240,7 @@ static const char * const scifb2_groups[] = {
|
||||
"scifb2_data_b",
|
||||
"scifb2_clk_b",
|
||||
"scifb2_ctrl_b",
|
||||
"scifb0_data_c",
|
||||
"scifb2_data_c",
|
||||
"scifb2_clk_c",
|
||||
"scifb2_data_d",
|
||||
};
|
||||
@ -5343,17 +5339,17 @@ static const char * const vin1_groups[] = {
|
||||
"vin1_field",
|
||||
"vin1_clkenb",
|
||||
"vin1_clk",
|
||||
"vin1_b_data24",
|
||||
"vin1_b_data20",
|
||||
"vin1_b_data18",
|
||||
"vin1_b_data16",
|
||||
"vin1_b_data12",
|
||||
"vin1_b_data10",
|
||||
"vin1_b_data8",
|
||||
"vin1_b_sync",
|
||||
"vin1_b_field",
|
||||
"vin1_b_clkenb",
|
||||
"vin1_b_clk",
|
||||
"vin1_data24_b",
|
||||
"vin1_data20_b",
|
||||
"vin1_data18_b",
|
||||
"vin1_data16_b",
|
||||
"vin1_data12_b",
|
||||
"vin1_data10_b",
|
||||
"vin1_data8_b",
|
||||
"vin1_sync_b",
|
||||
"vin1_field_b",
|
||||
"vin1_clkenb_b",
|
||||
"vin1_clk_b",
|
||||
};
|
||||
|
||||
static const char * const vin2_groups[] = {
|
||||
@ -5366,7 +5362,7 @@ static const char * const vin2_groups[] = {
|
||||
|
||||
static const struct {
|
||||
struct sh_pfc_function common[58];
|
||||
struct sh_pfc_function r8a779x[2];
|
||||
struct sh_pfc_function automotive[2];
|
||||
} pinmux_functions = {
|
||||
.common = {
|
||||
SH_PFC_FUNCTION(audio_clk),
|
||||
@ -5428,7 +5424,7 @@ static const struct {
|
||||
SH_PFC_FUNCTION(vin1),
|
||||
SH_PFC_FUNCTION(vin2),
|
||||
},
|
||||
.r8a779x = {
|
||||
.automotive = {
|
||||
SH_PFC_FUNCTION(adi),
|
||||
SH_PFC_FUNCTION(mlb),
|
||||
}
|
||||
@ -6635,6 +6631,28 @@ const struct sh_pfc_soc_info r8a7743_pinmux_info = {
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7744
|
||||
const struct sh_pfc_soc_info r8a7744_pinmux_info = {
|
||||
.name = "r8a77440_pfc",
|
||||
.ops = &r8a7791_pinmux_ops,
|
||||
.unlock_reg = 0xe6060000, /* PMMR */
|
||||
|
||||
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
|
||||
|
||||
.pins = pinmux_pins,
|
||||
.nr_pins = ARRAY_SIZE(pinmux_pins),
|
||||
.groups = pinmux_groups.common,
|
||||
.nr_groups = ARRAY_SIZE(pinmux_groups.common),
|
||||
.functions = pinmux_functions.common,
|
||||
.nr_functions = ARRAY_SIZE(pinmux_functions.common),
|
||||
|
||||
.cfg_regs = pinmux_config_regs,
|
||||
|
||||
.pinmux_data = pinmux_data,
|
||||
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A7791
|
||||
const struct sh_pfc_soc_info r8a7791_pinmux_info = {
|
||||
.name = "r8a77910_pfc",
|
||||
@ -6647,10 +6665,10 @@ const struct sh_pfc_soc_info r8a7791_pinmux_info = {
|
||||
.nr_pins = ARRAY_SIZE(pinmux_pins),
|
||||
.groups = pinmux_groups.common,
|
||||
.nr_groups = ARRAY_SIZE(pinmux_groups.common) +
|
||||
ARRAY_SIZE(pinmux_groups.r8a779x),
|
||||
ARRAY_SIZE(pinmux_groups.automotive),
|
||||
.functions = pinmux_functions.common,
|
||||
.nr_functions = ARRAY_SIZE(pinmux_functions.common) +
|
||||
ARRAY_SIZE(pinmux_functions.r8a779x),
|
||||
ARRAY_SIZE(pinmux_functions.automotive),
|
||||
|
||||
.cfg_regs = pinmux_config_regs,
|
||||
|
||||
@ -6671,10 +6689,10 @@ const struct sh_pfc_soc_info r8a7793_pinmux_info = {
|
||||
.nr_pins = ARRAY_SIZE(pinmux_pins),
|
||||
.groups = pinmux_groups.common,
|
||||
.nr_groups = ARRAY_SIZE(pinmux_groups.common) +
|
||||
ARRAY_SIZE(pinmux_groups.r8a779x),
|
||||
ARRAY_SIZE(pinmux_groups.automotive),
|
||||
.functions = pinmux_functions.common,
|
||||
.nr_functions = ARRAY_SIZE(pinmux_functions.common) +
|
||||
ARRAY_SIZE(pinmux_functions.r8a779x),
|
||||
ARRAY_SIZE(pinmux_functions.automotive),
|
||||
|
||||
.cfg_regs = pinmux_config_regs,
|
||||
|
||||
|
||||
@ -1477,7 +1477,7 @@ static const unsigned int vin1_clk_mux[] = {
|
||||
VI1_CLK_MARK,
|
||||
};
|
||||
/* - VIN2 ------------------------------------------------------------------- */
|
||||
static const union vin_data vin2_data_pins = {
|
||||
static const union vin_data16 vin2_data_pins = {
|
||||
.data16 = {
|
||||
RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
|
||||
RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
|
||||
@ -1489,7 +1489,7 @@ static const union vin_data vin2_data_pins = {
|
||||
RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
|
||||
},
|
||||
};
|
||||
static const union vin_data vin2_data_mux = {
|
||||
static const union vin_data16 vin2_data_mux = {
|
||||
.data16 = {
|
||||
VI2_D0_C0_MARK, VI2_D1_C1_MARK,
|
||||
VI2_D2_C2_MARK, VI2_D3_C3_MARK,
|
||||
@ -1527,7 +1527,7 @@ static const unsigned int vin2_clk_mux[] = {
|
||||
VI2_CLK_MARK,
|
||||
};
|
||||
/* - VIN3 ------------------------------------------------------------------- */
|
||||
static const union vin_data vin3_data_pins = {
|
||||
static const union vin_data16 vin3_data_pins = {
|
||||
.data16 = {
|
||||
RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
|
||||
RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
|
||||
@ -1539,7 +1539,7 @@ static const union vin_data vin3_data_pins = {
|
||||
RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16),
|
||||
},
|
||||
};
|
||||
static const union vin_data vin3_data_mux = {
|
||||
static const union vin_data16 vin3_data_mux = {
|
||||
.data16 = {
|
||||
VI3_D0_C0_MARK, VI3_D1_C1_MARK,
|
||||
VI3_D2_C2_MARK, VI3_D3_C3_MARK,
|
||||
@ -1577,7 +1577,7 @@ static const unsigned int vin3_clk_mux[] = {
|
||||
VI3_CLK_MARK,
|
||||
};
|
||||
/* - VIN4 ------------------------------------------------------------------- */
|
||||
static const union vin_data vin4_data_pins = {
|
||||
static const union vin_data12 vin4_data_pins = {
|
||||
.data12 = {
|
||||
RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
|
||||
RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
|
||||
@ -1587,7 +1587,7 @@ static const union vin_data vin4_data_pins = {
|
||||
RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15),
|
||||
},
|
||||
};
|
||||
static const union vin_data vin4_data_mux = {
|
||||
static const union vin_data12 vin4_data_mux = {
|
||||
.data12 = {
|
||||
VI4_D0_C0_MARK, VI4_D1_C1_MARK,
|
||||
VI4_D2_C2_MARK, VI4_D3_C3_MARK,
|
||||
@ -1623,7 +1623,7 @@ static const unsigned int vin4_clk_mux[] = {
|
||||
VI4_CLK_MARK,
|
||||
};
|
||||
/* - VIN5 ------------------------------------------------------------------- */
|
||||
static const union vin_data vin5_data_pins = {
|
||||
static const union vin_data12 vin5_data_pins = {
|
||||
.data12 = {
|
||||
RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
|
||||
RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
|
||||
@ -1633,7 +1633,7 @@ static const union vin_data vin5_data_pins = {
|
||||
RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15),
|
||||
},
|
||||
};
|
||||
static const union vin_data vin5_data_mux = {
|
||||
static const union vin_data12 vin5_data_mux = {
|
||||
.data12 = {
|
||||
VI5_D0_C0_MARK, VI5_D1_C1_MARK,
|
||||
VI5_D2_C2_MARK, VI5_D3_C3_MARK,
|
||||
@ -1747,10 +1747,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 12),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 8),
|
||||
VIN_DATA_PIN_GROUP(vin1_data_b, 24),
|
||||
VIN_DATA_PIN_GROUP(vin1_data_b, 20),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
|
||||
SH_PFC_PIN_GROUP(vin1_data18_b),
|
||||
VIN_DATA_PIN_GROUP(vin1_data_b, 16),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
|
||||
SH_PFC_PIN_GROUP(vin1_sync),
|
||||
SH_PFC_PIN_GROUP(vin1_field),
|
||||
SH_PFC_PIN_GROUP(vin1_clkenb),
|
||||
@ -1916,6 +1916,7 @@ static const char * const vin1_groups[] = {
|
||||
"vin1_data8",
|
||||
"vin1_data24_b",
|
||||
"vin1_data20_b",
|
||||
"vin1_data18_b",
|
||||
"vin1_data16_b",
|
||||
"vin1_sync",
|
||||
"vin1_field",
|
||||
|
||||
@ -3707,7 +3707,7 @@ static const unsigned int vin0_clk_mux[] = {
|
||||
VI0_CLK_MARK,
|
||||
};
|
||||
/* - VIN1 ------------------------------------------------------------------- */
|
||||
static const union vin_data vin1_data_pins = {
|
||||
static const union vin_data12 vin1_data_pins = {
|
||||
.data12 = {
|
||||
RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
|
||||
RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
|
||||
@ -3717,7 +3717,7 @@ static const union vin_data vin1_data_pins = {
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
|
||||
},
|
||||
};
|
||||
static const union vin_data vin1_data_mux = {
|
||||
static const union vin_data12 vin1_data_mux = {
|
||||
.data12 = {
|
||||
VI1_DATA0_MARK, VI1_DATA1_MARK,
|
||||
VI1_DATA2_MARK, VI1_DATA3_MARK,
|
||||
@ -5215,7 +5215,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, }
|
||||
},
|
||||
{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
|
||||
1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3, 3) {
|
||||
1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3) {
|
||||
/* IP9_31 [1] */
|
||||
0, 0,
|
||||
/* IP9_30_28 [3] */
|
||||
@ -5563,7 +5563,18 @@ static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int r8a7794_pinmux_soc_init(struct sh_pfc *pfc)
|
||||
{
|
||||
/* Initialize TDSEL on old revisions */
|
||||
if ((rmobile_get_cpu_rev_integer() == 1) &&
|
||||
(rmobile_get_cpu_rev_fraction() == 0))
|
||||
sh_pfc_write(pfc, 0xe6060068, 0x55555500);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = {
|
||||
.init = r8a7794_pinmux_soc_init,
|
||||
.pin_to_pocctrl = r8a7794_pin_to_pocctrl,
|
||||
};
|
||||
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
/*
|
||||
* R8A7795 ES2.0+ processor support - PFC hardware block.
|
||||
*
|
||||
* Copyright (C) 2015-2019 Renesas Electronics Corporation
|
||||
* Copyright (C) 2015-2017 Renesas Electronics Corporation
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
@ -202,8 +202,8 @@
|
||||
#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
|
||||
|
||||
/* GPSR7 */
|
||||
#define GPSR7_3 FM(GP7_03)
|
||||
#define GPSR7_2 FM(GP7_02)
|
||||
#define GPSR7_3 FM(HDMI1_CEC)
|
||||
#define GPSR7_2 FM(HDMI0_CEC)
|
||||
#define GPSR7_1 FM(AVS2)
|
||||
#define GPSR7_0 FM(AVS1)
|
||||
|
||||
@ -352,7 +352,7 @@
|
||||
#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
|
||||
#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
|
||||
#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
|
||||
@ -463,7 +463,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
|
||||
#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
|
||||
#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
|
||||
#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
|
||||
#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
|
||||
#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
|
||||
|
||||
/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
|
||||
#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
|
||||
@ -499,8 +499,8 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
|
||||
#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
|
||||
#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
|
||||
#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
|
||||
#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
|
||||
#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
|
||||
#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
|
||||
#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
|
||||
#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
|
||||
|
||||
#define PINMUX_MOD_SELS \
|
||||
@ -552,6 +552,9 @@ MOD_SEL0_4_3 MOD_SEL1_4 \
|
||||
FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
|
||||
FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
|
||||
|
||||
#define PINMUX_PHYS \
|
||||
FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
|
||||
|
||||
enum {
|
||||
PINMUX_RESERVED = 0,
|
||||
|
||||
@ -577,6 +580,7 @@ enum {
|
||||
PINMUX_IPSR
|
||||
PINMUX_MOD_SELS
|
||||
PINMUX_STATIC
|
||||
PINMUX_PHYS
|
||||
PINMUX_MARK_END,
|
||||
#undef F_
|
||||
#undef FM
|
||||
@ -588,11 +592,8 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_SINGLE(AVS1),
|
||||
PINMUX_SINGLE(AVS2),
|
||||
PINMUX_SINGLE(CLKOUT),
|
||||
PINMUX_SINGLE(GP7_02),
|
||||
PINMUX_SINGLE(GP7_03),
|
||||
PINMUX_SINGLE(I2C_SEL_0_1),
|
||||
PINMUX_SINGLE(I2C_SEL_3_1),
|
||||
PINMUX_SINGLE(I2C_SEL_5_1),
|
||||
PINMUX_SINGLE(HDMI0_CEC),
|
||||
PINMUX_SINGLE(HDMI1_CEC),
|
||||
PINMUX_SINGLE(MSIOF0_RXD),
|
||||
PINMUX_SINGLE(MSIOF0_SCK),
|
||||
PINMUX_SINGLE(MSIOF0_TXD),
|
||||
@ -616,14 +617,16 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
|
||||
PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
|
||||
PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
|
||||
PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
|
||||
PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
|
||||
PINMUX_IPSR_MSEL(IP0_19_16, FSCLKST2_N_A, I2C_SEL_5_0),
|
||||
PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
|
||||
PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
|
||||
PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
|
||||
PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
|
||||
PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
|
||||
@ -676,14 +679,16 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
|
||||
PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
|
||||
PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
|
||||
PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
|
||||
PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
|
||||
PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
|
||||
PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
|
||||
PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
|
||||
PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP1_31_28, A0),
|
||||
PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
|
||||
@ -1115,16 +1120,18 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
|
||||
PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
|
||||
PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
|
||||
PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
|
||||
PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
|
||||
PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
|
||||
PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
|
||||
PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
|
||||
PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
|
||||
|
||||
PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
|
||||
PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
|
||||
PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
|
||||
PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
|
||||
PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
|
||||
PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
|
||||
PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
|
||||
PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
|
||||
@ -1157,7 +1164,7 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
|
||||
PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
|
||||
PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
|
||||
PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
|
||||
PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
|
||||
PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
|
||||
PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
|
||||
PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
|
||||
@ -1216,7 +1223,7 @@ static const u16 pinmux_data[] = {
|
||||
|
||||
PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
|
||||
PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
|
||||
PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
|
||||
PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
|
||||
PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
|
||||
PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
|
||||
PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
|
||||
@ -1263,7 +1270,7 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
|
||||
PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
|
||||
PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
|
||||
PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
|
||||
PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
|
||||
PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
|
||||
PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
|
||||
PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
|
||||
@ -1272,7 +1279,7 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
|
||||
PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
|
||||
PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
|
||||
PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
|
||||
PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
|
||||
PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
|
||||
PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
|
||||
PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
|
||||
@ -1403,9 +1410,10 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
|
||||
|
||||
/* IPSR17 */
|
||||
PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
|
||||
PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
|
||||
PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
|
||||
PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
|
||||
PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
|
||||
PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
|
||||
PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
|
||||
@ -1491,10 +1499,10 @@ static const u16 pinmux_data[] = {
|
||||
|
||||
/*
|
||||
* Static pins can not be muxed between different functions but
|
||||
* still needs a mark entry in the pinmux list. Add each static
|
||||
* still need mark entries in the pinmux list. Add each static
|
||||
* pin to the list without an associated function. The sh-pfc
|
||||
* core will do the right thing and skip trying to mux then pin
|
||||
* while still applying configuration to it
|
||||
* core will do the right thing and skip trying to mux the pin
|
||||
* while still applying configuration to it.
|
||||
*/
|
||||
#define FM(x) PINMUX_DATA(x##_MARK, 0),
|
||||
PINMUX_STATIC
|
||||
@ -2125,23 +2133,20 @@ static const unsigned int du_disp_mux[] = {
|
||||
DU_DISP_MARK,
|
||||
};
|
||||
|
||||
/* - GP7_02/03 -------------------------------------------------------------- */
|
||||
static const unsigned int gp7_02_pins[] = {
|
||||
/* GP7_02 */
|
||||
/* - HDMI ------------------------------------------------------------------- */
|
||||
static const unsigned int hdmi0_cec_pins[] = {
|
||||
/* HDMI0_CEC */
|
||||
RCAR_GP_PIN(7, 2),
|
||||
};
|
||||
|
||||
static const unsigned int gp7_02_mux[] = {
|
||||
GP7_02_MARK,
|
||||
static const unsigned int hdmi0_cec_mux[] = {
|
||||
HDMI0_CEC_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int gp7_03_pins[] = {
|
||||
/* GP7_03 */
|
||||
static const unsigned int hdmi1_cec_pins[] = {
|
||||
/* HDMI1_CEC */
|
||||
RCAR_GP_PIN(7, 3),
|
||||
};
|
||||
|
||||
static const unsigned int gp7_03_mux[] = {
|
||||
GP7_03_MARK,
|
||||
static const unsigned int hdmi1_cec_mux[] = {
|
||||
HDMI1_CEC_MARK,
|
||||
};
|
||||
|
||||
/* - HSCIF0 ----------------------------------------------------------------- */
|
||||
@ -2352,6 +2357,15 @@ static const unsigned int hscif4_data_b_mux[] = {
|
||||
};
|
||||
|
||||
/* - I2C -------------------------------------------------------------------- */
|
||||
static const unsigned int i2c0_pins[] = {
|
||||
/* SCL, SDA */
|
||||
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
|
||||
};
|
||||
|
||||
static const unsigned int i2c0_mux[] = {
|
||||
SCL0_MARK, SDA0_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int i2c1_a_pins[] = {
|
||||
/* SDA, SCL */
|
||||
RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
|
||||
@ -2380,6 +2394,25 @@ static const unsigned int i2c2_b_pins[] = {
|
||||
static const unsigned int i2c2_b_mux[] = {
|
||||
SDA2_B_MARK, SCL2_B_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int i2c3_pins[] = {
|
||||
/* SCL, SDA */
|
||||
RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
|
||||
};
|
||||
|
||||
static const unsigned int i2c3_mux[] = {
|
||||
SCL3_MARK, SDA3_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int i2c5_pins[] = {
|
||||
/* SCL, SDA */
|
||||
RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
|
||||
};
|
||||
|
||||
static const unsigned int i2c5_mux[] = {
|
||||
SCL5_MARK, SDA5_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int i2c6_a_pins[] = {
|
||||
/* SDA, SCL */
|
||||
RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
|
||||
@ -3123,7 +3156,7 @@ static const unsigned int msiof3_ss1_e_mux[] = {
|
||||
MSIOF3_SS1_E_MARK,
|
||||
};
|
||||
static const unsigned int msiof3_ss2_e_pins[] = {
|
||||
/* SS1 */
|
||||
/* SS2 */
|
||||
RCAR_GP_PIN(2, 0),
|
||||
};
|
||||
static const unsigned int msiof3_ss2_e_mux[] = {
|
||||
@ -4067,67 +4100,29 @@ static const unsigned int vin4_clk_mux[] = {
|
||||
};
|
||||
|
||||
/* - VIN5 ------------------------------------------------------------------- */
|
||||
static const unsigned int vin5_data8_pins[] = {
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
static const union vin_data16 vin5_data_pins = {
|
||||
.data16 = {
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
|
||||
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
},
|
||||
};
|
||||
static const unsigned int vin5_data8_mux[] = {
|
||||
VI5_DATA0_MARK, VI5_DATA1_MARK,
|
||||
VI5_DATA2_MARK, VI5_DATA3_MARK,
|
||||
VI5_DATA4_MARK, VI5_DATA5_MARK,
|
||||
VI5_DATA6_MARK, VI5_DATA7_MARK,
|
||||
};
|
||||
static const unsigned int vin5_data10_pins[] = {
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
|
||||
};
|
||||
static const unsigned int vin5_data10_mux[] = {
|
||||
VI5_DATA0_MARK, VI5_DATA1_MARK,
|
||||
VI5_DATA2_MARK, VI5_DATA3_MARK,
|
||||
VI5_DATA4_MARK, VI5_DATA5_MARK,
|
||||
VI5_DATA6_MARK, VI5_DATA7_MARK,
|
||||
VI5_DATA8_MARK, VI5_DATA9_MARK,
|
||||
};
|
||||
static const unsigned int vin5_data12_pins[] = {
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
|
||||
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
|
||||
};
|
||||
static const unsigned int vin5_data12_mux[] = {
|
||||
VI5_DATA0_MARK, VI5_DATA1_MARK,
|
||||
VI5_DATA2_MARK, VI5_DATA3_MARK,
|
||||
VI5_DATA4_MARK, VI5_DATA5_MARK,
|
||||
VI5_DATA6_MARK, VI5_DATA7_MARK,
|
||||
VI5_DATA8_MARK, VI5_DATA9_MARK,
|
||||
VI5_DATA10_MARK, VI5_DATA11_MARK,
|
||||
};
|
||||
static const unsigned int vin5_data16_pins[] = {
|
||||
RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
|
||||
RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
|
||||
RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
|
||||
RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
|
||||
RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
|
||||
RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
|
||||
RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
|
||||
RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
|
||||
};
|
||||
static const unsigned int vin5_data16_mux[] = {
|
||||
VI5_DATA0_MARK, VI5_DATA1_MARK,
|
||||
VI5_DATA2_MARK, VI5_DATA3_MARK,
|
||||
VI5_DATA4_MARK, VI5_DATA5_MARK,
|
||||
VI5_DATA6_MARK, VI5_DATA7_MARK,
|
||||
VI5_DATA8_MARK, VI5_DATA9_MARK,
|
||||
VI5_DATA10_MARK, VI5_DATA11_MARK,
|
||||
VI5_DATA12_MARK, VI5_DATA13_MARK,
|
||||
VI5_DATA14_MARK, VI5_DATA15_MARK,
|
||||
static const union vin_data16 vin5_data_mux = {
|
||||
.data16 = {
|
||||
VI5_DATA0_MARK, VI5_DATA1_MARK,
|
||||
VI5_DATA2_MARK, VI5_DATA3_MARK,
|
||||
VI5_DATA4_MARK, VI5_DATA5_MARK,
|
||||
VI5_DATA6_MARK, VI5_DATA7_MARK,
|
||||
VI5_DATA8_MARK, VI5_DATA9_MARK,
|
||||
VI5_DATA10_MARK, VI5_DATA11_MARK,
|
||||
VI5_DATA12_MARK, VI5_DATA13_MARK,
|
||||
VI5_DATA14_MARK, VI5_DATA15_MARK,
|
||||
},
|
||||
};
|
||||
static const unsigned int vin5_sync_pins[] = {
|
||||
/* HSYNC#, VSYNC# */
|
||||
@ -4232,8 +4227,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(du_oddf),
|
||||
SH_PFC_PIN_GROUP(du_cde),
|
||||
SH_PFC_PIN_GROUP(du_disp),
|
||||
SH_PFC_PIN_GROUP(gp7_02),
|
||||
SH_PFC_PIN_GROUP(gp7_03),
|
||||
SH_PFC_PIN_GROUP(hdmi0_cec),
|
||||
SH_PFC_PIN_GROUP(hdmi1_cec),
|
||||
SH_PFC_PIN_GROUP(hscif0_data),
|
||||
SH_PFC_PIN_GROUP(hscif0_clk),
|
||||
SH_PFC_PIN_GROUP(hscif0_ctrl),
|
||||
@ -4262,10 +4257,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(hscif4_clk),
|
||||
SH_PFC_PIN_GROUP(hscif4_ctrl),
|
||||
SH_PFC_PIN_GROUP(hscif4_data_b),
|
||||
SH_PFC_PIN_GROUP(i2c0),
|
||||
SH_PFC_PIN_GROUP(i2c1_a),
|
||||
SH_PFC_PIN_GROUP(i2c1_b),
|
||||
SH_PFC_PIN_GROUP(i2c2_a),
|
||||
SH_PFC_PIN_GROUP(i2c2_b),
|
||||
SH_PFC_PIN_GROUP(i2c3),
|
||||
SH_PFC_PIN_GROUP(i2c5),
|
||||
SH_PFC_PIN_GROUP(i2c6_a),
|
||||
SH_PFC_PIN_GROUP(i2c6_b),
|
||||
SH_PFC_PIN_GROUP(i2c6_c),
|
||||
@ -4478,28 +4476,28 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(usb2),
|
||||
SH_PFC_PIN_GROUP(usb2_ch3),
|
||||
SH_PFC_PIN_GROUP(usb30),
|
||||
VIN_DATA_PIN_GROUP(vin4_data_a, 8),
|
||||
VIN_DATA_PIN_GROUP(vin4_data_a, 10),
|
||||
VIN_DATA_PIN_GROUP(vin4_data_a, 12),
|
||||
VIN_DATA_PIN_GROUP(vin4_data_a, 16),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
|
||||
SH_PFC_PIN_GROUP(vin4_data18_a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data_a, 20),
|
||||
VIN_DATA_PIN_GROUP(vin4_data_a, 24),
|
||||
VIN_DATA_PIN_GROUP(vin4_data_b, 8),
|
||||
VIN_DATA_PIN_GROUP(vin4_data_b, 10),
|
||||
VIN_DATA_PIN_GROUP(vin4_data_b, 12),
|
||||
VIN_DATA_PIN_GROUP(vin4_data_b, 16),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
|
||||
SH_PFC_PIN_GROUP(vin4_data18_b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data_b, 20),
|
||||
VIN_DATA_PIN_GROUP(vin4_data_b, 24),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
|
||||
VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
|
||||
SH_PFC_PIN_GROUP(vin4_sync),
|
||||
SH_PFC_PIN_GROUP(vin4_field),
|
||||
SH_PFC_PIN_GROUP(vin4_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin4_clk),
|
||||
SH_PFC_PIN_GROUP(vin5_data8),
|
||||
SH_PFC_PIN_GROUP(vin5_data10),
|
||||
SH_PFC_PIN_GROUP(vin5_data12),
|
||||
SH_PFC_PIN_GROUP(vin5_data16),
|
||||
VIN_DATA_PIN_GROUP(vin5_data, 8),
|
||||
VIN_DATA_PIN_GROUP(vin5_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin5_data, 12),
|
||||
VIN_DATA_PIN_GROUP(vin5_data, 16),
|
||||
SH_PFC_PIN_GROUP(vin5_sync),
|
||||
SH_PFC_PIN_GROUP(vin5_field),
|
||||
SH_PFC_PIN_GROUP(vin5_clkenb),
|
||||
@ -4615,12 +4613,12 @@ static const char * const du_groups[] = {
|
||||
"du_disp",
|
||||
};
|
||||
|
||||
static const char * const gp7_02_groups[] = {
|
||||
"gp7_02",
|
||||
static const char * const hdmi0_groups[] = {
|
||||
"hdmi0_cec",
|
||||
};
|
||||
|
||||
static const char * const gp7_03_groups[] = {
|
||||
"gp7_03",
|
||||
static const char * const hdmi1_groups[] = {
|
||||
"hdmi1_cec",
|
||||
};
|
||||
|
||||
static const char * const hscif0_groups[] = {
|
||||
@ -4666,6 +4664,10 @@ static const char * const hscif4_groups[] = {
|
||||
"hscif4_data_b",
|
||||
};
|
||||
|
||||
static const char * const i2c0_groups[] = {
|
||||
"i2c0",
|
||||
};
|
||||
|
||||
static const char * const i2c1_groups[] = {
|
||||
"i2c1_a",
|
||||
"i2c1_b",
|
||||
@ -4676,6 +4678,14 @@ static const char * const i2c2_groups[] = {
|
||||
"i2c2_b",
|
||||
};
|
||||
|
||||
static const char * const i2c3_groups[] = {
|
||||
"i2c3",
|
||||
};
|
||||
|
||||
static const char * const i2c5_groups[] = {
|
||||
"i2c5",
|
||||
};
|
||||
|
||||
static const char * const i2c6_groups[] = {
|
||||
"i2c6_a",
|
||||
"i2c6_b",
|
||||
@ -5029,15 +5039,18 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
||||
SH_PFC_FUNCTION(drif2),
|
||||
SH_PFC_FUNCTION(drif3),
|
||||
SH_PFC_FUNCTION(du),
|
||||
SH_PFC_FUNCTION(gp7_02),
|
||||
SH_PFC_FUNCTION(gp7_03),
|
||||
SH_PFC_FUNCTION(hdmi0),
|
||||
SH_PFC_FUNCTION(hdmi1),
|
||||
SH_PFC_FUNCTION(hscif0),
|
||||
SH_PFC_FUNCTION(hscif1),
|
||||
SH_PFC_FUNCTION(hscif2),
|
||||
SH_PFC_FUNCTION(hscif3),
|
||||
SH_PFC_FUNCTION(hscif4),
|
||||
SH_PFC_FUNCTION(i2c0),
|
||||
SH_PFC_FUNCTION(i2c1),
|
||||
SH_PFC_FUNCTION(i2c2),
|
||||
SH_PFC_FUNCTION(i2c3),
|
||||
SH_PFC_FUNCTION(i2c5),
|
||||
SH_PFC_FUNCTION(i2c6),
|
||||
SH_PFC_FUNCTION(intc_ex),
|
||||
SH_PFC_FUNCTION(msiof0),
|
||||
@ -5751,8 +5764,8 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
|
||||
{ RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
|
||||
{ RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
|
||||
{ RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
|
||||
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
|
||||
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
|
||||
{ RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
|
||||
{ RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
|
||||
{ PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
|
||||
{ PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
|
||||
} },
|
||||
@ -6006,8 +6019,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
|
||||
[25] = RCAR_GP_PIN(0, 15), /* D15 */
|
||||
[26] = RCAR_GP_PIN(7, 0), /* AVS1 */
|
||||
[27] = RCAR_GP_PIN(7, 1), /* AVS2 */
|
||||
[28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
|
||||
[29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
|
||||
[28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
|
||||
[29] = RCAR_GP_PIN(7, 3), /* HDMI1_CEC */
|
||||
[30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
|
||||
[31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
|
||||
} },
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
6350
drivers/pinctrl/renesas/pfc-r8a77965.c
Normal file
6350
drivers/pinctrl/renesas/pfc-r8a77965.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -3,6 +3,7 @@
|
||||
* R8A77970 processor support - PFC hardware block.
|
||||
*
|
||||
* Copyright (C) 2016 Renesas Electronics Corp.
|
||||
* Copyright (C) 2017 Cogent Embedded, Inc. <source@cogentembedded.com>
|
||||
*
|
||||
* This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
|
||||
*
|
||||
@ -20,12 +21,12 @@
|
||||
#include "sh_pfc.h"
|
||||
|
||||
#define CPU_ALL_PORT(fn, sfx) \
|
||||
PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
|
||||
PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
|
||||
PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
|
||||
PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
|
||||
PORT_GP_CFG_6(4, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
|
||||
PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH)
|
||||
PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_28(1, fn, sfx), \
|
||||
PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
|
||||
PORT_GP_6(4, fn, sfx), \
|
||||
PORT_GP_15(5, fn, sfx)
|
||||
/*
|
||||
* F_() : just information
|
||||
* FM() : macro for FN_xxx / xxx_MARK
|
||||
@ -1383,6 +1384,56 @@ static const unsigned int pwm4_b_mux[] = {
|
||||
PWM4_B_MARK,
|
||||
};
|
||||
|
||||
/* - QSPI0 ------------------------------------------------------------------ */
|
||||
static const unsigned int qspi0_ctrl_pins[] = {
|
||||
/* SPCLK, SSL */
|
||||
RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5),
|
||||
};
|
||||
static const unsigned int qspi0_ctrl_mux[] = {
|
||||
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data2_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1 */
|
||||
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
|
||||
};
|
||||
static const unsigned int qspi0_data2_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi0_data4_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
|
||||
RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
|
||||
RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
|
||||
};
|
||||
static const unsigned int qspi0_data4_mux[] = {
|
||||
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
|
||||
QSPI0_IO2_MARK, QSPI0_IO3_MARK
|
||||
};
|
||||
|
||||
/* - QSPI1 ------------------------------------------------------------------ */
|
||||
static const unsigned int qspi1_ctrl_pins[] = {
|
||||
/* SPCLK, SSL */
|
||||
RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11),
|
||||
};
|
||||
static const unsigned int qspi1_ctrl_mux[] = {
|
||||
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data2_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1 */
|
||||
RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
|
||||
};
|
||||
static const unsigned int qspi1_data2_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
};
|
||||
static const unsigned int qspi1_data4_pins[] = {
|
||||
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
|
||||
RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
|
||||
RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
|
||||
};
|
||||
static const unsigned int qspi1_data4_mux[] = {
|
||||
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
|
||||
QSPI1_IO2_MARK, QSPI1_IO3_MARK
|
||||
};
|
||||
|
||||
/* - SCIF Clock ------------------------------------------------------------- */
|
||||
static const unsigned int scif_clk_a_pins[] = {
|
||||
/* SCIF_CLK */
|
||||
@ -1529,47 +1580,25 @@ static const unsigned int tmu_tclk2_b_mux[] = {
|
||||
};
|
||||
|
||||
/* - VIN0 ------------------------------------------------------------------- */
|
||||
static const unsigned int vin0_data8_pins[] = {
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
|
||||
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
|
||||
static const union vin_data12 vin0_data_pins = {
|
||||
.data12 = {
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
|
||||
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
|
||||
RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
|
||||
RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
|
||||
},
|
||||
};
|
||||
static const unsigned int vin0_data8_mux[] = {
|
||||
VI0_DATA0_MARK, VI0_DATA1_MARK,
|
||||
VI0_DATA2_MARK, VI0_DATA3_MARK,
|
||||
VI0_DATA4_MARK, VI0_DATA5_MARK,
|
||||
VI0_DATA6_MARK, VI0_DATA7_MARK,
|
||||
};
|
||||
static const unsigned int vin0_data10_pins[] = {
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
|
||||
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
|
||||
RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
|
||||
};
|
||||
static const unsigned int vin0_data10_mux[] = {
|
||||
VI0_DATA0_MARK, VI0_DATA1_MARK,
|
||||
VI0_DATA2_MARK, VI0_DATA3_MARK,
|
||||
VI0_DATA4_MARK, VI0_DATA5_MARK,
|
||||
VI0_DATA6_MARK, VI0_DATA7_MARK,
|
||||
VI0_DATA8_MARK, VI0_DATA9_MARK,
|
||||
};
|
||||
static const unsigned int vin0_data12_pins[] = {
|
||||
RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
|
||||
RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
|
||||
RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
|
||||
RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
|
||||
RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
|
||||
RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
|
||||
};
|
||||
static const unsigned int vin0_data12_mux[] = {
|
||||
VI0_DATA0_MARK, VI0_DATA1_MARK,
|
||||
VI0_DATA2_MARK, VI0_DATA3_MARK,
|
||||
VI0_DATA4_MARK, VI0_DATA5_MARK,
|
||||
VI0_DATA6_MARK, VI0_DATA7_MARK,
|
||||
VI0_DATA8_MARK, VI0_DATA9_MARK,
|
||||
VI0_DATA10_MARK, VI0_DATA11_MARK,
|
||||
static const union vin_data12 vin0_data_mux = {
|
||||
.data12 = {
|
||||
VI0_DATA0_MARK, VI0_DATA1_MARK,
|
||||
VI0_DATA2_MARK, VI0_DATA3_MARK,
|
||||
VI0_DATA4_MARK, VI0_DATA5_MARK,
|
||||
VI0_DATA6_MARK, VI0_DATA7_MARK,
|
||||
VI0_DATA8_MARK, VI0_DATA9_MARK,
|
||||
VI0_DATA10_MARK, VI0_DATA11_MARK,
|
||||
},
|
||||
};
|
||||
static const unsigned int vin0_sync_pins[] = {
|
||||
/* HSYNC#, VSYNC# */
|
||||
@ -1601,47 +1630,25 @@ static const unsigned int vin0_clk_mux[] = {
|
||||
};
|
||||
|
||||
/* - VIN1 ------------------------------------------------------------------- */
|
||||
static const unsigned int vin1_data8_pins[] = {
|
||||
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
|
||||
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
|
||||
static const union vin_data12 vin1_data_pins = {
|
||||
.data12 = {
|
||||
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
|
||||
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
|
||||
RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
|
||||
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
|
||||
},
|
||||
};
|
||||
static const unsigned int vin1_data8_mux[] = {
|
||||
VI1_DATA0_MARK, VI1_DATA1_MARK,
|
||||
VI1_DATA2_MARK, VI1_DATA3_MARK,
|
||||
VI1_DATA4_MARK, VI1_DATA5_MARK,
|
||||
VI1_DATA6_MARK, VI1_DATA7_MARK,
|
||||
};
|
||||
static const unsigned int vin1_data10_pins[] = {
|
||||
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
|
||||
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
|
||||
RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
|
||||
};
|
||||
static const unsigned int vin1_data10_mux[] = {
|
||||
VI1_DATA0_MARK, VI1_DATA1_MARK,
|
||||
VI1_DATA2_MARK, VI1_DATA3_MARK,
|
||||
VI1_DATA4_MARK, VI1_DATA5_MARK,
|
||||
VI1_DATA6_MARK, VI1_DATA7_MARK,
|
||||
VI1_DATA8_MARK, VI1_DATA9_MARK,
|
||||
};
|
||||
static const unsigned int vin1_data12_pins[] = {
|
||||
RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
|
||||
RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
|
||||
RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
|
||||
RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
|
||||
RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
|
||||
RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
|
||||
};
|
||||
static const unsigned int vin1_data12_mux[] = {
|
||||
VI1_DATA0_MARK, VI1_DATA1_MARK,
|
||||
VI1_DATA2_MARK, VI1_DATA3_MARK,
|
||||
VI1_DATA4_MARK, VI1_DATA5_MARK,
|
||||
VI1_DATA6_MARK, VI1_DATA7_MARK,
|
||||
VI1_DATA8_MARK, VI1_DATA9_MARK,
|
||||
VI1_DATA10_MARK, VI1_DATA11_MARK,
|
||||
static const union vin_data12 vin1_data_mux = {
|
||||
.data12 = {
|
||||
VI1_DATA0_MARK, VI1_DATA1_MARK,
|
||||
VI1_DATA2_MARK, VI1_DATA3_MARK,
|
||||
VI1_DATA4_MARK, VI1_DATA5_MARK,
|
||||
VI1_DATA6_MARK, VI1_DATA7_MARK,
|
||||
VI1_DATA8_MARK, VI1_DATA9_MARK,
|
||||
VI1_DATA10_MARK, VI1_DATA11_MARK,
|
||||
},
|
||||
};
|
||||
static const unsigned int vin1_sync_pins[] = {
|
||||
/* HSYNC#, VSYNC# */
|
||||
@ -1757,6 +1764,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(pwm3_b),
|
||||
SH_PFC_PIN_GROUP(pwm4_a),
|
||||
SH_PFC_PIN_GROUP(pwm4_b),
|
||||
SH_PFC_PIN_GROUP(qspi0_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi0_data2),
|
||||
SH_PFC_PIN_GROUP(qspi0_data4),
|
||||
SH_PFC_PIN_GROUP(qspi1_ctrl),
|
||||
SH_PFC_PIN_GROUP(qspi1_data2),
|
||||
SH_PFC_PIN_GROUP(qspi1_data4),
|
||||
SH_PFC_PIN_GROUP(scif_clk_a),
|
||||
SH_PFC_PIN_GROUP(scif_clk_b),
|
||||
SH_PFC_PIN_GROUP(scif0_data),
|
||||
@ -1776,16 +1789,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(tmu_tclk1_b),
|
||||
SH_PFC_PIN_GROUP(tmu_tclk2_a),
|
||||
SH_PFC_PIN_GROUP(tmu_tclk2_b),
|
||||
SH_PFC_PIN_GROUP(vin0_data8),
|
||||
SH_PFC_PIN_GROUP(vin0_data10),
|
||||
SH_PFC_PIN_GROUP(vin0_data12),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 8),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin0_data, 12),
|
||||
SH_PFC_PIN_GROUP(vin0_sync),
|
||||
SH_PFC_PIN_GROUP(vin0_field),
|
||||
SH_PFC_PIN_GROUP(vin0_clkenb),
|
||||
SH_PFC_PIN_GROUP(vin0_clk),
|
||||
SH_PFC_PIN_GROUP(vin1_data8),
|
||||
SH_PFC_PIN_GROUP(vin1_data10),
|
||||
SH_PFC_PIN_GROUP(vin1_data12),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 8),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 10),
|
||||
VIN_DATA_PIN_GROUP(vin1_data, 12),
|
||||
SH_PFC_PIN_GROUP(vin1_sync),
|
||||
SH_PFC_PIN_GROUP(vin1_field),
|
||||
SH_PFC_PIN_GROUP(vin1_clkenb),
|
||||
@ -1951,6 +1964,18 @@ static const char * const pwm4_groups[] = {
|
||||
"pwm4_b",
|
||||
};
|
||||
|
||||
static const char * const qspi0_groups[] = {
|
||||
"qspi0_ctrl",
|
||||
"qspi0_data2",
|
||||
"qspi0_data4",
|
||||
};
|
||||
|
||||
static const char * const qspi1_groups[] = {
|
||||
"qspi1_ctrl",
|
||||
"qspi1_data2",
|
||||
"qspi1_data4",
|
||||
};
|
||||
|
||||
static const char * const scif_clk_groups[] = {
|
||||
"scif_clk_a",
|
||||
"scif_clk_b",
|
||||
@ -2034,6 +2059,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
||||
SH_PFC_FUNCTION(pwm2),
|
||||
SH_PFC_FUNCTION(pwm3),
|
||||
SH_PFC_FUNCTION(pwm4),
|
||||
SH_PFC_FUNCTION(qspi0),
|
||||
SH_PFC_FUNCTION(qspi1),
|
||||
SH_PFC_FUNCTION(scif_clk),
|
||||
SH_PFC_FUNCTION(scif0),
|
||||
SH_PFC_FUNCTION(scif1),
|
||||
@ -2352,7 +2379,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
#define F_(x, y) x,
|
||||
#define FM(x) FN_##x,
|
||||
{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
|
||||
4, 4, 4, 4,
|
||||
4, 4, 4, 4, 4,
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
|
||||
/* RESERVED 31, 30, 29, 28 */
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
@ -2380,18 +2407,31 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
|
||||
{ },
|
||||
};
|
||||
|
||||
enum ioctrl_regs {
|
||||
IOCTRL30,
|
||||
IOCTRL31,
|
||||
IOCTRL32,
|
||||
};
|
||||
|
||||
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
|
||||
[IOCTRL30] = { 0xe6060380 },
|
||||
[IOCTRL31] = { 0xe6060384 },
|
||||
[IOCTRL32] = { 0xe6060388 },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
|
||||
u32 *pocctrl)
|
||||
{
|
||||
int bit = pin & 0x1f;
|
||||
|
||||
*pocctrl = 0xe6060380;
|
||||
*pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg;
|
||||
if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
|
||||
return bit;
|
||||
if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
|
||||
return bit + 22;
|
||||
|
||||
*pocctrl += 4;
|
||||
*pocctrl = pinmux_ioctrl_regs[IOCTRL31].reg;
|
||||
if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
|
||||
return bit - 10;
|
||||
if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
|
||||
@ -2419,6 +2459,7 @@ const struct sh_pfc_soc_info r8a77970_pinmux_info = {
|
||||
.nr_functions = ARRAY_SIZE(pinmux_functions),
|
||||
|
||||
.cfg_regs = pinmux_config_regs,
|
||||
.ioctrl_regs = pinmux_ioctrl_regs,
|
||||
|
||||
.pinmux_data = pinmux_data,
|
||||
.pinmux_data_size = ARRAY_SIZE(pinmux_data),
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -384,6 +384,9 @@ FM(IP12_23_20) IP12_23_20 \
|
||||
FM(IP12_27_24) IP12_27_24 \
|
||||
FM(IP12_31_28) IP12_31_28 \
|
||||
|
||||
/* The bit numbering in MOD_SEL fields is reversed */
|
||||
#define REV4(f0, f1, f2, f3) f0 f2 f1 f3
|
||||
|
||||
/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
|
||||
#define MOD_SEL0_30 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1)
|
||||
#define MOD_SEL0_29 FM(SEL_I2C3_0) FM(SEL_I2C3_1)
|
||||
@ -391,10 +394,10 @@ FM(IP12_31_28) IP12_31_28 \
|
||||
#define MOD_SEL0_27 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1)
|
||||
#define MOD_SEL0_26 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1)
|
||||
#define MOD_SEL0_25 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1)
|
||||
#define MOD_SEL0_24_23 FM(SEL_PWM0_0) FM(SEL_PWM0_1) FM(SEL_PWM0_2) FM(SEL_PWM0_3)
|
||||
#define MOD_SEL0_22_21 FM(SEL_PWM1_0) FM(SEL_PWM1_1) FM(SEL_PWM1_2) FM(SEL_PWM1_3)
|
||||
#define MOD_SEL0_20_19 FM(SEL_PWM2_0) FM(SEL_PWM2_1) FM(SEL_PWM2_2) FM(SEL_PWM2_3)
|
||||
#define MOD_SEL0_18_17 FM(SEL_PWM3_0) FM(SEL_PWM3_1) FM(SEL_PWM3_2) FM(SEL_PWM3_3)
|
||||
#define MOD_SEL0_24_23 REV4(FM(SEL_PWM0_0), FM(SEL_PWM0_1), FM(SEL_PWM0_2), F_(0, 0))
|
||||
#define MOD_SEL0_22_21 REV4(FM(SEL_PWM1_0), FM(SEL_PWM1_1), FM(SEL_PWM1_2), F_(0, 0))
|
||||
#define MOD_SEL0_20_19 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0))
|
||||
#define MOD_SEL0_18_17 REV4(FM(SEL_PWM3_0), FM(SEL_PWM3_1), FM(SEL_PWM3_2), F_(0, 0))
|
||||
#define MOD_SEL0_15 FM(SEL_IRQ_0_0) FM(SEL_IRQ_0_1)
|
||||
#define MOD_SEL0_14 FM(SEL_IRQ_1_0) FM(SEL_IRQ_1_1)
|
||||
#define MOD_SEL0_13 FM(SEL_IRQ_2_0) FM(SEL_IRQ_2_1)
|
||||
@ -471,12 +474,6 @@ enum {
|
||||
#undef FM
|
||||
};
|
||||
|
||||
#define PINMUX_IPSR_MSEL2(ipsr, fn, msel1, msel2) \
|
||||
PINMUX_DATA(fn##_MARK, FN_##msel1, FN_##msel2, FN_##fn, FN_##ipsr)
|
||||
|
||||
#define PINMUX_IPSR_PHYS(ipsr, fn, msel) \
|
||||
PINMUX_DATA(fn##_MARK, FN_##msel)
|
||||
|
||||
static const u16 pinmux_data[] = {
|
||||
PINMUX_DATA_GP_ALL(),
|
||||
|
||||
@ -520,6 +517,10 @@ static const u16 pinmux_data[] = {
|
||||
PINMUX_SINGLE(QSPI0_SPCLK),
|
||||
PINMUX_SINGLE(SCL0),
|
||||
PINMUX_SINGLE(SDA0),
|
||||
PINMUX_SINGLE(MSIOF0_RXD),
|
||||
PINMUX_SINGLE(MSIOF0_TXD),
|
||||
PINMUX_SINGLE(MSIOF0_SYNC),
|
||||
PINMUX_SINGLE(MSIOF0_SCK),
|
||||
|
||||
/* IPSR0 */
|
||||
PINMUX_IPSR_MSEL(IP0_3_0, IRQ0_A, SEL_IRQ_0_0),
|
||||
@ -1277,6 +1278,289 @@ static const unsigned int mmc_ctrl_mux[] = {
|
||||
MMC_CLK_MARK, MMC_CMD_MARK,
|
||||
};
|
||||
|
||||
/* - MSIOF0 ----------------------------------------------------------------- */
|
||||
static const unsigned int msiof0_clk_pins[] = {
|
||||
/* SCK */
|
||||
RCAR_GP_PIN(4, 12),
|
||||
};
|
||||
|
||||
static const unsigned int msiof0_clk_mux[] = {
|
||||
MSIOF0_SCK_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof0_sync_pins[] = {
|
||||
/* SYNC */
|
||||
RCAR_GP_PIN(4, 13),
|
||||
};
|
||||
|
||||
static const unsigned int msiof0_sync_mux[] = {
|
||||
MSIOF0_SYNC_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof0_ss1_pins[] = {
|
||||
/* SS1 */
|
||||
RCAR_GP_PIN(4, 20),
|
||||
};
|
||||
|
||||
static const unsigned int msiof0_ss1_mux[] = {
|
||||
MSIOF0_SS1_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof0_ss2_pins[] = {
|
||||
/* SS2 */
|
||||
RCAR_GP_PIN(4, 21),
|
||||
};
|
||||
|
||||
static const unsigned int msiof0_ss2_mux[] = {
|
||||
MSIOF0_SS2_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof0_txd_pins[] = {
|
||||
/* TXD */
|
||||
RCAR_GP_PIN(4, 14),
|
||||
};
|
||||
|
||||
static const unsigned int msiof0_txd_mux[] = {
|
||||
MSIOF0_TXD_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof0_rxd_pins[] = {
|
||||
/* RXD */
|
||||
RCAR_GP_PIN(4, 15),
|
||||
};
|
||||
|
||||
static const unsigned int msiof0_rxd_mux[] = {
|
||||
MSIOF0_RXD_MARK,
|
||||
};
|
||||
|
||||
/* - MSIOF1 ----------------------------------------------------------------- */
|
||||
static const unsigned int msiof1_clk_pins[] = {
|
||||
/* SCK */
|
||||
RCAR_GP_PIN(4, 16),
|
||||
};
|
||||
|
||||
static const unsigned int msiof1_clk_mux[] = {
|
||||
MSIOF1_SCK_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof1_sync_pins[] = {
|
||||
/* SYNC */
|
||||
RCAR_GP_PIN(4, 19),
|
||||
};
|
||||
|
||||
static const unsigned int msiof1_sync_mux[] = {
|
||||
MSIOF1_SYNC_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof1_ss1_pins[] = {
|
||||
/* SS1 */
|
||||
RCAR_GP_PIN(4, 25),
|
||||
};
|
||||
|
||||
static const unsigned int msiof1_ss1_mux[] = {
|
||||
MSIOF1_SS1_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof1_ss2_pins[] = {
|
||||
/* SS2 */
|
||||
RCAR_GP_PIN(4, 22),
|
||||
};
|
||||
|
||||
static const unsigned int msiof1_ss2_mux[] = {
|
||||
MSIOF1_SS2_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof1_txd_pins[] = {
|
||||
/* TXD */
|
||||
RCAR_GP_PIN(4, 17),
|
||||
};
|
||||
|
||||
static const unsigned int msiof1_txd_mux[] = {
|
||||
MSIOF1_TXD_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof1_rxd_pins[] = {
|
||||
/* RXD */
|
||||
RCAR_GP_PIN(4, 18),
|
||||
};
|
||||
|
||||
static const unsigned int msiof1_rxd_mux[] = {
|
||||
MSIOF1_RXD_MARK,
|
||||
};
|
||||
|
||||
/* - MSIOF2 ----------------------------------------------------------------- */
|
||||
static const unsigned int msiof2_clk_pins[] = {
|
||||
/* SCK */
|
||||
RCAR_GP_PIN(0, 3),
|
||||
};
|
||||
|
||||
static const unsigned int msiof2_clk_mux[] = {
|
||||
MSIOF2_SCK_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof2_sync_a_pins[] = {
|
||||
/* SYNC */
|
||||
RCAR_GP_PIN(0, 6),
|
||||
};
|
||||
|
||||
static const unsigned int msiof2_sync_a_mux[] = {
|
||||
MSIOF2_SYNC_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof2_sync_b_pins[] = {
|
||||
/* SYNC */
|
||||
RCAR_GP_PIN(0, 2),
|
||||
};
|
||||
|
||||
static const unsigned int msiof2_sync_b_mux[] = {
|
||||
MSIOF2_SYNC_B_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof2_ss1_pins[] = {
|
||||
/* SS1 */
|
||||
RCAR_GP_PIN(0, 7),
|
||||
};
|
||||
|
||||
static const unsigned int msiof2_ss1_mux[] = {
|
||||
MSIOF2_SS1_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof2_ss2_pins[] = {
|
||||
/* SS2 */
|
||||
RCAR_GP_PIN(0, 8),
|
||||
};
|
||||
|
||||
static const unsigned int msiof2_ss2_mux[] = {
|
||||
MSIOF2_SS2_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof2_txd_pins[] = {
|
||||
/* TXD */
|
||||
RCAR_GP_PIN(0, 4),
|
||||
};
|
||||
|
||||
static const unsigned int msiof2_txd_mux[] = {
|
||||
MSIOF2_TXD_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof2_rxd_pins[] = {
|
||||
/* RXD */
|
||||
RCAR_GP_PIN(0, 5),
|
||||
};
|
||||
|
||||
static const unsigned int msiof2_rxd_mux[] = {
|
||||
MSIOF2_RXD_MARK,
|
||||
};
|
||||
|
||||
/* - MSIOF3 ----------------------------------------------------------------- */
|
||||
static const unsigned int msiof3_clk_a_pins[] = {
|
||||
/* SCK */
|
||||
RCAR_GP_PIN(2, 24),
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_clk_a_mux[] = {
|
||||
MSIOF3_SCK_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_sync_a_pins[] = {
|
||||
/* SYNC */
|
||||
RCAR_GP_PIN(2, 21),
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_sync_a_mux[] = {
|
||||
MSIOF3_SYNC_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_ss1_a_pins[] = {
|
||||
/* SS1 */
|
||||
RCAR_GP_PIN(2, 14),
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_ss1_a_mux[] = {
|
||||
MSIOF3_SS1_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_ss2_a_pins[] = {
|
||||
/* SS2 */
|
||||
RCAR_GP_PIN(2, 10),
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_ss2_a_mux[] = {
|
||||
MSIOF3_SS2_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_txd_a_pins[] = {
|
||||
/* TXD */
|
||||
RCAR_GP_PIN(2, 22),
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_txd_a_mux[] = {
|
||||
MSIOF3_TXD_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_rxd_a_pins[] = {
|
||||
/* RXD */
|
||||
RCAR_GP_PIN(2, 23),
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_rxd_a_mux[] = {
|
||||
MSIOF3_RXD_A_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_clk_b_pins[] = {
|
||||
/* SCK */
|
||||
RCAR_GP_PIN(1, 8),
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_clk_b_mux[] = {
|
||||
MSIOF3_SCK_B_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_sync_b_pins[] = {
|
||||
/* SYNC */
|
||||
RCAR_GP_PIN(1, 9),
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_sync_b_mux[] = {
|
||||
MSIOF3_SYNC_B_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_ss1_b_pins[] = {
|
||||
/* SS1 */
|
||||
RCAR_GP_PIN(1, 6),
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_ss1_b_mux[] = {
|
||||
MSIOF3_SS1_B_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_ss2_b_pins[] = {
|
||||
/* SS2 */
|
||||
RCAR_GP_PIN(1, 7),
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_ss2_b_mux[] = {
|
||||
MSIOF3_SS2_B_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_txd_b_pins[] = {
|
||||
/* TXD */
|
||||
RCAR_GP_PIN(1, 0),
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_txd_b_mux[] = {
|
||||
MSIOF3_TXD_B_MARK,
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_rxd_b_pins[] = {
|
||||
/* RXD */
|
||||
RCAR_GP_PIN(1, 1),
|
||||
};
|
||||
|
||||
static const unsigned int msiof3_rxd_b_mux[] = {
|
||||
MSIOF3_RXD_B_MARK,
|
||||
};
|
||||
|
||||
/* - PWM0 ------------------------------------------------------------------ */
|
||||
static const unsigned int pwm0_a_pins[] = {
|
||||
/* PWM */
|
||||
@ -1752,6 +2036,37 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
|
||||
SH_PFC_PIN_GROUP(mmc_data4),
|
||||
SH_PFC_PIN_GROUP(mmc_data8),
|
||||
SH_PFC_PIN_GROUP(mmc_ctrl),
|
||||
SH_PFC_PIN_GROUP(msiof0_clk),
|
||||
SH_PFC_PIN_GROUP(msiof0_sync),
|
||||
SH_PFC_PIN_GROUP(msiof0_ss1),
|
||||
SH_PFC_PIN_GROUP(msiof0_ss2),
|
||||
SH_PFC_PIN_GROUP(msiof0_txd),
|
||||
SH_PFC_PIN_GROUP(msiof0_rxd),
|
||||
SH_PFC_PIN_GROUP(msiof1_clk),
|
||||
SH_PFC_PIN_GROUP(msiof1_sync),
|
||||
SH_PFC_PIN_GROUP(msiof1_ss1),
|
||||
SH_PFC_PIN_GROUP(msiof1_ss2),
|
||||
SH_PFC_PIN_GROUP(msiof1_txd),
|
||||
SH_PFC_PIN_GROUP(msiof1_rxd),
|
||||
SH_PFC_PIN_GROUP(msiof2_clk),
|
||||
SH_PFC_PIN_GROUP(msiof2_sync_a),
|
||||
SH_PFC_PIN_GROUP(msiof2_sync_b),
|
||||
SH_PFC_PIN_GROUP(msiof2_ss1),
|
||||
SH_PFC_PIN_GROUP(msiof2_ss2),
|
||||
SH_PFC_PIN_GROUP(msiof2_txd),
|
||||
SH_PFC_PIN_GROUP(msiof2_rxd),
|
||||
SH_PFC_PIN_GROUP(msiof3_clk_a),
|
||||
SH_PFC_PIN_GROUP(msiof3_sync_a),
|
||||
SH_PFC_PIN_GROUP(msiof3_ss1_a),
|
||||
SH_PFC_PIN_GROUP(msiof3_ss2_a),
|
||||
SH_PFC_PIN_GROUP(msiof3_txd_a),
|
||||
SH_PFC_PIN_GROUP(msiof3_rxd_a),
|
||||
SH_PFC_PIN_GROUP(msiof3_clk_b),
|
||||
SH_PFC_PIN_GROUP(msiof3_sync_b),
|
||||
SH_PFC_PIN_GROUP(msiof3_ss1_b),
|
||||
SH_PFC_PIN_GROUP(msiof3_ss2_b),
|
||||
SH_PFC_PIN_GROUP(msiof3_txd_b),
|
||||
SH_PFC_PIN_GROUP(msiof3_rxd_b),
|
||||
SH_PFC_PIN_GROUP(pwm0_a),
|
||||
SH_PFC_PIN_GROUP(pwm0_b),
|
||||
SH_PFC_PIN_GROUP(pwm0_c),
|
||||
@ -1982,6 +2297,49 @@ static const char * const vin4_groups[] = {
|
||||
"vin4_clk",
|
||||
};
|
||||
|
||||
static const char * const msiof0_groups[] = {
|
||||
"msiof0_clk",
|
||||
"msiof0_sync",
|
||||
"msiof0_ss1",
|
||||
"msiof0_ss2",
|
||||
"msiof0_txd",
|
||||
"msiof0_rxd",
|
||||
};
|
||||
|
||||
static const char * const msiof1_groups[] = {
|
||||
"msiof1_clk",
|
||||
"msiof1_sync",
|
||||
"msiof1_ss1",
|
||||
"msiof1_ss2",
|
||||
"msiof1_txd",
|
||||
"msiof1_rxd",
|
||||
};
|
||||
|
||||
static const char * const msiof2_groups[] = {
|
||||
"msiof2_clk",
|
||||
"msiof2_sync_a",
|
||||
"msiof2_sync_b",
|
||||
"msiof2_ss1",
|
||||
"msiof2_ss2",
|
||||
"msiof2_txd",
|
||||
"msiof2_rxd",
|
||||
};
|
||||
|
||||
static const char * const msiof3_groups[] = {
|
||||
"msiof3_clk_a",
|
||||
"msiof3_sync_a",
|
||||
"msiof3_ss1_a",
|
||||
"msiof3_ss2_a",
|
||||
"msiof3_txd_a",
|
||||
"msiof3_rxd_a",
|
||||
"msiof3_clk_b",
|
||||
"msiof3_sync_b",
|
||||
"msiof3_ss1_b",
|
||||
"msiof3_ss2_b",
|
||||
"msiof3_txd_b",
|
||||
"msiof3_rxd_b",
|
||||
};
|
||||
|
||||
static const struct sh_pfc_function pinmux_functions[] = {
|
||||
SH_PFC_FUNCTION(audio_clk),
|
||||
SH_PFC_FUNCTION(avb0),
|
||||
@ -1996,6 +2354,10 @@ static const struct sh_pfc_function pinmux_functions[] = {
|
||||
SH_PFC_FUNCTION(i2c2),
|
||||
SH_PFC_FUNCTION(i2c3),
|
||||
SH_PFC_FUNCTION(mmc),
|
||||
SH_PFC_FUNCTION(msiof0),
|
||||
SH_PFC_FUNCTION(msiof1),
|
||||
SH_PFC_FUNCTION(msiof2),
|
||||
SH_PFC_FUNCTION(msiof3),
|
||||
SH_PFC_FUNCTION(pwm0),
|
||||
SH_PFC_FUNCTION(pwm1),
|
||||
SH_PFC_FUNCTION(pwm2),
|
||||
|
||||
@ -28,6 +28,7 @@ enum sh_pfc_model {
|
||||
SH_PFC_R8A7794,
|
||||
SH_PFC_R8A7795,
|
||||
SH_PFC_R8A7796,
|
||||
SH_PFC_R8A77965,
|
||||
SH_PFC_R8A77970,
|
||||
SH_PFC_R8A77990,
|
||||
SH_PFC_R8A77995,
|
||||
@ -808,6 +809,10 @@ static int sh_pfc_pinctrl_probe(struct udevice *dev)
|
||||
if (model == SH_PFC_R8A7796)
|
||||
priv->pfc.info = &r8a7796_pinmux_info;
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77965
|
||||
if (model == SH_PFC_R8A77965)
|
||||
priv->pfc.info = &r8a77965_pinmux_info;
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77970
|
||||
if (model == SH_PFC_R8A77970)
|
||||
priv->pfc.info = &r8a77970_pinmux_info;
|
||||
@ -869,9 +874,12 @@ static const struct udevice_id sh_pfc_pinctrl_ids[] = {
|
||||
{
|
||||
.compatible = "renesas,pfc-r8a7796",
|
||||
.data = SH_PFC_R8A7796,
|
||||
}, {
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77965
|
||||
{
|
||||
.compatible = "renesas,pfc-r8a77965",
|
||||
.data = SH_PFC_R8A7796,
|
||||
.data = SH_PFC_R8A77965,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_PINCTRL_PFC_R8A77970
|
||||
|
||||
@ -53,18 +53,32 @@ struct sh_pfc_pin_group {
|
||||
};
|
||||
|
||||
/*
|
||||
* Using union vin_data saves memory occupied by the VIN data pins.
|
||||
* VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
|
||||
* in this case.
|
||||
* Using union vin_data{,12,16} saves memory occupied by the VIN data pins.
|
||||
* VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
|
||||
* in this case. It accepts an optional 'version' argument used when the
|
||||
* same group can appear on a different set of pins.
|
||||
*/
|
||||
#define VIN_DATA_PIN_GROUP(n, s) \
|
||||
{ \
|
||||
.name = #n#s, \
|
||||
.pins = n##_pins.data##s, \
|
||||
.mux = n##_mux.data##s, \
|
||||
.nr_pins = ARRAY_SIZE(n##_pins.data##s), \
|
||||
#define VIN_DATA_PIN_GROUP(n, s, ...) \
|
||||
{ \
|
||||
.name = #n#s#__VA_ARGS__, \
|
||||
.pins = n##__VA_ARGS__##_pins.data##s, \
|
||||
.mux = n##__VA_ARGS__##_mux.data##s, \
|
||||
.nr_pins = ARRAY_SIZE(n##__VA_ARGS__##_pins.data##s), \
|
||||
}
|
||||
|
||||
union vin_data12 {
|
||||
unsigned int data12[12];
|
||||
unsigned int data10[10];
|
||||
unsigned int data8[8];
|
||||
};
|
||||
|
||||
union vin_data16 {
|
||||
unsigned int data16[16];
|
||||
unsigned int data12[12];
|
||||
unsigned int data10[10];
|
||||
unsigned int data8[8];
|
||||
};
|
||||
|
||||
union vin_data {
|
||||
unsigned int data24[24];
|
||||
unsigned int data20[20];
|
||||
@ -270,9 +284,11 @@ extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a77990_pinmux_info;
|
||||
extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
|
||||
|
||||
/* -----------------------------------------------------------------------------
|
||||
* Helper macros to create pin and port lists
|
||||
*/
|
||||
@ -341,6 +357,28 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
|
||||
#define PINMUX_IPSR_MSEL(ipsr, fn, msel) \
|
||||
PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
|
||||
|
||||
/*
|
||||
* Describe a pinmux configuration similar to PINMUX_IPSR_MSEL, but with
|
||||
* an additional select register that controls physical multiplexing
|
||||
* with another pin.
|
||||
* - ipsr: IPSR field
|
||||
* - fn: Function name, also referring to the IPSR field
|
||||
* - psel: Physical multiplexing selector
|
||||
* - msel: Module selector
|
||||
*/
|
||||
#define PINMUX_IPSR_PHYS_MSEL(ipsr, fn, psel, msel) \
|
||||
PINMUX_DATA(fn##_MARK, FN_##psel, FN_##msel, FN_##fn, FN_##ipsr)
|
||||
|
||||
/*
|
||||
* Describe a pinmux configuration in which a pin is physically multiplexed
|
||||
* with other pins.
|
||||
* - ipsr: IPSR field
|
||||
* - fn: Function name, also referring to the IPSR field
|
||||
* - psel: Physical multiplexing selector
|
||||
*/
|
||||
#define PINMUX_IPSR_PHYS(ipsr, fn, psel) \
|
||||
PINMUX_DATA(fn##_MARK, FN_##psel)
|
||||
|
||||
/*
|
||||
* Describe a pinmux configuration for a single-function pin with GPIO
|
||||
* capability.
|
||||
@ -388,12 +426,11 @@ extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
|
||||
|
||||
#define PORT_GP_CFG_11(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_10(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 10, fn, sfx, cfg)
|
||||
PORT_GP_CFG_1(bank, 10, fn, sfx, cfg)
|
||||
#define PORT_GP_11(bank, fn, sfx) PORT_GP_CFG_11(bank, fn, sfx, 0)
|
||||
|
||||
#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
|
||||
PORT_GP_CFG_10(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_11(bank, fn, sfx, cfg), \
|
||||
PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
|
||||
#define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
|
||||
|
||||
|
||||
57
dts/Kconfig
57
dts/Kconfig
@ -130,6 +130,63 @@ config OF_LIST
|
||||
device tree files (without the directory or .dtb suffix)
|
||||
separated by <space>.
|
||||
|
||||
choice
|
||||
prompt "SPL OF LIST compression"
|
||||
depends on MULTI_DTB_FIT
|
||||
default MULTI_DTB_FIT_NO_COMPRESSION
|
||||
|
||||
config MULTI_DTB_FIT_LZO
|
||||
bool "LZO"
|
||||
depends on SYS_MALLOC_F
|
||||
select LZO
|
||||
help
|
||||
Compress the FIT image containing the DTBs available for the SPL
|
||||
using LZO compression. (requires lzop on host).
|
||||
|
||||
config MULTI_DTB_FIT_GZIP
|
||||
bool "GZIP"
|
||||
depends on SYS_MALLOC_F
|
||||
select GZIP
|
||||
help
|
||||
Compress the FIT image containing the DTBs available for the SPL
|
||||
using GZIP compression. (requires gzip on host)
|
||||
|
||||
config MULTI_DTB_FIT_NO_COMPRESSION
|
||||
bool "No compression"
|
||||
help
|
||||
Do not compress the FIT image containing the DTBs available for the SPL.
|
||||
Use this options only if LZO is not available and the DTBs are very small.
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "Location of uncompressed DTBs"
|
||||
depends on (MULTI_DTB_FIT_GZIP || MULTI_DTB_FIT_LZO)
|
||||
default MULTI_DTB_FIT_DYN_ALLOC if SYS_MALLOC_F
|
||||
|
||||
config MULTI_DTB_FIT_DYN_ALLOC
|
||||
bool "Dynamically allocate the memory"
|
||||
depends on SYS_MALLOC_F
|
||||
|
||||
config MULTI_DTB_FIT_USER_DEFINED_AREA
|
||||
bool "User-defined location"
|
||||
endchoice
|
||||
|
||||
config MULTI_DTB_FIT_UNCOMPRESS_SZ
|
||||
hex "Size of memory reserved to uncompress the DTBs"
|
||||
depends on (MULTI_DTB_FIT_GZIP || MULTI_DTB_FIT_LZO)
|
||||
default 0x8000
|
||||
help
|
||||
This is the size of this area where the DTBs are uncompressed.
|
||||
If this area is dynamically allocated, make sure that
|
||||
SYS_MALLOC_F_LEN is big enough to contain it.
|
||||
|
||||
config MULTI_DTB_FIT_USER_DEF_ADDR
|
||||
hex "Address of memory where dtbs are uncompressed"
|
||||
depends on MULTI_DTB_FIT_USER_DEFINED_AREA
|
||||
help
|
||||
the FIT image containing the DTBs is uncompressed in an area defined
|
||||
at compilation time. This is the address of this area. It must be
|
||||
aligned on 2-byte boundary.
|
||||
|
||||
config DTB_RESELECT
|
||||
bool "Support swapping dtbs at a later point in boot"
|
||||
|
||||
@ -16,7 +16,4 @@
|
||||
#define CONFIG_BOOTM_RTEMS 1
|
||||
#define CONFIG_BOOTM_VXWORKS 1
|
||||
|
||||
#define CONFIG_GZIP 1
|
||||
#define CONFIG_ZLIB 1
|
||||
|
||||
#endif
|
||||
|
||||
@ -39,7 +39,8 @@
|
||||
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"bootm_size=0x10000000\0"
|
||||
"bootm_size=0x10000000\0" \
|
||||
"usb_pgood_delay=2000\0"
|
||||
|
||||
/* SPL support */
|
||||
#define CONFIG_SPL_TEXT_BASE 0xe6300000
|
||||
|
||||
@ -1,10 +1,6 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7790_CPG_MSSR_H__
|
||||
|
||||
@ -1,10 +1,6 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7791_CPG_MSSR_H__
|
||||
|
||||
@ -1,10 +1,6 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__
|
||||
|
||||
@ -1,16 +1,8 @@
|
||||
/*
|
||||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* r8a7793 clock definition
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7793_H__
|
||||
|
||||
@ -1,10 +1,6 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7793_CPG_MSSR_H__
|
||||
|
||||
@ -1,11 +1,7 @@
|
||||
/*
|
||||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation
|
||||
* Copyright 2013 Ideas On Board SPRL
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7794_H__
|
||||
|
||||
@ -1,10 +1,6 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__
|
||||
|
||||
@ -1,10 +1,6 @@
|
||||
/*
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
* Copyright (C) 2015 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
|
||||
@ -54,7 +50,7 @@
|
||||
#define R8A7795_CLK_CANFD 39
|
||||
#define R8A7795_CLK_HDMI 40
|
||||
#define R8A7795_CLK_CSI0 41
|
||||
#define R8A7795_CLK_CSIREF 42
|
||||
/* CLK_CSIREF was removed */
|
||||
#define R8A7795_CLK_CP 43
|
||||
#define R8A7795_CLK_CPEX 44
|
||||
#define R8A7795_CLK_R 45
|
||||
|
||||
@ -1,10 +1,6 @@
|
||||
/*
|
||||
* Copyright (C) 2016 Renesas Electronics Corp.
|
||||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
* Copyright (C) 2016 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
|
||||
@ -60,7 +56,7 @@
|
||||
#define R8A7796_CLK_CANFD 45
|
||||
#define R8A7796_CLK_HDMI 46
|
||||
#define R8A7796_CLK_CSI0 47
|
||||
#define R8A7796_CLK_CSIREF 48
|
||||
/* CLK_CSIREF was removed */
|
||||
#define R8A7796_CLK_CP 49
|
||||
#define R8A7796_CLK_CPEX 50
|
||||
#define R8A7796_CLK_R 51
|
||||
|
||||
@ -1,10 +1,6 @@
|
||||
/*
|
||||
* Copyright (C) 2017 Glider bvba
|
||||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
* Copyright (C) 2017 Glider bvba
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__
|
||||
@ -39,8 +35,8 @@
|
||||
#define R8A77995_CLK_CRD2 24
|
||||
#define R8A77995_CLK_SD0H 25
|
||||
#define R8A77995_CLK_SD0 26
|
||||
#define R8A77995_CLK_SSP2 27
|
||||
#define R8A77995_CLK_SSP1 28
|
||||
/* CLK_SSP2 was removed */
|
||||
/* CLK_SSP1 was removed */
|
||||
#define R8A77995_CLK_RPC 29
|
||||
#define R8A77995_CLK_RPCD2 30
|
||||
#define R8A77995_CLK_ZA2 31
|
||||
@ -53,5 +49,6 @@
|
||||
#define R8A77995_CLK_LV0 38
|
||||
#define R8A77995_CLK_LV1 39
|
||||
#define R8A77995_CLK_CP 40
|
||||
#define R8A77995_CLK_CPEX 41
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A77995_CPG_MSSR_H__ */
|
||||
|
||||
@ -917,6 +917,26 @@ struct display_timing {
|
||||
int fdtdec_decode_display_timing(const void *blob, int node, int index,
|
||||
struct display_timing *config);
|
||||
|
||||
/**
|
||||
* fdtdec_setup_mem_size_base_fdt() - decode and setup gd->ram_size and
|
||||
* gd->ram_start
|
||||
*
|
||||
* Decode the /memory 'reg' property to determine the size and start of the
|
||||
* first memory bank, populate the global data with the size and start of the
|
||||
* first bank of memory.
|
||||
*
|
||||
* This function should be called from a boards dram_init(). This helper
|
||||
* function allows for boards to query the device tree for DRAM size and start
|
||||
* address instead of hard coding the value in the case where the memory size
|
||||
* and start address cannot be detected automatically.
|
||||
*
|
||||
* @param blob FDT blob
|
||||
*
|
||||
* @return 0 if OK, -EINVAL if the /memory node or reg property is missing or
|
||||
* invalid
|
||||
*/
|
||||
int fdtdec_setup_mem_size_base_fdt(const void *blob);
|
||||
|
||||
/**
|
||||
* fdtdec_setup_mem_size_base() - decode and setup gd->ram_size and
|
||||
* gd->ram_start
|
||||
@ -935,6 +955,25 @@ int fdtdec_decode_display_timing(const void *blob, int node, int index,
|
||||
*/
|
||||
int fdtdec_setup_mem_size_base(void);
|
||||
|
||||
/**
|
||||
* fdtdec_setup_memory_banksize_fdt() - decode and populate gd->bd->bi_dram
|
||||
*
|
||||
* Decode the /memory 'reg' property to determine the address and size of the
|
||||
* memory banks. Use this data to populate the global data board info with the
|
||||
* phys address and size of memory banks.
|
||||
*
|
||||
* This function should be called from a boards dram_init_banksize(). This
|
||||
* helper function allows for boards to query the device tree for memory bank
|
||||
* information instead of hard coding the information in cases where it cannot
|
||||
* be detected automatically.
|
||||
*
|
||||
* @param blob FDT blob
|
||||
*
|
||||
* @return 0 if OK, -EINVAL if the /memory node or reg property is missing or
|
||||
* invalid
|
||||
*/
|
||||
int fdtdec_setup_memory_banksize_fdt(const void *blob);
|
||||
|
||||
/**
|
||||
* fdtdec_setup_memory_banksize() - decode and populate gd->bd->bi_dram
|
||||
*
|
||||
|
||||
13
lib/Kconfig
13
lib/Kconfig
@ -301,6 +301,19 @@ config LZO
|
||||
help
|
||||
This enables support for LZO compression algorithm.r
|
||||
|
||||
config GZIP
|
||||
bool "Enable gzip decompression support for SPL build"
|
||||
select ZLIB
|
||||
default y
|
||||
help
|
||||
This enables support for GZIP compression algorithm.
|
||||
|
||||
config ZLIB
|
||||
bool
|
||||
default y
|
||||
help
|
||||
This enables ZLIB compression lib.
|
||||
|
||||
config SPL_LZ4
|
||||
bool "Enable LZ4 decompression support in SPL"
|
||||
help
|
||||
|
||||
50
lib/fdtdec.c
50
lib/fdtdec.c
@ -1088,18 +1088,18 @@ int fdtdec_decode_display_timing(const void *blob, int parent, int index,
|
||||
return ret;
|
||||
}
|
||||
|
||||
int fdtdec_setup_mem_size_base(void)
|
||||
int fdtdec_setup_mem_size_base_fdt(const void *blob)
|
||||
{
|
||||
int ret, mem;
|
||||
struct fdt_resource res;
|
||||
|
||||
mem = fdt_path_offset(gd->fdt_blob, "/memory");
|
||||
mem = fdt_path_offset(blob, "/memory");
|
||||
if (mem < 0) {
|
||||
debug("%s: Missing /memory node\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = fdt_get_resource(gd->fdt_blob, mem, "reg", 0, &res);
|
||||
ret = fdt_get_resource(blob, mem, "reg", 0, &res);
|
||||
if (ret != 0) {
|
||||
debug("%s: Unable to decode first memory bank\n", __func__);
|
||||
return -EINVAL;
|
||||
@ -1113,38 +1113,43 @@ int fdtdec_setup_mem_size_base(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
int fdtdec_setup_mem_size_base(void)
|
||||
{
|
||||
return fdtdec_setup_mem_size_base_fdt(gd->fdt_blob);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_NR_DRAM_BANKS)
|
||||
|
||||
static int get_next_memory_node(const void *blob, int mem)
|
||||
{
|
||||
do {
|
||||
mem = fdt_node_offset_by_prop_value(gd->fdt_blob, mem,
|
||||
mem = fdt_node_offset_by_prop_value(blob, mem,
|
||||
"device_type", "memory", 7);
|
||||
} while (!fdtdec_get_is_enabled(blob, mem));
|
||||
|
||||
return mem;
|
||||
}
|
||||
|
||||
int fdtdec_setup_memory_banksize(void)
|
||||
int fdtdec_setup_memory_banksize_fdt(const void *blob)
|
||||
{
|
||||
int bank, ret, mem, reg = 0;
|
||||
struct fdt_resource res;
|
||||
|
||||
mem = get_next_memory_node(gd->fdt_blob, -1);
|
||||
mem = get_next_memory_node(blob, -1);
|
||||
if (mem < 0) {
|
||||
debug("%s: Missing /memory node\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
|
||||
ret = fdt_get_resource(gd->fdt_blob, mem, "reg", reg++, &res);
|
||||
ret = fdt_get_resource(blob, mem, "reg", reg++, &res);
|
||||
if (ret == -FDT_ERR_NOTFOUND) {
|
||||
reg = 0;
|
||||
mem = get_next_memory_node(gd->fdt_blob, mem);
|
||||
mem = get_next_memory_node(blob, mem);
|
||||
if (mem == -FDT_ERR_NOTFOUND)
|
||||
break;
|
||||
|
||||
ret = fdt_get_resource(gd->fdt_blob, mem, "reg", reg++, &res);
|
||||
ret = fdt_get_resource(blob, mem, "reg", reg++, &res);
|
||||
if (ret == -FDT_ERR_NOTFOUND)
|
||||
break;
|
||||
}
|
||||
@ -1164,6 +1169,12 @@ int fdtdec_setup_memory_banksize(void)
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int fdtdec_setup_memory_banksize(void)
|
||||
{
|
||||
return fdtdec_setup_memory_banksize_fdt(gd->fdt_blob);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
#if CONFIG_IS_ENABLED(MULTI_DTB_FIT)
|
||||
@ -1171,17 +1182,22 @@ int fdtdec_setup_memory_banksize(void)
|
||||
CONFIG_IS_ENABLED(MULTI_DTB_FIT_LZO)
|
||||
static int uncompress_blob(const void *src, ulong sz_src, void **dstp)
|
||||
{
|
||||
size_t sz_out = CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ;
|
||||
size_t sz_out = CONFIG_VAL(MULTI_DTB_FIT_UNCOMPRESS_SZ);
|
||||
bool gzip = 0, lzo = 0;
|
||||
ulong sz_in = sz_src;
|
||||
void *dst;
|
||||
int rc;
|
||||
|
||||
if (CONFIG_IS_ENABLED(GZIP))
|
||||
if (gzip_parse_header(src, sz_in) < 0)
|
||||
return -1;
|
||||
if (gzip_parse_header(src, sz_in) >= 0)
|
||||
gzip = 1;
|
||||
if (CONFIG_IS_ENABLED(LZO))
|
||||
if (!lzop_is_valid_header(src))
|
||||
return -EBADMSG;
|
||||
if (!gzip && lzop_is_valid_header(src))
|
||||
lzo = 1;
|
||||
|
||||
if (!gzip && !lzo)
|
||||
return -EBADMSG;
|
||||
|
||||
|
||||
if (CONFIG_IS_ENABLED(MULTI_DTB_FIT_DYN_ALLOC)) {
|
||||
dst = malloc(sz_out);
|
||||
@ -1197,10 +1213,12 @@ static int uncompress_blob(const void *src, ulong sz_src, void **dstp)
|
||||
# endif
|
||||
}
|
||||
|
||||
if (CONFIG_IS_ENABLED(GZIP))
|
||||
if (CONFIG_IS_ENABLED(GZIP) && gzip)
|
||||
rc = gunzip(dst, sz_out, (u8 *)src, &sz_in);
|
||||
else if (CONFIG_IS_ENABLED(LZO))
|
||||
else if (CONFIG_IS_ENABLED(LZO) && lzo)
|
||||
rc = lzop_decompress(src, sz_in, dst, &sz_out);
|
||||
else
|
||||
hang();
|
||||
|
||||
if (rc < 0) {
|
||||
/* not a valid compressed blob */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user