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LPC2292 SODIMM port coding style cleanup.

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This commit is contained in:
Wolfgang Denk 2007-01-30 00:50:40 +01:00 committed by Wolfgang Denk
parent 6bd2447ee4
commit f8db84f132
10 changed files with 409 additions and 369 deletions
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43
CHANGELOG
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@ -1,3 +1,46 @@
commit 6bd2447ee47ee23c18d2b3c7ccd5a20f7626f5b3
Author: Gary Jennejohn <garyj@pollux.denx.de>
Date: Wed Jan 24 12:16:56 2007 +0100
Add port for the lpc2292sodimm evaluation board from EmbeddedArtists
commit 2daf046ba627f85f44195815778140039636244e
Author: Bartlomiej Sieka <tur@semihalf.com>
Date: Tue Jan 23 17:22:06 2007 +0100
[iDMR] Add MTD and JFFS2 support, also add default partition definition.
commit f7db33101fbc9c8f0a10738ce87034875a17aeb9
Author: Bartlomiej Sieka <tur@semihalf.com>
Date: Tue Jan 23 14:21:14 2007 +0100
[iDMR] Flash driver on initialisation write-protects some sectors,
currently sectors 0-3. Sector 3 does not need to be protected, though
(U-boot occupies sectors 0-1 and the environment sector 2). This commit
fixes this, i.e., only sectors 0-2 are protected.
commit 0ed47bb119cd2c4c16edb2548789148f9e6dc9de
Author: Bartlomiej Sieka <tur@semihalf.com>
Date: Tue Jan 23 14:11:22 2007 +0100
[iDMR] Using MII-related commands on iDRM board doesn't work now (e.g.,
"mii device" results in "Unexpected exception"). Fixing this properly
requires some clean-up in the FEC drivers infrastructure for ColdFire, so
this commit disables MII commads for now.
commit 363d1d8f9c99b63daef81f5985cab3fc00edde5c
Author: Bartlomiej Sieka <tur@semihalf.com>
Date: Tue Jan 23 13:25:22 2007 +0100
[ColdFire MCF5271 family] Add CPU detection based on the value of Chip
Identification Register (CIR).
commit a4012396645533aef218354eeba754dff0deace8
Author: Wolfgang Denk <wd@pollux.denx.de>
Date: Fri Jan 19 23:08:39 2007 +0100
Minor code cleanup.
commit f539b7ba7d7ef6dd187c8209609001cb1cd95e39
Author: Heiko Schocher <hs@pollux.denx.de>
Date: Fri Jan 19 19:57:10 2007 +0100

1
board/lpc2292sodimm/config.mk
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@ -28,4 +28,3 @@
#address where u-boot will be relocated
#TEXT_BASE = 0x0
TEXT_BASE = 0x81500000

15
board/lpc2292sodimm/eth.c
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@ -314,6 +314,7 @@ static unsigned char next_pointer_msb;
static unsigned char buffer[ENC_MAX_FRM_LEN];
static int rxResetCounter = 0;
#define RX_RESET_COUNTER 1000;
/*-----------------------------------------------------------------------------
@ -400,8 +401,7 @@ static void encReceiverResetCallback(void)
*/
int eth_rx (void)
{
if(rxResetCounter > 0 && --rxResetCounter == 0)
{
if (rxResetCounter > 0 && --rxResetCounter == 0) {
encReceiverResetCallback ();
}
@ -521,7 +521,8 @@ static void encRx(void)
pkt_cnt = m_nic_read (CTL_REG_EPKTCNT);
/* switch to bank 0 */
m_nic_bfc(CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
m_nic_bfc (CTL_REG_ECON1,
(ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
if (copy_len == 0) {
eir_reg = m_nic_read (CTL_REG_EIR);
@ -643,8 +644,7 @@ static void encReadBuff(unsigned short length, unsigned char *pBuff)
spi_unlock ();
}
static void encWriteBuff(unsigned short length,
unsigned char *pBuff)
static void encWriteBuff (unsigned short length, unsigned char *pBuff)
{
spi_lock ();
enc_cfg_spi ();
@ -752,6 +752,7 @@ static void encInit(unsigned char *pEthAddr)
/* Wait for Oscillator Start-up Timer (OST). */
while ((m_nic_read (CTL_REG_ESTAT) & ENC_ESTAT_CLKRDY) == 0) {
static int cnt = 0;
if (cnt++ >= 1000) {
cnt = 0;
}
@ -787,8 +788,8 @@ static void encInit(unsigned char *pEthAddr)
/* configure pad, tx-crc and duplex */
/* TODO maybe enable FRMLNEN */
m_nic_write_retry(CTL_REG_MACON3, (ENC_MACON3_PADCFG0|ENC_MACON3_TXCRCEN),
10);
m_nic_write_retry (CTL_REG_MACON3,
(ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN), 10);
/* set maximum frame length */
m_nic_write_retry (CTL_REG_MAMXFLL, (ENC_MAX_FRM_LEN & 0xff), 10);

1
board/lpc2292sodimm/flash.c
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@ -350,7 +350,6 @@ int write_buff_sst (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
src_org++;
}
return ret;
}

4
board/lpc2292sodimm/spi.h
View File

@ -79,6 +79,4 @@ static inline void spi_set_cfg(unsigned char phase,
PUT8(S0SPCR, v);
}
#endif
#endif /* SPI_H */