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85xx: Using proper I2C source clock divider for MPC8544

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The MPC8544 RM incorrect shows the SEC_CFG bit in PORDEVSR2 as being
bit 26, instead it should be bit 28.  This caused in incorrect
interpretation of the i2c_clk which is the same as the SEC clk on
MPC8544.  The SEC clk is controlled by cfg_sec_freq that is reported
in PORDEVSR2.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2008-10-16 21:58:50 -05:00 committed by Wolfgang Denk
parent 42653b826a
commit f7d190b1c0
1 changed files with 1 additions and 1 deletions
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2
include/asm-ppc/immap_85xx.h
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@ -1579,7 +1579,7 @@ typedef struct ccsr_gur {
#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
uint pordevsr2; /* 0xe0014 - POR I/O device status regsiter 2 */
#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000020
#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
char res1[8];
uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
char res2[12];